diff options
Diffstat (limited to 'include/asm-m68k/m5282.h')
| -rw-r--r-- | include/asm-m68k/m5282.h | 411 |
1 files changed, 194 insertions, 217 deletions
diff --git a/include/asm-m68k/m5282.h b/include/asm-m68k/m5282.h index f6a6b04..d59a8b2 100644 --- a/include/asm-m68k/m5282.h +++ b/include/asm-m68k/m5282.h @@ -125,112 +125,112 @@ /* General Purpose I/O Module GPIO */ -#define MCFGPIO_PORTA (*(vu_char *) (CFG_MBAR+0x100000)) -#define MCFGPIO_PORTB (*(vu_char *) (CFG_MBAR+0x100001)) -#define MCFGPIO_PORTC (*(vu_char *) (CFG_MBAR+0x100002)) -#define MCFGPIO_PORTD (*(vu_char *) (CFG_MBAR+0x100003)) -#define MCFGPIO_PORTE (*(vu_char *) (CFG_MBAR+0x100004)) -#define MCFGPIO_PORTF (*(vu_char *) (CFG_MBAR+0x100005)) -#define MCFGPIO_PORTG (*(vu_char *) (CFG_MBAR+0x100006)) -#define MCFGPIO_PORTH (*(vu_char *) (CFG_MBAR+0x100007)) -#define MCFGPIO_PORTJ (*(vu_char *) (CFG_MBAR+0x100008)) -#define MCFGPIO_PORTDD (*(vu_char *) (CFG_MBAR+0x100009)) -#define MCFGPIO_PORTEH (*(vu_char *) (CFG_MBAR+0x10000A)) -#define MCFGPIO_PORTEL (*(vu_char *) (CFG_MBAR+0x10000B)) -#define MCFGPIO_PORTAS (*(vu_char *) (CFG_MBAR+0x10000C)) -#define MCFGPIO_PORTQS (*(vu_char *) (CFG_MBAR+0x10000D)) -#define MCFGPIO_PORTSD (*(vu_char *) (CFG_MBAR+0x10000E)) -#define MCFGPIO_PORTTC (*(vu_char *) (CFG_MBAR+0x10000F)) -#define MCFGPIO_PORTTD (*(vu_char *) (CFG_MBAR+0x100010)) -#define MCFGPIO_PORTUA (*(vu_char *) (CFG_MBAR+0x100011)) - -#define MCFGPIO_DDRA (*(vu_char *) (CFG_MBAR+0x100014)) -#define MCFGPIO_DDRB (*(vu_char *) (CFG_MBAR+0x100015)) -#define MCFGPIO_DDRC (*(vu_char *) (CFG_MBAR+0x100016)) -#define MCFGPIO_DDRD (*(vu_char *) (CFG_MBAR+0x100017)) -#define MCFGPIO_DDRE (*(vu_char *) (CFG_MBAR+0x100018)) -#define MCFGPIO_DDRF (*(vu_char *) (CFG_MBAR+0x100019)) -#define MCFGPIO_DDRG (*(vu_char *) (CFG_MBAR+0x10001A)) -#define MCFGPIO_DDRH (*(vu_char *) (CFG_MBAR+0x10001B)) -#define MCFGPIO_DDRJ (*(vu_char *) (CFG_MBAR+0x10001C)) -#define MCFGPIO_DDRDD (*(vu_char *) (CFG_MBAR+0x10001D)) -#define MCFGPIO_DDREH (*(vu_char *) (CFG_MBAR+0x10001E)) -#define MCFGPIO_DDREL (*(vu_char *) (CFG_MBAR+0x10001F)) -#define MCFGPIO_DDRAS (*(vu_char *) (CFG_MBAR+0x100020)) -#define MCFGPIO_DDRQS (*(vu_char *) (CFG_MBAR+0x100021)) -#define MCFGPIO_DDRSD (*(vu_char *) (CFG_MBAR+0x100022)) -#define MCFGPIO_DDRTC (*(vu_char *) (CFG_MBAR+0x100023)) -#define MCFGPIO_DDRTD (*(vu_char *) (CFG_MBAR+0x100024)) -#define MCFGPIO_DDRUA (*(vu_char *) (CFG_MBAR+0x100025)) - -#define MCFGPIO_PORTAP (*(vu_char *) (CFG_MBAR+0x100028)) -#define MCFGPIO_PORTBP (*(vu_char *) (CFG_MBAR+0x100029)) -#define MCFGPIO_PORTCP (*(vu_char *) (CFG_MBAR+0x10002A)) -#define MCFGPIO_PORTDP (*(vu_char *) (CFG_MBAR+0x10002B)) -#define MCFGPIO_PORTEP (*(vu_char *) (CFG_MBAR+0x10002C)) -#define MCFGPIO_PORTFP (*(vu_char *) (CFG_MBAR+0x10002D)) -#define MCFGPIO_PORTGP (*(vu_char *) (CFG_MBAR+0x10002E)) -#define MCFGPIO_PORTHP (*(vu_char *) (CFG_MBAR+0x10002F)) -#define MCFGPIO_PORTJP (*(vu_char *) (CFG_MBAR+0x100030)) -#define MCFGPIO_PORTDDP (*(vu_char *) (CFG_MBAR+0x100031)) -#define MCFGPIO_PORTEHP (*(vu_char *) (CFG_MBAR+0x100032)) -#define MCFGPIO_PORTELP (*(vu_char *) (CFG_MBAR+0x100033)) -#define MCFGPIO_PORTASP (*(vu_char *) (CFG_MBAR+0x100034)) -#define MCFGPIO_PORTQSP (*(vu_char *) (CFG_MBAR+0x100035)) -#define MCFGPIO_PORTSDP (*(vu_char *) (CFG_MBAR+0x100036)) -#define MCFGPIO_PORTTCP (*(vu_char *) (CFG_MBAR+0x100037)) -#define MCFGPIO_PORTTDP (*(vu_char *) (CFG_MBAR+0x100038)) -#define MCFGPIO_PORTUAP (*(vu_char *) (CFG_MBAR+0x100039)) - -#define MCFGPIO_SETA (*(vu_char *) (CFG_MBAR+0x100028)) -#define MCFGPIO_SETB (*(vu_char *) (CFG_MBAR+0x100029)) -#define MCFGPIO_SETC (*(vu_char *) (CFG_MBAR+0x10002A)) -#define MCFGPIO_SETD (*(vu_char *) (CFG_MBAR+0x10002B)) -#define MCFGPIO_SETE (*(vu_char *) (CFG_MBAR+0x10002C)) -#define MCFGPIO_SETF (*(vu_char *) (CFG_MBAR+0x10002D)) -#define MCFGPIO_SETG (*(vu_char *) (CFG_MBAR+0x10002E)) -#define MCFGPIO_SETH (*(vu_char *) (CFG_MBAR+0x10002F)) -#define MCFGPIO_SETJ (*(vu_char *) (CFG_MBAR+0x100030)) -#define MCFGPIO_SETDD (*(vu_char *) (CFG_MBAR+0x100031)) -#define MCFGPIO_SETEH (*(vu_char *) (CFG_MBAR+0x100032)) -#define MCFGPIO_SETEL (*(vu_char *) (CFG_MBAR+0x100033)) -#define MCFGPIO_SETAS (*(vu_char *) (CFG_MBAR+0x100034)) -#define MCFGPIO_SETQS (*(vu_char *) (CFG_MBAR+0x100035)) -#define MCFGPIO_SETSD (*(vu_char *) (CFG_MBAR+0x100036)) -#define MCFGPIO_SETTC (*(vu_char *) (CFG_MBAR+0x100037)) -#define MCFGPIO_SETTD (*(vu_char *) (CFG_MBAR+0x100038)) -#define MCFGPIO_SETUA (*(vu_char *) (CFG_MBAR+0x100039)) - -#define MCFGPIO_CLRA (*(vu_char *) (CFG_MBAR+0x10003C)) -#define MCFGPIO_CLRB (*(vu_char *) (CFG_MBAR+0x10003D)) -#define MCFGPIO_CLRC (*(vu_char *) (CFG_MBAR+0x10003E)) -#define MCFGPIO_CLRD (*(vu_char *) (CFG_MBAR+0x10003F)) -#define MCFGPIO_CLRE (*(vu_char *) (CFG_MBAR+0x100040)) -#define MCFGPIO_CLRF (*(vu_char *) (CFG_MBAR+0x100041)) -#define MCFGPIO_CLRG (*(vu_char *) (CFG_MBAR+0x100042)) -#define MCFGPIO_CLRH (*(vu_char *) (CFG_MBAR+0x100043)) -#define MCFGPIO_CLRJ (*(vu_char *) (CFG_MBAR+0x100044)) -#define MCFGPIO_CLRDD (*(vu_char *) (CFG_MBAR+0x100045)) -#define MCFGPIO_CLREH (*(vu_char *) (CFG_MBAR+0x100046)) -#define MCFGPIO_CLREL (*(vu_char *) (CFG_MBAR+0x100047)) -#define MCFGPIO_CLRAS (*(vu_char *) (CFG_MBAR+0x100048)) -#define MCFGPIO_CLRQS (*(vu_char *) (CFG_MBAR+0x100049)) -#define MCFGPIO_CLRSD (*(vu_char *) (CFG_MBAR+0x10004A)) -#define MCFGPIO_CLRTC (*(vu_char *) (CFG_MBAR+0x10004B)) -#define MCFGPIO_CLRTD (*(vu_char *) (CFG_MBAR+0x10004C)) -#define MCFGPIO_CLRUA (*(vu_char *) (CFG_MBAR+0x10004D)) - -#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_MBAR+0x100050)) -#define MCFGPIO_PFPAR (*(vu_char *) (CFG_MBAR+0x100051)) -#define MCFGPIO_PEPAR (*(vu_short *)(CFG_MBAR+0x100052)) -#define MCFGPIO_PJPAR (*(vu_char *) (CFG_MBAR+0x100054)) -#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_MBAR+0x100055)) -#define MCFGPIO_PASPAR (*(vu_short *)(CFG_MBAR+0x100056)) -#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_MBAR+0x100058)) -#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_MBAR+0x100059)) -#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_MBAR+0x10005A)) -#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_MBAR+0x10005B)) -#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_MBAR+0x10005C)) +#define MCFGPIO_PORTA (*(vu_char *) (CONFIG_SYS_MBAR+0x100000)) +#define MCFGPIO_PORTB (*(vu_char *) (CONFIG_SYS_MBAR+0x100001)) +#define MCFGPIO_PORTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100002)) +#define MCFGPIO_PORTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100003)) +#define MCFGPIO_PORTE (*(vu_char *) (CONFIG_SYS_MBAR+0x100004)) +#define MCFGPIO_PORTF (*(vu_char *) (CONFIG_SYS_MBAR+0x100005)) +#define MCFGPIO_PORTG (*(vu_char *) (CONFIG_SYS_MBAR+0x100006)) +#define MCFGPIO_PORTH (*(vu_char *) (CONFIG_SYS_MBAR+0x100007)) +#define MCFGPIO_PORTJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100008)) +#define MCFGPIO_PORTDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100009)) +#define MCFGPIO_PORTEH (*(vu_char *) (CONFIG_SYS_MBAR+0x10000A)) +#define MCFGPIO_PORTEL (*(vu_char *) (CONFIG_SYS_MBAR+0x10000B)) +#define MCFGPIO_PORTAS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000C)) +#define MCFGPIO_PORTQS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000D)) +#define MCFGPIO_PORTSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10000E)) +#define MCFGPIO_PORTTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10000F)) +#define MCFGPIO_PORTTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100010)) +#define MCFGPIO_PORTUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100011)) + +#define MCFGPIO_DDRA (*(vu_char *) (CONFIG_SYS_MBAR+0x100014)) +#define MCFGPIO_DDRB (*(vu_char *) (CONFIG_SYS_MBAR+0x100015)) +#define MCFGPIO_DDRC (*(vu_char *) (CONFIG_SYS_MBAR+0x100016)) +#define MCFGPIO_DDRD (*(vu_char *) (CONFIG_SYS_MBAR+0x100017)) +#define MCFGPIO_DDRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100018)) +#define MCFGPIO_DDRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100019)) +#define MCFGPIO_DDRG (*(vu_char *) (CONFIG_SYS_MBAR+0x10001A)) +#define MCFGPIO_DDRH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001B)) +#define MCFGPIO_DDRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x10001C)) +#define MCFGPIO_DDRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x10001D)) +#define MCFGPIO_DDREH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001E)) +#define MCFGPIO_DDREL (*(vu_char *) (CONFIG_SYS_MBAR+0x10001F)) +#define MCFGPIO_DDRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100020)) +#define MCFGPIO_DDRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100021)) +#define MCFGPIO_DDRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100022)) +#define MCFGPIO_DDRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100023)) +#define MCFGPIO_DDRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100024)) +#define MCFGPIO_DDRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100025)) + +#define MCFGPIO_PORTAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100028)) +#define MCFGPIO_PORTBP (*(vu_char *) (CONFIG_SYS_MBAR+0x100029)) +#define MCFGPIO_PORTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A)) +#define MCFGPIO_PORTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B)) +#define MCFGPIO_PORTEP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C)) +#define MCFGPIO_PORTFP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D)) +#define MCFGPIO_PORTGP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E)) +#define MCFGPIO_PORTHP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F)) +#define MCFGPIO_PORTJP (*(vu_char *) (CONFIG_SYS_MBAR+0x100030)) +#define MCFGPIO_PORTDDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100031)) +#define MCFGPIO_PORTEHP (*(vu_char *) (CONFIG_SYS_MBAR+0x100032)) +#define MCFGPIO_PORTELP (*(vu_char *) (CONFIG_SYS_MBAR+0x100033)) +#define MCFGPIO_PORTASP (*(vu_char *) (CONFIG_SYS_MBAR+0x100034)) +#define MCFGPIO_PORTQSP (*(vu_char *) (CONFIG_SYS_MBAR+0x100035)) +#define MCFGPIO_PORTSDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100036)) +#define MCFGPIO_PORTTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x100037)) +#define MCFGPIO_PORTTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100038)) +#define MCFGPIO_PORTUAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100039)) + +#define MCFGPIO_SETA (*(vu_char *) (CONFIG_SYS_MBAR+0x100028)) +#define MCFGPIO_SETB (*(vu_char *) (CONFIG_SYS_MBAR+0x100029)) +#define MCFGPIO_SETC (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A)) +#define MCFGPIO_SETD (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B)) +#define MCFGPIO_SETE (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C)) +#define MCFGPIO_SETF (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D)) +#define MCFGPIO_SETG (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E)) +#define MCFGPIO_SETH (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F)) +#define MCFGPIO_SETJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100030)) +#define MCFGPIO_SETDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100031)) +#define MCFGPIO_SETEH (*(vu_char *) (CONFIG_SYS_MBAR+0x100032)) +#define MCFGPIO_SETEL (*(vu_char *) (CONFIG_SYS_MBAR+0x100033)) +#define MCFGPIO_SETAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100034)) +#define MCFGPIO_SETQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100035)) +#define MCFGPIO_SETSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100036)) +#define MCFGPIO_SETTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100037)) +#define MCFGPIO_SETTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100038)) +#define MCFGPIO_SETUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100039)) + +#define MCFGPIO_CLRA (*(vu_char *) (CONFIG_SYS_MBAR+0x10003C)) +#define MCFGPIO_CLRB (*(vu_char *) (CONFIG_SYS_MBAR+0x10003D)) +#define MCFGPIO_CLRC (*(vu_char *) (CONFIG_SYS_MBAR+0x10003E)) +#define MCFGPIO_CLRD (*(vu_char *) (CONFIG_SYS_MBAR+0x10003F)) +#define MCFGPIO_CLRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100040)) +#define MCFGPIO_CLRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100041)) +#define MCFGPIO_CLRG (*(vu_char *) (CONFIG_SYS_MBAR+0x100042)) +#define MCFGPIO_CLRH (*(vu_char *) (CONFIG_SYS_MBAR+0x100043)) +#define MCFGPIO_CLRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100044)) +#define MCFGPIO_CLRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100045)) +#define MCFGPIO_CLREH (*(vu_char *) (CONFIG_SYS_MBAR+0x100046)) +#define MCFGPIO_CLREL (*(vu_char *) (CONFIG_SYS_MBAR+0x100047)) +#define MCFGPIO_CLRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100048)) +#define MCFGPIO_CLRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100049)) +#define MCFGPIO_CLRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004A)) +#define MCFGPIO_CLRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10004B)) +#define MCFGPIO_CLRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004C)) +#define MCFGPIO_CLRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x10004D)) + +#define MCFGPIO_PBCDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100050)) +#define MCFGPIO_PFPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100051)) +#define MCFGPIO_PEPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100052)) +#define MCFGPIO_PJPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100054)) +#define MCFGPIO_PSDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100055)) +#define MCFGPIO_PASPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100056)) +#define MCFGPIO_PEHLPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100058)) +#define MCFGPIO_PQSPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100059)) +#define MCFGPIO_PTCPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005A)) +#define MCFGPIO_PTDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005B)) +#define MCFGPIO_PUAPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005C)) /* Bit level definitions and macros */ #define MCFGPIO_PORT7 (0x80) @@ -327,25 +327,25 @@ /* System Conrol Module SCM */ -#define MCFSCM_RAMBAR (*(vu_long *) (CFG_MBAR+0x00000008)) -#define MCFSCM_CRSR (*(vu_char *) (CFG_MBAR+0x00000010)) -#define MCFSCM_CWCR (*(vu_char *) (CFG_MBAR+0x00000011)) -#define MCFSCM_LPICR (*(vu_char *) (CFG_MBAR+0x00000012)) -#define MCFSCM_CWSR (*(vu_char *) (CFG_MBAR+0x00000013)) - -#define MCFSCM_MPARK (*(vu_long *) (CFG_MBAR+0x0000001C)) -#define MCFSCM_MPR (*(vu_char *) (CFG_MBAR+0x00000020)) -#define MCFSCM_PACR0 (*(vu_char *) (CFG_MBAR+0x00000024)) -#define MCFSCM_PACR1 (*(vu_char *) (CFG_MBAR+0x00000025)) -#define MCFSCM_PACR2 (*(vu_char *) (CFG_MBAR+0x00000026)) -#define MCFSCM_PACR3 (*(vu_char *) (CFG_MBAR+0x00000027)) -#define MCFSCM_PACR4 (*(vu_char *) (CFG_MBAR+0x00000028)) -#define MCFSCM_PACR5 (*(vu_char *) (CFG_MBAR+0x0000002A)) -#define MCFSCM_PACR6 (*(vu_char *) (CFG_MBAR+0x0000002B)) -#define MCFSCM_PACR7 (*(vu_char *) (CFG_MBAR+0x0000002C)) -#define MCFSCM_PACR8 (*(vu_char *) (CFG_MBAR+0x0000002E)) -#define MCFSCM_GPACR0 (*(vu_char *) (CFG_MBAR+0x00000030)) -#define MCFSCM_GPACR1 (*(vu_char *) (CFG_MBAR+0x00000031)) +#define MCFSCM_RAMBAR (*(vu_long *) (CONFIG_SYS_MBAR+0x00000008)) +#define MCFSCM_CRSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000010)) +#define MCFSCM_CWCR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000011)) +#define MCFSCM_LPICR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000012)) +#define MCFSCM_CWSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000013)) + +#define MCFSCM_MPARK (*(vu_long *) (CONFIG_SYS_MBAR+0x0000001C)) +#define MCFSCM_MPR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000020)) +#define MCFSCM_PACR0 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000024)) +#define MCFSCM_PACR1 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000025)) +#define MCFSCM_PACR2 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000026)) +#define MCFSCM_PACR3 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000027)) +#define MCFSCM_PACR4 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000028)) +#define MCFSCM_PACR5 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002A)) +#define MCFSCM_PACR6 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002B)) +#define MCFSCM_PACR7 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002C)) +#define MCFSCM_PACR8 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002E)) +#define MCFSCM_GPACR0 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000030)) +#define MCFSCM_GPACR1 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000031)) #define MCFSCM_CRSR_EXT (0x80) #define MCFSCM_CRSR_CWDR (0x20) @@ -354,8 +354,8 @@ /* Reset Controller Module RCM */ -#define MCFRESET_RCR (*(vu_char *) (CFG_MBAR+0x00110000)) -#define MCFRESET_RSR (*(vu_char *) (CFG_MBAR+0x00110001)) +#define MCFRESET_RCR (*(vu_char *) (CONFIG_SYS_MBAR+0x00110000)) +#define MCFRESET_RSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00110001)) #define MCFRESET_RCR_SOFTRST (0x80) #define MCFRESET_RCR_FRCRSTOUT (0x40) @@ -377,9 +377,9 @@ /* Chip Configuration Module CCM */ -#define MCFCCM_CCR (*(vu_short *)(CFG_MBAR+0x00110004)) -#define MCFCCM_RCON (*(vu_short *)(CFG_MBAR+0x00110008)) -#define MCFCCM_CIR (*(vu_short *)(CFG_MBAR+0x0011000A)) +#define MCFCCM_CCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00110004)) +#define MCFCCM_RCON (*(vu_short *)(CONFIG_SYS_MBAR+0x00110008)) +#define MCFCCM_CIR (*(vu_short *)(CONFIG_SYS_MBAR+0x0011000A)) /* Bit level definitions and macros */ #define MCFCCM_CCR_LOAD (0x8000) @@ -394,18 +394,18 @@ /* Clock Module */ -#define MCFCLOCK_SYNCR (*(vu_short *)(CFG_MBAR+0x120000)) -#define MCFCLOCK_SYNSR (*(vu_char *) (CFG_MBAR+0x120002)) +#define MCFCLOCK_SYNCR (*(vu_short *)(CONFIG_SYS_MBAR+0x120000)) +#define MCFCLOCK_SYNSR (*(vu_char *) (CONFIG_SYS_MBAR+0x120002)) #define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12) #define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8) #define MCFCLOCK_SYNSR_LOCK 0x08 -#define MCFSDRAMC_DCR (*(vu_short *)(CFG_MBAR+0x00000040)) -#define MCFSDRAMC_DACR0 (*(vu_long *) (CFG_MBAR+0x00000048)) -#define MCFSDRAMC_DMR0 (*(vu_long *) (CFG_MBAR+0x0000004c)) -#define MCFSDRAMC_DACR1 (*(vu_long *) (CFG_MBAR+0x00000050)) -#define MCFSDRAMC_DMR1 (*(vu_long *) (CFG_MBAR+0x00000054)) +#define MCFSDRAMC_DCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00000040)) +#define MCFSDRAMC_DACR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000048)) +#define MCFSDRAMC_DMR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x0000004c)) +#define MCFSDRAMC_DACR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000050)) +#define MCFSDRAMC_DMR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000054)) #define MCFSDRAMC_DCR_NAM (0x2000) #define MCFSDRAMC_DCR_COC (0x1000) @@ -435,83 +435,60 @@ #define MCFSDRAMC_DMR_UD (0x00000002) #define MCFSDRAMC_DMR_V (0x00000001) -#define MCFWTM_WCR (*(vu_short *)(CFG_MBAR+0x00140000)) -#define MCFWTM_WMR (*(vu_short *)(CFG_MBAR+0x00140002)) -#define MCFWTM_WCNTR (*(vu_short *)(CFG_MBAR+0x00140004)) -#define MCFWTM_WSR (*(vu_short *)(CFG_MBAR+0x00140006)) - -/* Chip SELECT Module CSM */ -#define MCFCSM_CSAR0 (*(vu_short *)(CFG_MBAR+0x00000080)) -#define MCFCSM_CSMR0 (*(vu_long *) (CFG_MBAR+0x00000084)) -#define MCFCSM_CSCR0 (*(vu_short *)(CFG_MBAR+0x0000008a)) -#define MCFCSM_CSAR1 (*(vu_short *)(CFG_MBAR+0x0000008C)) -#define MCFCSM_CSMR1 (*(vu_long *) (CFG_MBAR+0x00000090)) -#define MCFCSM_CSCR1 (*(vu_short *)(CFG_MBAR+0x00000096)) -#define MCFCSM_CSAR2 (*(vu_short *)(CFG_MBAR+0x00000098)) -#define MCFCSM_CSMR2 (*(vu_long *) (CFG_MBAR+0x0000009C)) -#define MCFCSM_CSCR2 (*(vu_short *)(CFG_MBAR+0x000000A2)) -#define MCFCSM_CSAR3 (*(vu_short *)(CFG_MBAR+0x000000A4)) -#define MCFCSM_CSMR3 (*(vu_long *) (CFG_MBAR+0x000000A8)) -#define MCFCSM_CSCR3 (*(vu_short *)(CFG_MBAR+0x000000AE)) - -#define MCFCSM_CSMR_BAM(x) ((x) & 0xFFFF0000) -#define MCFCSM_CSMR_WP (1<<8) -#define MCFCSM_CSMR_V (0x01) -#define MCFCSM_CSCR_WS(x) ((x & 0x0F)<<10) -#define MCFCSM_CSCR_AA (0x0100) -#define MCFCSM_CSCR_PS_32 (0x0000) -#define MCFCSM_CSCR_PS_8 (0x0040) -#define MCFCSM_CSCR_PS_16 (0x0080) +#define MCFWTM_WCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140000)) +#define MCFWTM_WMR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140002)) +#define MCFWTM_WCNTR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140004)) +#define MCFWTM_WSR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140006)) /********************************************************************* * General Purpose Timer (GPT) Module *********************************************************************/ -#define MCFGPTA_GPTIOS (*(vu_char *)(CFG_MBAR+0x1A0000)) -#define MCFGPTA_GPTCFORC (*(vu_char *)(CFG_MBAR+0x1A0001)) -#define MCFGPTA_GPTOC3M (*(vu_char *)(CFG_MBAR+0x1A0002)) -#define MCFGPTA_GPTOC3D (*(vu_char *)(CFG_MBAR+0x1A0003)) -#define MCFGPTA_GPTCNT (*(vu_short *)(CFG_MBAR+0x1A0004)) -#define MCFGPTA_GPTSCR1 (*(vu_char *)(CFG_MBAR+0x1A0006)) -#define MCFGPTA_GPTTOV (*(vu_char *)(CFG_MBAR+0x1A0008)) -#define MCFGPTA_GPTCTL1 (*(vu_char *)(CFG_MBAR+0x1A0009)) -#define MCFGPTA_GPTCTL2 (*(vu_char *)(CFG_MBAR+0x1A000B)) -#define MCFGPTA_GPTIE (*(vu_char *)(CFG_MBAR+0x1A000C)) -#define MCFGPTA_GPTSCR2 (*(vu_char *)(CFG_MBAR+0x1A000D)) -#define MCFGPTA_GPTFLG1 (*(vu_char *)(CFG_MBAR+0x1A000E)) -#define MCFGPTA_GPTFLG2 (*(vu_char *)(CFG_MBAR+0x1A000F)) -#define MCFGPTA_GPTC0 (*(vu_short *)(CFG_MBAR+0x1A0010)) -#define MCFGPTA_GPTC1 (*(vu_short *)(CFG_MBAR+0x1A0012)) -#define MCFGPTA_GPTC2 (*(vu_short *)(CFG_MBAR+0x1A0014)) -#define MCFGPTA_GPTC3 (*(vu_short *)(CFG_MBAR+0x1A0016)) -#define MCFGPTA_GPTPACTL (*(vu_char *)(CFG_MBAR+0x1A0018)) -#define MCFGPTA_GPTPAFLG (*(vu_char *)(CFG_MBAR+0x1A0019)) -#define MCFGPTA_GPTPACNT (*(vu_short *)(CFG_MBAR+0x1A001A)) -#define MCFGPTA_GPTPORT (*(vu_char *)(CFG_MBAR+0x1A001D)) -#define MCFGPTA_GPTDDR (*(vu_char *)(CFG_MBAR+0x1A001E)) - -#define MCFGPTB_GPTIOS (*(vu_char *)(CFG_MBAR+0x1B0000)) -#define MCFGPTB_GPTCFORC (*(vu_char *)(CFG_MBAR+0x1B0001)) -#define MCFGPTB_GPTOC3M (*(vu_char *)(CFG_MBAR+0x1B0002)) -#define MCFGPTB_GPTOC3D (*(vu_char *)(CFG_MBAR+0x1B0003)) -#define MCFGPTB_GPTCNT (*(vu_short *)(CFG_MBAR+0x1B0004)) -#define MCFGPTB_GPTSCR1 (*(vu_char *)(CFG_MBAR+0x1B0006)) -#define MCFGPTB_GPTTOV (*(vu_char *)(CFG_MBAR+0x1B0008)) -#define MCFGPTB_GPTCTL1 (*(vu_char *)(CFG_MBAR+0x1B0009)) -#define MCFGPTB_GPTCTL2 (*(vu_char *)(CFG_MBAR+0x1B000B)) -#define MCFGPTB_GPTIE (*(vu_char *)(CFG_MBAR+0x1B000C)) -#define MCFGPTB_GPTSCR2 (*(vu_char *)(CFG_MBAR+0x1B000D)) -#define MCFGPTB_GPTFLG1 (*(vu_char *)(CFG_MBAR+0x1B000E)) -#define MCFGPTB_GPTFLG2 (*(vu_char *)(CFG_MBAR+0x1B000F)) -#define MCFGPTB_GPTC0 (*(vu_short *)(CFG_MBAR+0x1B0010)) -#define MCFGPTB_GPTC1 (*(vu_short *)(CFG_MBAR+0x1B0012)) -#define MCFGPTB_GPTC2 (*(vu_short *)(CFG_MBAR+0x1B0014)) -#define MCFGPTB_GPTC3 (*(vu_short *)(CFG_MBAR+0x1B0016)) -#define MCFGPTB_GPTPACTL (*(vu_char *)(CFG_MBAR+0x1B0018)) -#define MCFGPTB_GPTPAFLG (*(vu_char *)(CFG_MBAR+0x1B0019)) -#define MCFGPTB_GPTPACNT (*(vu_short *)(CFG_MBAR+0x1B001A)) -#define MCFGPTB_GPTPORT (*(vu_char *)(CFG_MBAR+0x1B001D)) -#define MCFGPTB_GPTDDR (*(vu_char *)(CFG_MBAR+0x1B001E)) +#define MCFGPTA_GPTIOS (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0000)) +#define MCFGPTA_GPTCFORC (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0001)) +#define MCFGPTA_GPTOC3M (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0002)) +#define MCFGPTA_GPTOC3D (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0003)) +#define MCFGPTA_GPTCNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0004)) +#define MCFGPTA_GPTSCR1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0006)) +#define MCFGPTA_GPTTOV (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0008)) +#define MCFGPTA_GPTCTL1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0009)) +#define MCFGPTA_GPTCTL2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000B)) +#define MCFGPTA_GPTIE (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000C)) +#define MCFGPTA_GPTSCR2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000D)) +#define MCFGPTA_GPTFLG1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000E)) +#define MCFGPTA_GPTFLG2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000F)) +#define MCFGPTA_GPTC0 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0010)) +#define MCFGPTA_GPTC1 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0012)) +#define MCFGPTA_GPTC2 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0014)) +#define MCFGPTA_GPTC3 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0016)) +#define MCFGPTA_GPTPACTL (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0018)) +#define MCFGPTA_GPTPAFLG (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0019)) +#define MCFGPTA_GPTPACNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1A001A)) +#define MCFGPTA_GPTPORT (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001D)) +#define MCFGPTA_GPTDDR (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001E)) + +#define MCFGPTB_GPTIOS (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0000)) +#define MCFGPTB_GPTCFORC (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0001)) +#define MCFGPTB_GPTOC3M (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0002)) +#define MCFGPTB_GPTOC3D (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0003)) +#define MCFGPTB_GPTCNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0004)) +#define MCFGPTB_GPTSCR1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0006)) +#define MCFGPTB_GPTTOV (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0008)) +#define MCFGPTB_GPTCTL1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0009)) +#define MCFGPTB_GPTCTL2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000B)) +#define MCFGPTB_GPTIE (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000C)) +#define MCFGPTB_GPTSCR2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000D)) +#define MCFGPTB_GPTFLG1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000E)) +#define MCFGPTB_GPTFLG2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000F)) +#define MCFGPTB_GPTC0 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0010)) +#define MCFGPTB_GPTC1 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0012)) +#define MCFGPTB_GPTC2 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0014)) +#define MCFGPTB_GPTC3 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0016)) +#define MCFGPTB_GPTPACTL (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0018)) +#define MCFGPTB_GPTPAFLG (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0019)) +#define MCFGPTB_GPTPACNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1B001A)) +#define MCFGPTB_GPTPORT (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001D)) +#define MCFGPTB_GPTDDR (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001E)) /* Bit level definitions and macros */ #define MCFGPT_GPTIOS_IOS3 (0x08) @@ -596,7 +573,7 @@ /* Coldfire Flash Module CFM */ -#define MCFCFM_MCR (*(vu_short *)(CFG_MBAR+0x1D0000)) +#define MCFCFM_MCR (*(vu_short *)(CONFIG_SYS_MBAR+0x1D0000)) #define MCFCFM_MCR_LOCK (0x0400) #define MCFCFM_MCR_PVIE (0x0200) #define MCFCFM_MCR_AEIE (0x0100) @@ -604,23 +581,23 @@ #define MCFCFM_MCR_CCIE (0x0040) #define MCFCFM_MCR_KEYACC (0x0020) -#define MCFCFM_CLKD (*(vu_char *)(CFG_MBAR+0x1D0002)) +#define MCFCFM_CLKD (*(vu_char *)(CONFIG_SYS_MBAR+0x1D0002)) -#define MCFCFM_SEC (*(vu_long*) (CFG_MBAR+0x1D0008)) +#define MCFCFM_SEC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0008)) #define MCFCFM_SEC_KEYEN (0x80000000) #define MCFCFM_SEC_SECSTAT (0x40000000) -#define MCFCFM_PROT (*(vu_long*) (CFG_MBAR+0x1D0010)) -#define MCFCFM_SACC (*(vu_long*) (CFG_MBAR+0x1D0014)) -#define MCFCFM_DACC (*(vu_long*) (CFG_MBAR+0x1D0018)) -#define MCFCFM_USTAT (*(vu_char*) (CFG_MBAR+0x1D0020)) +#define MCFCFM_PROT (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0010)) +#define MCFCFM_SACC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0014)) +#define MCFCFM_DACC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0018)) +#define MCFCFM_USTAT (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0020)) #define MCFCFM_USTAT_CBEIF 0x80 #define MCFCFM_USTAT_CCIF 0x40 #define MCFCFM_USTAT_PVIOL 0x20 #define MCFCFM_USTAT_ACCERR 0x10 #define MCFCFM_USTAT_BLANK 0x04 -#define MCFCFM_CMD (*(vu_char*) (CFG_MBAR+0x1D0024)) +#define MCFCFM_CMD (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0024)) #define MCFCFM_CMD_ERSVER 0x05 #define MCFCFM_CMD_PGERSVER 0x06 #define MCFCFM_CMD_PGM 0x20 |