diff options
Diffstat (limited to 'include/asm-m68k/immap_5235.h')
| -rw-r--r-- | include/asm-m68k/immap_5235.h | 166 |
1 files changed, 12 insertions, 154 deletions
diff --git a/include/asm-m68k/immap_5235.h b/include/asm-m68k/immap_5235.h index 3ef0321..f7f35fc 100644 --- a/include/asm-m68k/immap_5235.h +++ b/include/asm-m68k/immap_5235.h @@ -63,6 +63,15 @@ #define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000) #define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000) +#include <asm/coldfire/eport.h> +#include <asm/coldfire/flexbus.h> +#include <asm/coldfire/flexcan.h> +#include <asm/coldfire/intctrl.h> +#include <asm/coldfire/mdha.h> +#include <asm/coldfire/qspi.h> +#include <asm/coldfire/rng.h> +#include <asm/coldfire/skha.h> + /* System Control Module register */ typedef struct scm_ctrl { u32 ipsbar; /* 0x00 - MBAR */ @@ -104,141 +113,9 @@ typedef struct sdram_ctrl { u32 dmr1; /* 0x14 mask register block 1 */ } sdram_t; -/* Flexbus module Chip select registers */ -typedef struct fbcs_ctrl { - u16 csar0; /* 0x00 Chip-Select Address Register 0 */ - u16 res0; - u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */ - u16 res1; /* 0x08 */ - u16 cscr0; /* 0x0A Chip-Select Control Register 0 */ - - u16 csar1; /* 0x0C Chip-Select Address Register 1 */ - u16 res2; - u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */ - u16 res3; /* 0x14 */ - u16 cscr1; /* 0x16 Chip-Select Control Register 1 */ - - u16 csar2; /* 0x18 Chip-Select Address Register 2 */ - u16 res4; - u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */ - u16 res5; /* 0x20 */ - u16 cscr2; /* 0x22 Chip-Select Control Register 2 */ - - u16 csar3; /* 0x24 Chip-Select Address Register 3 */ - u16 res6; - u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */ - u16 res7; /* 0x2C */ - u16 cscr3; /* 0x2E Chip-Select Control Register 3 */ - - u16 csar4; /* 0x30 Chip-Select Address Register 4 */ - u16 res8; - u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */ - u16 res9; /* 0x38 */ - u16 cscr4; /* 0x3A Chip-Select Control Register 4 */ - - u16 csar5; /* 0x3C Chip-Select Address Register 5 */ - u16 res10; - u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */ - u16 res11; /* 0x44 */ - u16 cscr5; /* 0x46 Chip-Select Control Register 5 */ - - u16 csar6; /* 0x48 Chip-Select Address Register 5 */ - u16 res12; - u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */ - u16 res13; /* 0x50 */ - u16 cscr6; /* 0x52 Chip-Select Control Register 5 */ - - u16 csar7; /* 0x54 Chip-Select Address Register 5 */ - u16 res14; - u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */ - u16 res15; /* 0x5C */ - u16 cscr7; /* 0x5E Chip-Select Control Register 5 */ -} fbcs_t; - -/* QSPI module registers */ -typedef struct qspi_ctrl { - u16 qmr; /* Mode register */ - u16 res1; - u16 qdlyr; /* Delay register */ - u16 res2; - u16 qwr; /* Wrap register */ - u16 res3; - u16 qir; /* Interrupt register */ - u16 res4; - u16 qar; /* Address register */ - u16 res5; - u16 qdr; /* Data register */ - u16 res6; -} qspi_t; - -/* Interrupt module registers */ -typedef struct int0_ctrl { - /* Interrupt Controller 0 */ - u32 iprh0; /* 0x00 Pending Register High */ - u32 iprl0; /* 0x04 Pending Register Low */ - u32 imrh0; /* 0x08 Mask Register High */ - u32 imrl0; /* 0x0C Mask Register Low */ - u32 frch0; /* 0x10 Force Register High */ - u32 frcl0; /* 0x14 Force Register Low */ - u8 irlr; /* 0x18 */ - u8 iacklpr; /* 0x19 */ - u16 res1[19]; /* 0x1a - 0x3c */ - u8 icr0[64]; /* 0x40 - 0x7F Control registers */ - u32 res3[24]; /* 0x80 - 0xDF */ - u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */ - u8 res4[3]; /* 0xE1 - 0xE3 */ - u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */ - u8 res5[3]; /* 0xE5 - 0xE7 */ - u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */ - u8 res6[3]; /* 0xE9 - 0xEB */ - u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */ - u8 res7[3]; /* 0xED - 0xEF */ - u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */ - u8 res8[3]; /* 0xF1 - 0xF3 */ - u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */ - u8 res9[3]; /* 0xF5 - 0xF7 */ - u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */ - u8 resa[3]; /* 0xF9 - 0xFB */ - u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */ - u8 resb[3]; /* 0xFD - 0xFF */ -} int0_t; - -typedef struct int1_ctrl { - /* Interrupt Controller 1 */ - u32 iprh1; /* 0x00 Pending Register High */ - u32 iprl1; /* 0x04 Pending Register Low */ - u32 imrh1; /* 0x08 Mask Register High */ - u32 imrl1; /* 0x0C Mask Register Low */ - u32 frch1; /* 0x10 Force Register High */ - u32 frcl1; /* 0x14 Force Register Low */ - u8 irlr; /* 0x18 */ - u8 iacklpr; /* 0x19 */ - u16 res1[19]; /* 0x1a - 0x3c */ - u8 icr1[64]; /* 0x40 - 0x7F */ - u32 res4[24]; /* 0x80 - 0xDF */ - u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */ - u8 res5[3]; /* 0xE1 - 0xE3 */ - u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */ - u8 res6[3]; /* 0xE5 - 0xE7 */ - u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */ - u8 res7[3]; /* 0xE9 - 0xEB */ - u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */ - u8 res8[3]; /* 0xED - 0xEF */ - u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */ - u8 res9[3]; /* 0xF1 - 0xF3 */ - u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */ - u8 resa[3]; /* 0xF5 - 0xF7 */ - u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */ - u8 resb[3]; /* 0xF9 - 0xFB */ - u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */ - u8 resc[3]; /* 0xFD - 0xFF */ -} int1_t; - -typedef struct intgack_ctrl1 { - /* Global IACK Registers */ - u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */ - u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */ -} intgack_t; +typedef struct canex_ctrl { + can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */ +} canex_t; /* GPIO port registers */ typedef struct gpio_ctrl { @@ -356,23 +233,4 @@ typedef struct wdog_ctrl { u16 sr; /* 0x06 Service register */ } wdog_t; -/* FlexCan module registers */ -typedef struct can_ctrl { - u32 mcr; /* 0x00 Module Configuration register */ - u32 ctrl; /* 0x04 Control register */ - u32 timer; /* 0x08 Free Running Timer */ - u32 res1; /* 0x0C */ - u32 rxgmask; /* 0x10 Rx Global Mask */ - u32 rx14mask; /* 0x14 RxBuffer 14 Mask */ - u32 rx15mask; /* 0x18 RxBuffer 15 Mask */ - u32 errcnt; /* 0x1C Error Counter Register */ - u32 errstat; /* 0x20 Error and status Register */ - u32 res2; /* 0x24 */ - u32 imask; /* 0x28 Interrupt Mask Register */ - u32 res3; /* 0x2C */ - u32 iflag; /* 0x30 Interrupt Flag Register */ - u32 res4[19]; /* 0x34 - 0x7F */ - u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */ -} can_t; - #endif /* __IMMAP_5235__ */ |