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-rw-r--r--include/asm-blackfin/mach-common/bits/bootrom.h72
-rw-r--r--include/asm-blackfin/mach-common/bits/ebiu.h21
-rw-r--r--include/asm-blackfin/mach-common/bits/otp.h21
3 files changed, 74 insertions, 40 deletions
diff --git a/include/asm-blackfin/mach-common/bits/bootrom.h b/include/asm-blackfin/mach-common/bits/bootrom.h
index 6cdaa4f..fb97ff8 100644
--- a/include/asm-blackfin/mach-common/bits/bootrom.h
+++ b/include/asm-blackfin/mach-common/bits/bootrom.h
@@ -88,27 +88,42 @@
#define _BOOTROM_REV 0xEF000040
#define _BOOTROM_SESR 0xEF001000
+#define BOOTROM_FOLLOWS_C_ABI 1
+
#define BOOTROM_CAPS_ADI_BOOT_STRUCTS 1
-/* Not available on initial BF54x or BF52x */
-#if (defined(__ADSPBF54x__) && __SILICON_REVISION__ < 1) || \
- (defined(__ADSPBF52x__) && __SILICON_REVISION__ < 2)
-#define BOOTROM_CAPS_SYSCONTROL 0
-#else
-#define BOOTROM_CAPS_SYSCONTROL 1
#endif
+#ifndef BOOTROM_FOLLOWS_C_ABI
+#define BOOTROM_FOLLOWS_C_ABI 0
#endif
-
#ifndef BOOTROM_CAPS_ADI_BOOT_STRUCTS
#define BOOTROM_CAPS_ADI_BOOT_STRUCTS 0
#endif
-#ifndef BOOTROM_CAPS_SYSCONTROL
-#define BOOTROM_CAPS_SYSCONTROL 0
-#endif
+
+/* Possible syscontrol action flags */
+#define SYSCTRL_READ 0x00000000 /* read registers */
+#define SYSCTRL_WRITE 0x00000001 /* write registers */
+#define SYSCTRL_SYSRESET 0x00000002 /* perform system reset */
+#define SYSCTRL_CORERESET 0x00000004 /* perform core reset */
+#define SYSCTRL_SOFTRESET 0x00000006 /* perform core and system reset */
+#define SYSCTRL_VRCTL 0x00000010 /* read/write VR_CTL register */
+#define SYSCTRL_EXTVOLTAGE 0x00000020 /* VDDINT supplied externally */
+#define SYSCTRL_INTVOLTAGE 0x00000000 /* VDDINT generated by on-chip regulator */
+#define SYSCTRL_OTPVOLTAGE 0x00000040 /* For Factory Purposes Only */
+#define SYSCTRL_PLLCTL 0x00000100 /* read/write PLL_CTL register */
+#define SYSCTRL_PLLDIV 0x00000200 /* read/write PLL_DIV register */
+#define SYSCTRL_LOCKCNT 0x00000400 /* read/write PLL_LOCKCNT register */
+#define SYSCTRL_PLLSTAT 0x00000800 /* read/write PLL_STAT register */
#ifndef __ASSEMBLY__
+#if BOOTROM_FOLLOWS_C_ABI
+# define BOOTROM_CALLED_FUNC_ATTR
+#else
+# define BOOTROM_CALLED_FUNC_ATTR __attribute__((saveall))
+#endif
+
/* Structures for the syscontrol() function */
typedef struct ADI_SYSCTRL_VALUES {
uint16_t uwVrCtl;
@@ -121,25 +136,26 @@ typedef struct ADI_SYSCTRL_VALUES {
#ifndef _BOOTROM_SYSCONTROL
#define _BOOTROM_SYSCONTROL 0
#endif
-static uint32_t (* const syscontrol)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)_BOOTROM_SYSCONTROL;
-
-#endif /* __ASSEMBLY__ */
-
-/* Possible syscontrol action flags */
-#define SYSCTRL_READ 0x00000000 /* read registers */
-#define SYSCTRL_WRITE 0x00000001 /* write registers */
-#define SYSCTRL_SYSRESET 0x00000002 /* perform system reset */
-#define SYSCTRL_SOFTRESET 0x00000004 /* perform core and system reset */
-#define SYSCTRL_VRCTL 0x00000010 /* read/write VR_CTL register */
-#define SYSCTRL_EXTVOLTAGE 0x00000020 /* VDDINT supplied externally */
-#define SYSCTRL_INTVOLTAGE 0x00000000 /* VDDINT generated by on-chip regulator */
-#define SYSCTRL_OTPVOLTAGE 0x00000040 /* For Factory Purposes Only */
-#define SYSCTRL_PLLCTL 0x00000100 /* read/write PLL_CTL register */
-#define SYSCTRL_PLLDIV 0x00000200 /* read/write PLL_DIV register */
-#define SYSCTRL_LOCKCNT 0x00000400 /* read/write PLL_LOCKCNT register */
-#define SYSCTRL_PLLSTAT 0x00000800 /* read/write PLL_STAT register */
+static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)_BOOTROM_SYSCONTROL;
-#ifndef __ASSEMBLY__
+/* We need a dedicated function since we need to screw with the stack pointer
+ * when resetting. The on-chip ROM will save/restore registers on the stack
+ * when doing a system reset, so the stack cannot be outside of the chip.
+ */
+__attribute__((__noreturn__))
+static inline void bfrom_SoftReset(void *new_stack)
+{
+ while (1)
+ __asm__ __volatile__(
+ "sp = %[stack];"
+ "jump (%[bfrom_syscontrol]);"
+ : : [bfrom_syscontrol] "p"(bfrom_SysControl),
+ "q0"(SYSCTRL_SOFTRESET),
+ "q1"(0),
+ "q2"(NULL),
+ [stack] "p"(new_stack)
+ );
+}
/* Structures for working with LDRs and boot rom callbacks */
typedef struct ADI_BOOT_HEADER {
diff --git a/include/asm-blackfin/mach-common/bits/ebiu.h b/include/asm-blackfin/mach-common/bits/ebiu.h
index ab530ad..af456fb 100644
--- a/include/asm-blackfin/mach-common/bits/ebiu.h
+++ b/include/asm-blackfin/mach-common/bits/ebiu.h
@@ -410,12 +410,31 @@
/* EBIU_SDSTAT Masks */
#define SDCI 0x0001 /* SDRAM controller is idle */
-#define SDSRA 0x0002 /* SDRAM SDRAM self refresh is active */
+#define SDSRA 0x0002 /* SDRAM self refresh is active */
#define SDPUA 0x0004 /* SDRAM power up active */
#define SDRS 0x0008 /* SDRAM is in reset state */
#define SDEASE 0x0010 /* SDRAM EAB sticky error status - W1C */
#define BGSTAT 0x0020 /* Bus granted */
+/* Only available on DDR based-parts */
+#else
+
+/* EBIU_ERRMST Masks */
+#define DEB0_ERROR 0x0001 /* DEB0 access on reserved memory */
+#define DEB1_ERROR 0x0002 /* DEB1 access on reserved memory */
+#define DEB2_ERROR 0x0004 /* DEB2 (USB) access on reserved memory */
+#define CORE_ERROR 0x0008 /* Core access on reserved memory */
+#define DEB0_MERROR 0x0010 /* DEB0 access on reserved memory and DEB0_ERROR is set */
+#define DEB1_MERROR 0x0020 /* DEB1 access on reserved memory and DEB1_ERROR is set */
+#define DEB2_MERROR 0x0040 /* DEB2 access on reserved memory and DEB2_ERROR is set */
+#define CORE_MERROR 0x0080 /* Core access on reserved memory and CORE_ERROR is set */
+
+/* EBIU_RSTCTL Masks */
+#define DDR_SRESET 0x0001 /* Reset Control to DDR Controller */
+#define SRREQ 0x0008 /* Self Refresh Request */
+#define SRACK 0x0010 /* Self Refresh Request Acknowledgement */
+#define MDDRENABLE 0x0020 /* Mobile DDR Enable */
+
#endif /* EBIU_SDGCTL */
#endif
diff --git a/include/asm-blackfin/mach-common/bits/otp.h b/include/asm-blackfin/mach-common/bits/otp.h
index d529a0a..4e3f1af 100644
--- a/include/asm-blackfin/mach-common/bits/otp.h
+++ b/include/asm-blackfin/mach-common/bits/otp.h
@@ -9,23 +9,22 @@
#include "bootrom.h"
-static uint32_t (* const otp_command)(uint32_t command, uint32_t value) = (void *)_BOOTROM_OTP_COMMAND;
-static uint32_t (* const otp_read)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_READ;
-static uint32_t (* const otp_write)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_WRITE;
+static uint32_t (* const bfrom_OtpCommand)(uint32_t command, uint32_t value) = (void *)_BOOTROM_OTP_COMMAND;
+static uint32_t (* const bfrom_OtpRead)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_READ;
+static uint32_t (* const bfrom_OtpWrite)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_WRITE;
#endif
/* otp_command(): defines for "command" */
-#define OTP_INIT 0x00000001
-#define OTP_CLOSE 0x00000002
+#define OTP_INIT 0x00000001
+#define OTP_CLOSE 0x00000002
/* otp_{read,write}(): defines for "flags" */
-#define OTP_LOWER_HALF 0x00000000 /* select upper/lower 64-bit half (bit 0) */
-#define OTP_UPPER_HALF 0x00000001
-#define OTP_NO_ECC 0x00000010 /* do not use ECC */
-#define OTP_LOCK 0x00000020 /* sets page protection bit for page */
-#define OTP_ACCESS_READ 0x00001000
-#define OTP_ACCESS_READWRITE 0x00002000
+#define OTP_LOWER_HALF 0x00000000 /* select upper/lower 64-bit half (bit 0) */
+#define OTP_UPPER_HALF 0x00000001
+#define OTP_NO_ECC 0x00000010 /* do not use ECC */
+#define OTP_LOCK 0x00000020 /* sets page protection bit for page */
+#define OTP_CHECK_FOR_PREV_WRITE 0x00000080
/* Return values for all functions */
#define OTP_SUCCESS 0x00000000
generated by cgit v1.1 at 2024-12-26 17:58:47 +0000