diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf561/BF561_def.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf561/BF561_def.h | 173 |
1 files changed, 0 insertions, 173 deletions
diff --git a/include/asm-blackfin/mach-bf561/BF561_def.h b/include/asm-blackfin/mach-bf561/BF561_def.h deleted file mode 100644 index 8534962..0000000 --- a/include/asm-blackfin/mach-bf561/BF561_def.h +++ /dev/null @@ -1,173 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF561_proc__ -#define __BFIN_DEF_ADSP_BF561_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "../mach-common/ADSP-EDN-DUAL-CORE-extended_def.h" - -#define SRAM_BASE_ADDR 0xFFE00000 -#define DMEM_CONTROL 0xFFE00004 -#define DCPLB_STATUS 0xFFE00008 -#define DCPLB_FAULT_ADDR 0xFFE0000C -#define DCPLB_ADDR0 0xFFE00100 -#define DCPLB_ADDR1 0xFFE00104 -#define DCPLB_ADDR2 0xFFE00108 -#define DCPLB_ADDR3 0xFFE0010C -#define DCPLB_ADDR4 0xFFE00110 -#define DCPLB_ADDR5 0xFFE00114 -#define DCPLB_ADDR6 0xFFE00118 -#define DCPLB_ADDR7 0xFFE0011C -#define DCPLB_ADDR8 0xFFE00120 -#define DCPLB_ADDR9 0xFFE00124 -#define DCPLB_ADDR10 0xFFE00128 -#define DCPLB_ADDR11 0xFFE0012C -#define DCPLB_ADDR12 0xFFE00130 -#define DCPLB_ADDR13 0xFFE00134 -#define DCPLB_ADDR14 0xFFE00138 -#define DCPLB_ADDR15 0xFFE0013C -#define DCPLB_DATA0 0xFFE00200 -#define DCPLB_DATA1 0xFFE00204 -#define DCPLB_DATA2 0xFFE00208 -#define DCPLB_DATA3 0xFFE0020C -#define DCPLB_DATA4 0xFFE00210 -#define DCPLB_DATA5 0xFFE00214 -#define DCPLB_DATA6 0xFFE00218 -#define DCPLB_DATA7 0xFFE0021C -#define DCPLB_DATA8 0xFFE00220 -#define DCPLB_DATA9 0xFFE00224 -#define DCPLB_DATA10 0xFFE00228 -#define DCPLB_DATA11 0xFFE0022C -#define DCPLB_DATA12 0xFFE00230 -#define DCPLB_DATA13 0xFFE00234 -#define DCPLB_DATA14 0xFFE00238 -#define DCPLB_DATA15 0xFFE0023C -#define DTEST_COMMAND 0xFFE00300 -#define DTEST_DATA0 0xFFE00400 -#define DTEST_DATA1 0xFFE00404 -#define IMEM_CONTROL 0xFFE01004 -#define ICPLB_STATUS 0xFFE01008 -#define ICPLB_FAULT_ADDR 0xFFE0100C -#define ICPLB_ADDR0 0xFFE01100 -#define ICPLB_ADDR1 0xFFE01104 -#define ICPLB_ADDR2 0xFFE01108 -#define ICPLB_ADDR3 0xFFE0110C -#define ICPLB_ADDR4 0xFFE01110 -#define ICPLB_ADDR5 0xFFE01114 -#define ICPLB_ADDR6 0xFFE01118 -#define ICPLB_ADDR7 0xFFE0111C -#define ICPLB_ADDR8 0xFFE01120 -#define ICPLB_ADDR9 0xFFE01124 -#define ICPLB_ADDR10 0xFFE01128 -#define ICPLB_ADDR11 0xFFE0112C -#define ICPLB_ADDR12 0xFFE01130 -#define ICPLB_ADDR13 0xFFE01134 -#define ICPLB_ADDR14 0xFFE01138 -#define ICPLB_ADDR15 0xFFE0113C -#define ICPLB_DATA0 0xFFE01200 -#define ICPLB_DATA1 0xFFE01204 -#define ICPLB_DATA2 0xFFE01208 -#define ICPLB_DATA3 0xFFE0120C -#define ICPLB_DATA4 0xFFE01210 -#define ICPLB_DATA5 0xFFE01214 -#define ICPLB_DATA6 0xFFE01218 -#define ICPLB_DATA7 0xFFE0121C -#define ICPLB_DATA8 0xFFE01220 -#define ICPLB_DATA9 0xFFE01224 -#define ICPLB_DATA10 0xFFE01228 -#define ICPLB_DATA11 0xFFE0122C -#define ICPLB_DATA12 0xFFE01230 -#define ICPLB_DATA13 0xFFE01234 -#define ICPLB_DATA14 0xFFE01238 -#define ICPLB_DATA15 0xFFE0123C -#define ITEST_COMMAND 0xFFE01300 -#define ITEST_DATA0 0xFFE01400 -#define ITEST_DATA1 0xFFE01404 -#define SICA_SWRST 0xFFC00100 -#define SICA_SYSCR 0xFFC00104 -#define SICA_RVECT 0xFFC00108 -#define SICA_IMASK0 0xFFC0010C -#define SICA_IMASK1 0xFFC00110 -#define SICA_ISR0 0xFFC00114 -#define SICA_ISR1 0xFFC00118 -#define SICA_IWR0 0xFFC0011C -#define SICA_IWR1 0xFFC00120 -#define SICA_IAR0 0xFFC00124 -#define SICA_IAR1 0xFFC00128 -#define SICA_IAR2 0xFFC0012C -#define SICA_IAR3 0xFFC00130 -#define SICA_IAR4 0xFFC00134 -#define SICA_IAR5 0xFFC00138 -#define SICA_IAR6 0xFFC0013C -#define SICA_IAR7 0xFFC00140 -#define SICB_SWRST 0xFFC01100 -#define SICB_SYSCR 0xFFC01104 -#define SICB_RVECT 0xFFC01108 -#define SICB_IMASK0 0xFFC0110C -#define SICB_IMASK1 0xFFC01110 -#define SICB_ISR0 0xFFC01114 -#define SICB_ISR1 0xFFC01118 -#define SICB_IWR0 0xFFC0111C -#define SICB_IWR1 0xFFC01120 -#define SICB_IAR0 0xFFC01124 -#define SICB_IAR1 0xFFC01128 -#define SICB_IAR2 0xFFC0112C -#define SICB_IAR3 0xFFC01130 -#define SICB_IAR4 0xFFC01134 -#define SICB_IAR5 0xFFC01138 -#define SICB_IAR6 0xFFC0113C -#define SICB_IAR7 0xFFC01140 -#define PPI0_CONTROL 0xFFC01000 -#define PPI0_STATUS 0xFFC01004 -#define PPI0_DELAY 0xFFC0100C -#define PPI0_COUNT 0xFFC01008 -#define PPI0_FRAME 0xFFC01010 -#define PPI1_CONTROL 0xFFC01300 -#define PPI1_STATUS 0xFFC01304 -#define PPI1_DELAY 0xFFC0130C -#define PPI1_COUNT 0xFFC01308 -#define PPI1_FRAME 0xFFC01310 -#define TBUFCTL 0xFFE06000 -#define TBUFSTAT 0xFFE06004 -#define TBUF 0xFFE06100 -#define PFCTL 0xFFE08000 -#define PFCNTR0 0xFFE08100 -#define PFCNTR1 0xFFE08104 -#define SRAM_BASE_ADDR_CORE_A 0xFFE00000 -#define SRAM_BASE_ADDR_CORE_B 0xFFE00000 -#define EVT_OVERRIDE 0xFFE02100 -#define UART_THR 0xFFC00400 -#define UART_RBR 0xFFC00400 -#define UART_DLL 0xFFC00400 -#define UART_DLH 0xFFC00404 -#define UART_IER 0xFFC00404 -#define UART_IIR 0xFFC00408 -#define UART_LCR 0xFFC0040C -#define UART_MCR 0xFFC00410 -#define UART_LSR 0xFFC00414 -#define UART_MSR 0xFFC00418 -#define UART_SCR 0xFFC0041C -#define UART_GCTL 0xFFC00424 -#define UART_GBL 0xFFC00424 -#define EBIU_AMGCTL 0xFFC00A00 -#define EBIU_AMBCTL0 0xFFC00A04 -#define EBIU_AMBCTL1 0xFFC00A08 -#define EBIU_SDGCTL 0xFFC00A10 -#define EBIU_SDBCTL 0xFFC00A14 -#define EBIU_SDRRC 0xFFC00A18 -#define EBIU_SDSTAT 0xFFC00A1C -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA03FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA03FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) - -#endif /* __BFIN_DEF_ADSP_BF561_proc__ */ |