summaryrefslogtreecommitdiff
path: root/include/asm-blackfin/mach-bf548
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-blackfin/mach-bf548')
-rw-r--r--include/asm-blackfin/mach-bf548/BF541_cdef.h3
-rw-r--r--include/asm-blackfin/mach-bf548/BF541_def.h1
-rw-r--r--include/asm-blackfin/mach-bf548/BF542_cdef.h3
-rw-r--r--include/asm-blackfin/mach-bf548/BF542_def.h1
-rw-r--r--include/asm-blackfin/mach-bf548/BF544_cdef.h3
-rw-r--r--include/asm-blackfin/mach-bf548/BF544_def.h1
-rw-r--r--include/asm-blackfin/mach-bf548/BF547_cdef.h3
-rw-r--r--include/asm-blackfin/mach-bf548/BF547_def.h1
-rw-r--r--include/asm-blackfin/mach-bf548/BF548_cdef.h3
-rw-r--r--include/asm-blackfin/mach-bf548/BF548_def.h1
-rw-r--r--include/asm-blackfin/mach-bf548/BF549_cdef.h3
-rw-r--r--include/asm-blackfin/mach-bf548/BF549_def.h1
-rw-r--r--include/asm-blackfin/mach-bf548/anomaly.h78
-rw-r--r--include/asm-blackfin/mach-bf548/ports.h64
14 files changed, 104 insertions, 62 deletions
diff --git a/include/asm-blackfin/mach-bf548/BF541_cdef.h b/include/asm-blackfin/mach-bf548/BF541_cdef.h
index c0d2a42..1b8c79b 100644
--- a/include/asm-blackfin/mach-bf548/BF541_cdef.h
+++ b/include/asm-blackfin/mach-bf548/BF541_cdef.h
@@ -310,9 +310,6 @@
#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
#define bfin_read_IPRIO() bfin_read32(IPRIO)
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
diff --git a/include/asm-blackfin/mach-bf548/BF541_def.h b/include/asm-blackfin/mach-bf548/BF541_def.h
index 2f9cec6..1469ac2 100644
--- a/include/asm-blackfin/mach-bf548/BF541_def.h
+++ b/include/asm-blackfin/mach-bf548/BF541_def.h
@@ -110,7 +110,6 @@
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define DSPID 0xFFE05000
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
#define TBUF 0xFFE06100 /* Trace Buffer */
diff --git a/include/asm-blackfin/mach-bf548/BF542_cdef.h b/include/asm-blackfin/mach-bf548/BF542_cdef.h
index be48dfd..306b5f1 100644
--- a/include/asm-blackfin/mach-bf548/BF542_cdef.h
+++ b/include/asm-blackfin/mach-bf548/BF542_cdef.h
@@ -310,9 +310,6 @@
#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
#define bfin_read_IPRIO() bfin_read32(IPRIO)
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
diff --git a/include/asm-blackfin/mach-bf548/BF542_def.h b/include/asm-blackfin/mach-bf548/BF542_def.h
index c2be4de..40fe555 100644
--- a/include/asm-blackfin/mach-bf548/BF542_def.h
+++ b/include/asm-blackfin/mach-bf548/BF542_def.h
@@ -110,7 +110,6 @@
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define DSPID 0xFFE05000
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
#define TBUF 0xFFE06100 /* Trace Buffer */
diff --git a/include/asm-blackfin/mach-bf548/BF544_cdef.h b/include/asm-blackfin/mach-bf548/BF544_cdef.h
index b3232fc..47ef6e1 100644
--- a/include/asm-blackfin/mach-bf548/BF544_cdef.h
+++ b/include/asm-blackfin/mach-bf548/BF544_cdef.h
@@ -310,9 +310,6 @@
#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
#define bfin_read_IPRIO() bfin_read32(IPRIO)
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
diff --git a/include/asm-blackfin/mach-bf548/BF544_def.h b/include/asm-blackfin/mach-bf548/BF544_def.h
index 834b7a6..042e2ac 100644
--- a/include/asm-blackfin/mach-bf548/BF544_def.h
+++ b/include/asm-blackfin/mach-bf548/BF544_def.h
@@ -110,7 +110,6 @@
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define DSPID 0xFFE05000
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
#define TBUF 0xFFE06100 /* Trace Buffer */
diff --git a/include/asm-blackfin/mach-bf548/BF547_cdef.h b/include/asm-blackfin/mach-bf548/BF547_cdef.h
index e1a1daf..42d041a 100644
--- a/include/asm-blackfin/mach-bf548/BF547_cdef.h
+++ b/include/asm-blackfin/mach-bf548/BF547_cdef.h
@@ -310,9 +310,6 @@
#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
#define bfin_read_IPRIO() bfin_read32(IPRIO)
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
diff --git a/include/asm-blackfin/mach-bf548/BF547_def.h b/include/asm-blackfin/mach-bf548/BF547_def.h
index bb7ae5e..1cb3381 100644
--- a/include/asm-blackfin/mach-bf548/BF547_def.h
+++ b/include/asm-blackfin/mach-bf548/BF547_def.h
@@ -110,7 +110,6 @@
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define DSPID 0xFFE05000
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
#define TBUF 0xFFE06100 /* Trace Buffer */
diff --git a/include/asm-blackfin/mach-bf548/BF548_cdef.h b/include/asm-blackfin/mach-bf548/BF548_cdef.h
index 6cdfbf3..cf02834 100644
--- a/include/asm-blackfin/mach-bf548/BF548_cdef.h
+++ b/include/asm-blackfin/mach-bf548/BF548_cdef.h
@@ -310,9 +310,6 @@
#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
#define bfin_read_IPRIO() bfin_read32(IPRIO)
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
diff --git a/include/asm-blackfin/mach-bf548/BF548_def.h b/include/asm-blackfin/mach-bf548/BF548_def.h
index e725102..950ce43 100644
--- a/include/asm-blackfin/mach-bf548/BF548_def.h
+++ b/include/asm-blackfin/mach-bf548/BF548_def.h
@@ -110,7 +110,6 @@
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define DSPID 0xFFE05000
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
#define TBUF 0xFFE06100 /* Trace Buffer */
diff --git a/include/asm-blackfin/mach-bf548/BF549_cdef.h b/include/asm-blackfin/mach-bf548/BF549_cdef.h
index 9ac8c2d..3514cef 100644
--- a/include/asm-blackfin/mach-bf548/BF549_cdef.h
+++ b/include/asm-blackfin/mach-bf548/BF549_cdef.h
@@ -310,9 +310,6 @@
#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
#define bfin_read_IPRIO() bfin_read32(IPRIO)
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
diff --git a/include/asm-blackfin/mach-bf548/BF549_def.h b/include/asm-blackfin/mach-bf548/BF549_def.h
index f36ecd6..55b0a29 100644
--- a/include/asm-blackfin/mach-bf548/BF549_def.h
+++ b/include/asm-blackfin/mach-bf548/BF549_def.h
@@ -110,7 +110,6 @@
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
-#define DSPID 0xFFE05000
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
#define TBUF 0xFFE06100 /* Trace Buffer */
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
index 0451ea7..1dc75ef 100644
--- a/include/asm-blackfin/mach-bf548/anomaly.h
+++ b/include/asm-blackfin/mach-bf548/anomaly.h
@@ -2,18 +2,18 @@
* File: include/asm-blackfin/mach-bf548/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
- * Copyright (C) 2004-2007 Analog Devices Inc.
+ * Copyright (C) 2004-2008 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
/* This file shoule be up to date with:
- * - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
+ * - Revision F, 06/11/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1)
@@ -43,7 +43,7 @@
#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
/* Synchronous Burst Flash Boot Mode Is Not Functional */
#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
-/* Host DMA Boot Mode Is Not Functional */
+/* Host DMA Boot Modes Are Not Functional */
#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
@@ -61,26 +61,90 @@
#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
/* USB Calibration Value Is Not Intialized */
#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
-/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
+/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
/* Data Lost when Core Reads SDH Data FIFO */
#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
/* PLL Status Register Is Inaccurate */
#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
+/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
+#define ANOMALY_05000353 (1)
+/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
+#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
+/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
+#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (1)
/* External Memory Read Access Hangs Core With PLL Bypass */
#define ANOMALY_05000360 (1)
/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
#define ANOMALY_05000365 (1)
+/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
+#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
/* Addressing Conflict between Boot ROM and Asynchronous Memory */
#define ANOMALY_05000369 (1)
+/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
+#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (__SILICON_REVISION__ < 1)
+#define ANOMALY_05000371 (1)
+/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
+#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
/* Mobile DDR Operation Not Functional */
#define ANOMALY_05000377 (1)
/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
#define ANOMALY_05000378 (1)
+/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
+#define ANOMALY_05000379 (1)
+/* 8-Bit NAND Flash Boot Mode Not Functional */
+#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
+/* Some ATAPI Modes Are Not Functional */
+#define ANOMALY_05000383 (1)
+/* Boot from OTP Memory Not Functional */
+#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
+/* bfrom_SysControl() Firmware Routine Not Functional */
+#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
+/* Programmable Preboot Settings Not Functional */
+#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
+/* CRC32 Checksum Support Not Functional */
+#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
+/* Reset Vector Must Not Be in SDRAM Memory Space */
+#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
+/* Changed Meaning of BCODE Field in SYSCR Register */
+#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
+/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
+#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
+/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
+/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
+/* Log Buffer Not Functional */
+#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
+/* Hook Routine Not Functional */
+#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
+/* Header Indirect Bit Not Functional */
+#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
+/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
+#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
+/* Lockbox SESR Disallows Certain User Interrupts */
+#define ANOMALY_05000404 (1)
+/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
+#define ANOMALY_05000405 (1)
+/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
+#define ANOMALY_05000406 (1)
+/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
+#define ANOMALY_05000407 (1)
+/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
+#define ANOMALY_05000408 (1)
+/* Lockbox firmware leaves MDMA0 channel enabled */
+#define ANOMALY_05000409 (1)
+/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
+#define ANOMALY_05000411 (1)
+/* FIFO Boot Mode Is Not Functional */
+#define ANOMALY_05000412 (1)
+/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
+#define ANOMALY_05000413 (1)
+/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
+#define ANOMALY_05000414 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0)
@@ -93,7 +157,9 @@
#define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0)
+#define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0)
+#define ANOMALY_05000363 (0)
#endif
diff --git a/include/asm-blackfin/mach-bf548/ports.h b/include/asm-blackfin/mach-bf548/ports.h
index c9bd287..c828516 100644
--- a/include/asm-blackfin/mach-bf548/ports.h
+++ b/include/asm-blackfin/mach-bf548/ports.h
@@ -59,38 +59,38 @@
#define PORT_x_MUX_7_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
#define PORT_x_MUX_7_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
#define PORT_x_MUX_7_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_8_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_8_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_8_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_8_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_9_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_9_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_9_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_9_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_10_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_10_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_10_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_10_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_11_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_11_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_11_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_11_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_12_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_12_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_12_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_12_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_13_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_13_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_13_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_13_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_14_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_14_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_14_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_14_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
-#define PORT_x_MUX_15_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_15_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_15_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_15_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
+#define PORT_x_MUX_8_FUNC_1 (PORT_x_MUX_FUNC_1 << 16)
+#define PORT_x_MUX_8_FUNC_2 (PORT_x_MUX_FUNC_2 << 16)
+#define PORT_x_MUX_8_FUNC_3 (PORT_x_MUX_FUNC_3 << 16)
+#define PORT_x_MUX_8_FUNC_4 (PORT_x_MUX_FUNC_4 << 16)
+#define PORT_x_MUX_9_FUNC_1 (PORT_x_MUX_FUNC_1 << 18)
+#define PORT_x_MUX_9_FUNC_2 (PORT_x_MUX_FUNC_2 << 18)
+#define PORT_x_MUX_9_FUNC_3 (PORT_x_MUX_FUNC_3 << 18)
+#define PORT_x_MUX_9_FUNC_4 (PORT_x_MUX_FUNC_4 << 18)
+#define PORT_x_MUX_10_FUNC_1 (PORT_x_MUX_FUNC_1 << 20)
+#define PORT_x_MUX_10_FUNC_2 (PORT_x_MUX_FUNC_2 << 20)
+#define PORT_x_MUX_10_FUNC_3 (PORT_x_MUX_FUNC_3 << 20)
+#define PORT_x_MUX_10_FUNC_4 (PORT_x_MUX_FUNC_4 << 20)
+#define PORT_x_MUX_11_FUNC_1 (PORT_x_MUX_FUNC_1 << 22)
+#define PORT_x_MUX_11_FUNC_2 (PORT_x_MUX_FUNC_2 << 22)
+#define PORT_x_MUX_11_FUNC_3 (PORT_x_MUX_FUNC_3 << 22)
+#define PORT_x_MUX_11_FUNC_4 (PORT_x_MUX_FUNC_4 << 22)
+#define PORT_x_MUX_12_FUNC_1 (PORT_x_MUX_FUNC_1 << 24)
+#define PORT_x_MUX_12_FUNC_2 (PORT_x_MUX_FUNC_2 << 24)
+#define PORT_x_MUX_12_FUNC_3 (PORT_x_MUX_FUNC_3 << 24)
+#define PORT_x_MUX_12_FUNC_4 (PORT_x_MUX_FUNC_4 << 24)
+#define PORT_x_MUX_13_FUNC_1 (PORT_x_MUX_FUNC_1 << 26)
+#define PORT_x_MUX_13_FUNC_2 (PORT_x_MUX_FUNC_2 << 26)
+#define PORT_x_MUX_13_FUNC_3 (PORT_x_MUX_FUNC_3 << 26)
+#define PORT_x_MUX_13_FUNC_4 (PORT_x_MUX_FUNC_4 << 26)
+#define PORT_x_MUX_14_FUNC_1 (PORT_x_MUX_FUNC_1 << 28)
+#define PORT_x_MUX_14_FUNC_2 (PORT_x_MUX_FUNC_2 << 28)
+#define PORT_x_MUX_14_FUNC_3 (PORT_x_MUX_FUNC_3 << 28)
+#define PORT_x_MUX_14_FUNC_4 (PORT_x_MUX_FUNC_4 << 28)
+#define PORT_x_MUX_15_FUNC_1 (PORT_x_MUX_FUNC_1 << 30)
+#define PORT_x_MUX_15_FUNC_2 (PORT_x_MUX_FUNC_2 << 30)
+#define PORT_x_MUX_15_FUNC_3 (PORT_x_MUX_FUNC_3 << 30)
+#define PORT_x_MUX_15_FUNC_4 (PORT_x_MUX_FUNC_4 << 30)
/* Port A Masks */
#define PA0 0x0001
generated by cgit v1.1 at 2024-11-28 01:30:38 +0000