diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf548')
7 files changed, 29 insertions, 201 deletions
diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h index e9572a0..51d9cf2 100644 --- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h +++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h @@ -3577,7 +3577,6 @@ #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) #define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */ -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) #define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */ #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) @@ -3643,7 +3642,6 @@ #define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) #define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) #define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */ -#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX) #define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) #define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */ #define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) @@ -3709,7 +3707,6 @@ #define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) #define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) #define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */ -#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX) #define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) #define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */ #define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_cdef.h index 968cd3e..4c0fdf5 100644 --- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_cdef.h +++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_cdef.h @@ -4678,7 +4678,6 @@ #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) #define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */ -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) #define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */ #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) @@ -4744,7 +4743,6 @@ #define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) #define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) #define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */ -#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX) #define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) #define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */ #define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) @@ -4810,7 +4808,6 @@ #define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) #define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) #define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */ -#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX) #define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) #define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */ #define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_cdef.h index bd40f35..e0f76ae 100644 --- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_cdef.h +++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_cdef.h @@ -2713,7 +2713,6 @@ #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) #define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */ -#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) #define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */ #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) @@ -2779,7 +2778,6 @@ #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) #define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */ -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) #define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */ #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) @@ -2845,7 +2843,6 @@ #define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) #define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) #define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */ -#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX) #define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) #define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */ #define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) @@ -2911,7 +2908,6 @@ #define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) #define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) #define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */ -#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX) #define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) #define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */ #define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_cdef.h index 77cd5dc..caf2f6f 100644 --- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_cdef.h +++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_cdef.h @@ -4885,7 +4885,6 @@ #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) #define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */ -#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) #define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */ #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) @@ -4951,7 +4950,6 @@ #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) #define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */ -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) #define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */ #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) @@ -5017,7 +5015,6 @@ #define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) #define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) #define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */ -#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX) #define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) #define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */ #define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) @@ -5083,7 +5080,6 @@ #define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) #define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) #define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */ -#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX) #define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) #define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */ #define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_cdef.h index c5d3511..af90e4c 100644 --- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_cdef.h +++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_cdef.h @@ -5233,7 +5233,6 @@ #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) #define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */ -#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) #define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */ #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) @@ -5299,7 +5298,6 @@ #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) #define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */ -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) #define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */ #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) @@ -5365,7 +5363,6 @@ #define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) #define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) #define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */ -#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX) #define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) #define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */ #define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) @@ -5431,7 +5428,6 @@ #define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) #define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) #define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */ -#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX) #define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) #define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */ #define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h index 3b54309..882e40c 100644 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -2,12 +2,12 @@ * File: include/asm-blackfin/mach-bf548/anomaly.h * Bugs: Enter bugs at http://blackfin.uclinux.org/ * - * Copyright (C) 2004-2008 Analog Devices Inc. + * Copyright (C) 2004-2009 Analog Devices Inc. * Licensed under the GPL-2 or later. */ /* This file shoule be up to date with: - * - Revision G, 08/07/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List + * - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -91,8 +91,6 @@ #define ANOMALY_05000371 (__SILICON_REVISION__ < 2) /* USB DP/DM Data Pins May Lose State When Entering Hibernate */ #define ANOMALY_05000372 (__SILICON_REVISION__ < 1) -/* Mobile DDR Operation Not Functional */ -#define ANOMALY_05000377 (1) /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ #define ANOMALY_05000378 (__SILICON_REVISION__ < 2) /* 16-Bit NAND FLASH Boot Mode Is Not Functional */ @@ -157,8 +155,22 @@ #define ANOMALY_05000429 (__SILICON_REVISION__ < 2) /* Software System Reset Corrupts PLL_LOCKCNT Register */ #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) +/* Incorrect Use of Stack in Lockbox Firmware During Authentication */ +#define ANOMALY_05000431 (__SILICON_REVISION__ < 3) +/* OTP Write Accesses Not Supported */ +#define ANOMALY_05000442 (__SILICON_REVISION__ < 1) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) +/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */ +#define ANOMALY_05000446 (1) +/* UART IrDA Receiver Fails on Extended Bit Pulses */ +#define ANOMALY_05000447 (1) +/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */ +#define ANOMALY_05000448 (__SILICON_REVISION__ == 1) +/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */ +#define ANOMALY_05000449 (__SILICON_REVISION__ == 1) +/* USB DMA Mode 1 Short Packet Data Corruption */ +#define ANOMALY_05000450 (1 /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) @@ -171,10 +183,13 @@ #define ANOMALY_05000263 (0) #define ANOMALY_05000266 (0) #define ANOMALY_05000273 (0) +#define ANOMALY_05000278 (0) +#define ANOMALY_05000305 (0) #define ANOMALY_05000307 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000363 (0) +#define ANOMALY_05000380 (0) #define ANOMALY_05000412 (0) #define ANOMALY_05000432 (0) #define ANOMALY_05000435 (0) diff --git a/include/asm-blackfin/mach-bf548/ports.h b/include/asm-blackfin/mach-bf548/ports.h index 5f0e45e..50054f3 100644 --- a/include/asm-blackfin/mach-bf548/ports.h +++ b/include/asm-blackfin/mach-bf548/ports.h @@ -92,184 +92,15 @@ #define PORT_x_MUX_15_FUNC_3 (PORT_x_MUX_FUNC_3 << 30) #define PORT_x_MUX_15_FUNC_4 (PORT_x_MUX_FUNC_4 << 30) -/* Port A Masks */ -#define PA0 0x0001 -#define PA1 0x0002 -#define PA2 0x0004 -#define PA3 0x0008 -#define PA4 0x0010 -#define PA5 0x0020 -#define PA6 0x0040 -#define PA7 0x0080 -#define PA8 0x0100 -#define PA9 0x0200 -#define PA10 0x0400 -#define PA11 0x0800 -#define PA12 0x1000 -#define PA13 0x2000 -#define PA14 0x4000 -#define PA15 0x8000 - -/* Port B Masks */ -#define PB0 0x0001 -#define PB1 0x0002 -#define PB2 0x0004 -#define PB3 0x0008 -#define PB4 0x0010 -#define PB5 0x0020 -#define PB6 0x0040 -#define PB7 0x0080 -#define PB8 0x0100 -#define PB9 0x0200 -#define PB10 0x0400 -#define PB11 0x0800 -#define PB12 0x1000 -#define PB13 0x2000 -#define PB14 0x4000 -#define PB15 0x8000 - -/* Port C Masks */ -#define PC0 0x0001 -#define PC1 0x0002 -#define PC2 0x0004 -#define PC3 0x0008 -#define PC4 0x0010 -#define PC5 0x0020 -#define PC6 0x0040 -#define PC7 0x0080 -#define PC8 0x0100 -#define PC9 0x0200 -#define PC10 0x0400 -#define PC11 0x0800 -#define PC12 0x1000 -#define PC13 0x2000 -#define PC14 0x4000 -#define PC15 0x8000 - -/* Port F Masks */ -#define PD0 0x0001 -#define PD1 0x0002 -#define PD2 0x0004 -#define PD3 0x0008 -#define PD4 0x0010 -#define PD5 0x0020 -#define PD6 0x0040 -#define PD7 0x0080 -#define PD8 0x0100 -#define PD9 0x0200 -#define PD10 0x0400 -#define PD11 0x0800 -#define PD12 0x1000 -#define PD13 0x2000 -#define PD14 0x4000 -#define PD15 0x8000 - -/* Port F Masks */ -#define PE0 0x0001 -#define PE1 0x0002 -#define PE2 0x0004 -#define PE3 0x0008 -#define PE4 0x0010 -#define PE5 0x0020 -#define PE6 0x0040 -#define PE7 0x0080 -#define PE8 0x0100 -#define PE9 0x0200 -#define PE10 0x0400 -#define PE11 0x0800 -#define PE12 0x1000 -#define PE13 0x2000 -#define PE14 0x4000 -#define PE15 0x8000 - -/* Port F Masks */ -#define PF0 0x0001 -#define PF1 0x0002 -#define PF2 0x0004 -#define PF3 0x0008 -#define PF4 0x0010 -#define PF5 0x0020 -#define PF6 0x0040 -#define PF7 0x0080 -#define PF8 0x0100 -#define PF9 0x0200 -#define PF10 0x0400 -#define PF11 0x0800 -#define PF12 0x1000 -#define PF13 0x2000 -#define PF14 0x4000 -#define PF15 0x8000 - -/* Port G Masks */ -#define PG0 0x0001 -#define PG1 0x0002 -#define PG2 0x0004 -#define PG3 0x0008 -#define PG4 0x0010 -#define PG5 0x0020 -#define PG6 0x0040 -#define PG7 0x0080 -#define PG8 0x0100 -#define PG9 0x0200 -#define PG10 0x0400 -#define PG11 0x0800 -#define PG12 0x1000 -#define PG13 0x2000 -#define PG14 0x4000 -#define PG15 0x8000 - -/* Port H Masks */ -#define PH0 0x0001 -#define PH1 0x0002 -#define PH2 0x0004 -#define PH3 0x0008 -#define PH4 0x0010 -#define PH5 0x0020 -#define PH6 0x0040 -#define PH7 0x0080 -#define PH8 0x0100 -#define PH9 0x0200 -#define PH10 0x0400 -#define PH11 0x0800 -#define PH12 0x1000 -#define PH13 0x2000 -#define PH14 0x4000 -#define PH15 0x8000 - -/* Port I Masks */ -#define PI0 0x0001 -#define PI1 0x0002 -#define PI2 0x0004 -#define PI3 0x0008 -#define PI4 0x0010 -#define PI5 0x0020 -#define PI6 0x0040 -#define PI7 0x0080 -#define PI8 0x0100 -#define PI9 0x0200 -#define PI10 0x0400 -#define PI11 0x0800 -#define PI12 0x1000 -#define PI13 0x2000 -#define PI14 0x4000 -#define PI15 0x8000 - -/* Port I Masks */ -#define PJ0 0x0001 -#define PJ1 0x0002 -#define PJ2 0x0004 -#define PJ3 0x0008 -#define PJ4 0x0010 -#define PJ5 0x0020 -#define PJ6 0x0040 -#define PJ7 0x0080 -#define PJ8 0x0100 -#define PJ9 0x0200 -#define PJ10 0x0400 -#define PJ11 0x0800 -#define PJ12 0x1000 -#define PJ13 0x2000 -#define PJ14 0x4000 -#define PJ15 0x8000 +#include "../mach-common/bits/ports-a.h" +#include "../mach-common/bits/ports-b.h" +#include "../mach-common/bits/ports-c.h" +#include "../mach-common/bits/ports-d.h" +#include "../mach-common/bits/ports-e.h" +#include "../mach-common/bits/ports-f.h" +#include "../mach-common/bits/ports-g.h" +#include "../mach-common/bits/ports-h.h" +#include "../mach-common/bits/ports-i.h" +#include "../mach-common/bits/ports-j.h" #endif |