diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf527')
| -rw-r--r-- | include/asm-blackfin/mach-bf527/anomaly.h | 40 |
1 files changed, 32 insertions, 8 deletions
diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h index df6808d..0fd7e31 100644 --- a/include/asm-blackfin/mach-bf527/anomaly.h +++ b/include/asm-blackfin/mach-bf527/anomaly.h @@ -6,9 +6,9 @@ * Licensed under the GPL-2 or later. */ -/* This file shoule be up to date with: +/* This file should be up to date with: * - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List - * - Revision E, 08/18/2008; ADSP-BF527 Blackfin Processor Anomaly List + * - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -25,14 +25,16 @@ # define ANOMALY_BF527 0 #endif -/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ +/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ #define ANOMALY_05000074 (1) /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ #define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ +/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) +/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ +#define ANOMALY_05000254 (1) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ @@ -41,6 +43,8 @@ #define ANOMALY_05000313 (__SILICON_REVISION__ < 2) /* Incorrect Access of OTP_STATUS During otp_write() Function */ #define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* Host DMA Boot Modes Are Not Functional */ +#define ANOMALY_05000330 (__SILICON_REVISION__ < 2) /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ #define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ @@ -75,8 +79,6 @@ #define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* 8-Bit NAND Flash Boot Mode Not Functional */ #define ANOMALY_05000382 (__SILICON_REVISION__ < 2) -/* Host Must Not Read Back During Host DMA Boot */ -#define ANOMALY_05000384 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* Boot from OTP Memory Not Functional */ #define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* bfrom_SysControl() Firmware Routine Not Functional */ @@ -129,7 +131,7 @@ #define ANOMALY_05000416 (1) /* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */ #define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) -/* tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */ +/* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */ #define ANOMALY_05000418 (__SILICON_REVISION__ < 2) /* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */ #define ANOMALY_05000420 (__SILICON_REVISION__ < 2) @@ -143,25 +145,46 @@ #define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ #define ANOMALY_05000425 (__SILICON_REVISION__ < 2) -/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */ +/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ #define ANOMALY_05000426 (1) /* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */ #define ANOMALY_05000429 (__SILICON_REVISION__ < 2) /* Software System Reset Corrupts PLL_LOCKCNT Register */ #define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) +/* Incorrect Use of Stack in Lockbox Firmware During Authentication */ +#define ANOMALY_05000431 (1) /* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ #define ANOMALY_05000432 (ANOMALY_BF526) /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ #define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527) +/* Preboot Cannot be Used to Alter the PLL_DIV Register */ +#define ANOMALY_05000439 (1) +/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ +#define ANOMALY_05000440 (1) +/* OTP Write Accesses Not Supported */ +#define ANOMALY_05000442 (__SILICON_REVISION__ < 1) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) +/* The WURESET Bit in the SYSCR Register is not Functional */ +#define ANOMALY_05000445 (1) +/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ +#define ANOMALY_05000451 (1) +/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ +#define ANOMALY_05000452 (1) +/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ +#define ANOMALY_05000456 (1) +/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ +#define ANOMALY_05000457 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) #define ANOMALY_05000158 (0) +#define ANOMALY_05000171 (0) #define ANOMALY_05000183 (0) #define ANOMALY_05000198 (0) +#define ANOMALY_05000227 (0) #define ANOMALY_05000230 (0) +#define ANOMALY_05000242 (0) #define ANOMALY_05000244 (0) #define ANOMALY_05000261 (0) #define ANOMALY_05000263 (0) @@ -174,6 +197,7 @@ #define ANOMALY_05000311 (0) #define ANOMALY_05000312 (0) #define ANOMALY_05000323 (0) +#define ANOMALY_05000362 (1) #define ANOMALY_05000363 (0) #define ANOMALY_05000412 (0) #define ANOMALY_05000447 (0) |