diff options
Diffstat (limited to 'include/asm-blackfin/mach-bf527')
| -rw-r--r-- | include/asm-blackfin/mach-bf527/BF522_def.h | 15 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf527/BF523_def.h | 15 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf527/BF524_def.h | 15 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf527/BF525_def.h | 15 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf527/BF526_def.h | 15 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf527/BF527_def.h | 15 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf527/def_local.h | 1 | ||||
| -rw-r--r-- | include/asm-blackfin/mach-bf527/mem_map.h | 21 |
8 files changed, 22 insertions, 90 deletions
diff --git a/include/asm-blackfin/mach-bf527/BF522_def.h b/include/asm-blackfin/mach-bf527/BF522_def.h index 44143ba..bc05029 100644 --- a/include/asm-blackfin/mach-bf527/BF522_def.h +++ b/include/asm-blackfin/mach-bf527/BF522_def.h @@ -119,20 +119,5 @@ #define TPERIOD 0xFFE03004 /* Core Timer Period Register */ #define TSCALE 0xFFE03008 /* Core Timer Scale Register */ #define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF522_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF523_def.h b/include/asm-blackfin/mach-bf527/BF523_def.h index 02675a9..c27fd64 100644 --- a/include/asm-blackfin/mach-bf527/BF523_def.h +++ b/include/asm-blackfin/mach-bf527/BF523_def.h @@ -119,20 +119,5 @@ #define TPERIOD 0xFFE03004 /* Core Timer Period Register */ #define TSCALE 0xFFE03008 /* Core Timer Scale Register */ #define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF523_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF524_def.h b/include/asm-blackfin/mach-bf527/BF524_def.h index 10793e8..bd6aa8f 100644 --- a/include/asm-blackfin/mach-bf527/BF524_def.h +++ b/include/asm-blackfin/mach-bf527/BF524_def.h @@ -288,20 +288,5 @@ #define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ #define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF524_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF525_def.h b/include/asm-blackfin/mach-bf527/BF525_def.h index c4c2f2f..5e88b3b 100644 --- a/include/asm-blackfin/mach-bf527/BF525_def.h +++ b/include/asm-blackfin/mach-bf527/BF525_def.h @@ -288,20 +288,5 @@ #define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ #define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF525_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF526_def.h b/include/asm-blackfin/mach-bf527/BF526_def.h index 04db6c7..2644abf 100644 --- a/include/asm-blackfin/mach-bf527/BF526_def.h +++ b/include/asm-blackfin/mach-bf527/BF526_def.h @@ -367,20 +367,5 @@ #define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ #define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF526_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/BF527_def.h b/include/asm-blackfin/mach-bf527/BF527_def.h index c1e1aab..c46c2b0 100644 --- a/include/asm-blackfin/mach-bf527/BF527_def.h +++ b/include/asm-blackfin/mach-bf527/BF527_def.h @@ -367,20 +367,5 @@ #define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ #define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF527_proc__ */ diff --git a/include/asm-blackfin/mach-bf527/def_local.h b/include/asm-blackfin/mach-bf527/def_local.h index 14c111f..81eca83 100644 --- a/include/asm-blackfin/mach-bf527/def_local.h +++ b/include/asm-blackfin/mach-bf527/def_local.h @@ -1 +1,2 @@ +#include "mem_map.h" #include "ports.h" diff --git a/include/asm-blackfin/mach-bf527/mem_map.h b/include/asm-blackfin/mach-bf527/mem_map.h new file mode 100644 index 0000000..8386b4b --- /dev/null +++ b/include/asm-blackfin/mach-bf527/mem_map.h @@ -0,0 +1,21 @@ +/* + * Common Blackfin memory map + * + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#ifndef __BF52X_MEM_MAP_H__ +#define __BF52X_MEM_MAP_H__ + +#define L1_DATA_A_SRAM (0xFF800000) +#define L1_DATA_A_SRAM_SIZE (0x4000) +#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) +#define L1_DATA_B_SRAM (0xFF900000) +#define L1_DATA_B_SRAM_SIZE (0x4000) +#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) +#define L1_INST_SRAM (0xFFA00000) +#define L1_INST_SRAM_SIZE (0xC000) +#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) + +#endif |