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-rw-r--r--include/asm-avr32/arch-at32ap700x/clk.h21
-rw-r--r--include/asm-avr32/global_data.h3
-rw-r--r--include/asm-avr32/io.h4
3 files changed, 15 insertions, 13 deletions
diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h
index 21545a3..d83e93b 100644
--- a/include/asm-avr32/arch-at32ap700x/clk.h
+++ b/include/asm-avr32/arch-at32ap700x/clk.h
@@ -26,27 +26,28 @@
#include <asm/arch/portmux.h>
#ifdef CONFIG_PLL
-#define PLL0_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
+#define PLL0_RATE ((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV) \
+ * CONFIG_SYS_PLL0_MUL)
#define MAIN_CLK_RATE PLL0_RATE
#else
-#define MAIN_CLK_RATE (CFG_OSC0_HZ)
+#define MAIN_CLK_RATE (CONFIG_SYS_OSC0_HZ)
#endif
static inline unsigned long get_cpu_clk_rate(void)
{
- return MAIN_CLK_RATE >> CFG_CLKDIV_CPU;
+ return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_CPU;
}
static inline unsigned long get_hsb_clk_rate(void)
{
- return MAIN_CLK_RATE >> CFG_CLKDIV_HSB;
+ return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB;
}
static inline unsigned long get_pba_clk_rate(void)
{
- return MAIN_CLK_RATE >> CFG_CLKDIV_PBA;
+ return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBA;
}
static inline unsigned long get_pbb_clk_rate(void)
{
- return MAIN_CLK_RATE >> CFG_CLKDIV_PBB;
+ return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBB;
}
/* Accessors for specific devices. More will be added as needed. */
@@ -86,7 +87,7 @@ static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
extern void clk_init(void);
/* Board code may need the SDRAM base clock as a compile-time constant */
-#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB)
+#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB)
/* Generic clock control */
enum gclk_parent {
@@ -124,11 +125,11 @@ static inline unsigned long gclk_set_rate(unsigned int id,
switch (parent) {
case GCLK_PARENT_OSC0:
- parent_rate = CFG_OSC0_HZ;
+ parent_rate = CONFIG_SYS_OSC0_HZ;
break;
-#ifdef CFG_OSC1_HZ
+#ifdef CONFIG_SYS_OSC1_HZ
case GCLK_PARENT_OSC1:
- parent_rate = CFG_OSC1_HZ;
+ parent_rate = CONFIG_SYS_OSC1_HZ;
break;
#endif
#ifdef PLL0_RATE
diff --git a/include/asm-avr32/global_data.h b/include/asm-avr32/global_data.h
index 007cfe4..97a6c61 100644
--- a/include/asm-avr32/global_data.h
+++ b/include/asm-avr32/global_data.h
@@ -29,7 +29,7 @@
* global variables during system initialization (until we have set
* up the memory controller so that we can use RAM).
*
- * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
*/
typedef struct global_data {
@@ -54,6 +54,7 @@ typedef struct global_data {
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */
+#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5")
diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h
index 06e52b1..50967ac 100644
--- a/include/asm-avr32/io.h
+++ b/include/asm-avr32/io.h
@@ -76,12 +76,12 @@ extern void __readwrite_bug(const char *fn);
#include <asm/addrspace.h>
/* virt_to_phys will only work when address is in P1 or P2 */
-static __inline__ unsigned long virt_to_phys(volatile void *address)
+static inline phys_addr_t virt_to_phys(volatile void *address)
{
return PHYSADDR(address);
}
-static __inline__ void * phys_to_virt(unsigned long address)
+static inline void *phys_to_virt(phys_addr_t address)
{
return (void *)P1SEGADDR(address);
}