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-rw-r--r--include/asm-avr32/arch-at32ap700x/chip-features.h34
-rw-r--r--include/asm-avr32/arch-at32ap700x/clk.h78
-rw-r--r--include/asm-avr32/arch-at32ap700x/gpio.h220
-rw-r--r--include/asm-avr32/arch-at32ap700x/hmatrix2.h232
-rw-r--r--include/asm-avr32/arch-at32ap700x/memory-map.h66
-rw-r--r--include/asm-avr32/arch-at32ap700x/mmc.h96
6 files changed, 726 insertions, 0 deletions
diff --git a/include/asm-avr32/arch-at32ap700x/chip-features.h b/include/asm-avr32/arch-at32ap700x/chip-features.h
new file mode 100644
index 0000000..29b1fd6
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap700x/chip-features.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2007 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_ARCH_CHIP_FEATURES_H__
+#define __ASM_AVR32_ARCH_CHIP_FEATURES_H__
+
+/* Currently, all the AP700x chips have these */
+#define AT32AP700x_CHIP_HAS_USART
+#define AT32AP700x_CHIP_HAS_MMCI
+
+/* Only AP7000 has ethernet interface */
+#ifdef CONFIG_AT32AP7000
+#define AT32AP700x_CHIP_HAS_MACB
+#endif
+
+#endif /* __ASM_AVR32_ARCH_CHIP_FEATURES_H__ */
diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h
new file mode 100644
index 0000000..ea84c08
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap700x/clk.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_ARCH_CLK_H__
+#define __ASM_AVR32_ARCH_CLK_H__
+
+#include <asm/arch/chip-features.h>
+
+#ifdef CONFIG_PLL
+#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
+#else
+#define MAIN_CLK_RATE (CFG_OSC0_HZ)
+#endif
+
+static inline unsigned long get_cpu_clk_rate(void)
+{
+ return MAIN_CLK_RATE >> CFG_CLKDIV_CPU;
+}
+static inline unsigned long get_hsb_clk_rate(void)
+{
+ return MAIN_CLK_RATE >> CFG_CLKDIV_HSB;
+}
+static inline unsigned long get_pba_clk_rate(void)
+{
+ return MAIN_CLK_RATE >> CFG_CLKDIV_PBA;
+}
+static inline unsigned long get_pbb_clk_rate(void)
+{
+ return MAIN_CLK_RATE >> CFG_CLKDIV_PBB;
+}
+
+/* Accessors for specific devices. More will be added as needed. */
+static inline unsigned long get_sdram_clk_rate(void)
+{
+ return get_hsb_clk_rate();
+}
+#ifdef AT32AP700x_CHIP_HAS_USART
+static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
+{
+ return get_pba_clk_rate();
+}
+#endif
+#ifdef AT32AP700x_CHIP_HAS_USART
+static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
+{
+ return get_pbb_clk_rate();
+}
+static inline unsigned long get_macb_hclk_rate(unsigned int dev_id)
+{
+ return get_hsb_clk_rate();
+}
+#endif
+#ifdef AT32AP700x_CHIP_HAS_MMCI
+static inline unsigned long get_mci_clk_rate(void)
+{
+ return get_pbb_clk_rate();
+}
+#endif
+
+#endif /* __ASM_AVR32_ARCH_CLK_H__ */
diff --git a/include/asm-avr32/arch-at32ap700x/gpio.h b/include/asm-avr32/arch-at32ap700x/gpio.h
new file mode 100644
index 0000000..b10a3e4
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap700x/gpio.h
@@ -0,0 +1,220 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_ARCH_GPIO_H__
+#define __ASM_AVR32_ARCH_GPIO_H__
+
+#include <asm/arch/chip-features.h>
+#include <asm/arch/memory-map.h>
+
+#define NR_GPIO_CONTROLLERS 5
+
+/*
+ * Pin numbers identifying specific GPIO pins on the chip.
+ */
+#define GPIO_PIOA_BASE (0)
+#define GPIO_PIN_PA0 (GPIO_PIOA_BASE + 0)
+#define GPIO_PIN_PA1 (GPIO_PIOA_BASE + 1)
+#define GPIO_PIN_PA2 (GPIO_PIOA_BASE + 2)
+#define GPIO_PIN_PA3 (GPIO_PIOA_BASE + 3)
+#define GPIO_PIN_PA4 (GPIO_PIOA_BASE + 4)
+#define GPIO_PIN_PA5 (GPIO_PIOA_BASE + 5)
+#define GPIO_PIN_PA6 (GPIO_PIOA_BASE + 6)
+#define GPIO_PIN_PA7 (GPIO_PIOA_BASE + 7)
+#define GPIO_PIN_PA8 (GPIO_PIOA_BASE + 8)
+#define GPIO_PIN_PA9 (GPIO_PIOA_BASE + 9)
+#define GPIO_PIN_PA10 (GPIO_PIOA_BASE + 10)
+#define GPIO_PIN_PA11 (GPIO_PIOA_BASE + 11)
+#define GPIO_PIN_PA12 (GPIO_PIOA_BASE + 12)
+#define GPIO_PIN_PA13 (GPIO_PIOA_BASE + 13)
+#define GPIO_PIN_PA14 (GPIO_PIOA_BASE + 14)
+#define GPIO_PIN_PA15 (GPIO_PIOA_BASE + 15)
+#define GPIO_PIN_PA16 (GPIO_PIOA_BASE + 16)
+#define GPIO_PIN_PA17 (GPIO_PIOA_BASE + 17)
+#define GPIO_PIN_PA18 (GPIO_PIOA_BASE + 18)
+#define GPIO_PIN_PA19 (GPIO_PIOA_BASE + 19)
+#define GPIO_PIN_PA20 (GPIO_PIOA_BASE + 20)
+#define GPIO_PIN_PA21 (GPIO_PIOA_BASE + 21)
+#define GPIO_PIN_PA22 (GPIO_PIOA_BASE + 22)
+#define GPIO_PIN_PA23 (GPIO_PIOA_BASE + 23)
+#define GPIO_PIN_PA24 (GPIO_PIOA_BASE + 24)
+#define GPIO_PIN_PA25 (GPIO_PIOA_BASE + 25)
+#define GPIO_PIN_PA26 (GPIO_PIOA_BASE + 26)
+#define GPIO_PIN_PA27 (GPIO_PIOA_BASE + 27)
+#define GPIO_PIN_PA28 (GPIO_PIOA_BASE + 28)
+#define GPIO_PIN_PA29 (GPIO_PIOA_BASE + 29)
+#define GPIO_PIN_PA30 (GPIO_PIOA_BASE + 30)
+#define GPIO_PIN_PA31 (GPIO_PIOA_BASE + 31)
+
+#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
+#define GPIO_PIN_PB0 (GPIO_PIOB_BASE + 0)
+#define GPIO_PIN_PB1 (GPIO_PIOB_BASE + 1)
+#define GPIO_PIN_PB2 (GPIO_PIOB_BASE + 2)
+#define GPIO_PIN_PB3 (GPIO_PIOB_BASE + 3)
+#define GPIO_PIN_PB4 (GPIO_PIOB_BASE + 4)
+#define GPIO_PIN_PB5 (GPIO_PIOB_BASE + 5)
+#define GPIO_PIN_PB6 (GPIO_PIOB_BASE + 6)
+#define GPIO_PIN_PB7 (GPIO_PIOB_BASE + 7)
+#define GPIO_PIN_PB8 (GPIO_PIOB_BASE + 8)
+#define GPIO_PIN_PB9 (GPIO_PIOB_BASE + 9)
+#define GPIO_PIN_PB10 (GPIO_PIOB_BASE + 10)
+#define GPIO_PIN_PB11 (GPIO_PIOB_BASE + 11)
+#define GPIO_PIN_PB12 (GPIO_PIOB_BASE + 12)
+#define GPIO_PIN_PB13 (GPIO_PIOB_BASE + 13)
+#define GPIO_PIN_PB14 (GPIO_PIOB_BASE + 14)
+#define GPIO_PIN_PB15 (GPIO_PIOB_BASE + 15)
+#define GPIO_PIN_PB16 (GPIO_PIOB_BASE + 16)
+#define GPIO_PIN_PB17 (GPIO_PIOB_BASE + 17)
+#define GPIO_PIN_PB18 (GPIO_PIOB_BASE + 18)
+#define GPIO_PIN_PB19 (GPIO_PIOB_BASE + 19)
+#define GPIO_PIN_PB20 (GPIO_PIOB_BASE + 20)
+#define GPIO_PIN_PB21 (GPIO_PIOB_BASE + 21)
+#define GPIO_PIN_PB22 (GPIO_PIOB_BASE + 22)
+#define GPIO_PIN_PB23 (GPIO_PIOB_BASE + 23)
+#define GPIO_PIN_PB24 (GPIO_PIOB_BASE + 24)
+#define GPIO_PIN_PB25 (GPIO_PIOB_BASE + 25)
+#define GPIO_PIN_PB26 (GPIO_PIOB_BASE + 26)
+#define GPIO_PIN_PB27 (GPIO_PIOB_BASE + 27)
+#define GPIO_PIN_PB28 (GPIO_PIOB_BASE + 28)
+#define GPIO_PIN_PB29 (GPIO_PIOB_BASE + 29)
+#define GPIO_PIN_PB30 (GPIO_PIOB_BASE + 30)
+
+#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)
+#define GPIO_PIN_PC0 (GPIO_PIOC_BASE + 0)
+#define GPIO_PIN_PC1 (GPIO_PIOC_BASE + 1)
+#define GPIO_PIN_PC2 (GPIO_PIOC_BASE + 2)
+#define GPIO_PIN_PC3 (GPIO_PIOC_BASE + 3)
+#define GPIO_PIN_PC4 (GPIO_PIOC_BASE + 4)
+#define GPIO_PIN_PC5 (GPIO_PIOC_BASE + 5)
+#define GPIO_PIN_PC6 (GPIO_PIOC_BASE + 6)
+#define GPIO_PIN_PC7 (GPIO_PIOC_BASE + 7)
+#define GPIO_PIN_PC8 (GPIO_PIOC_BASE + 8)
+#define GPIO_PIN_PC9 (GPIO_PIOC_BASE + 9)
+#define GPIO_PIN_PC10 (GPIO_PIOC_BASE + 10)
+#define GPIO_PIN_PC11 (GPIO_PIOC_BASE + 11)
+#define GPIO_PIN_PC12 (GPIO_PIOC_BASE + 12)
+#define GPIO_PIN_PC13 (GPIO_PIOC_BASE + 13)
+#define GPIO_PIN_PC14 (GPIO_PIOC_BASE + 14)
+#define GPIO_PIN_PC15 (GPIO_PIOC_BASE + 15)
+#define GPIO_PIN_PC16 (GPIO_PIOC_BASE + 16)
+#define GPIO_PIN_PC17 (GPIO_PIOC_BASE + 17)
+#define GPIO_PIN_PC18 (GPIO_PIOC_BASE + 18)
+#define GPIO_PIN_PC19 (GPIO_PIOC_BASE + 19)
+#define GPIO_PIN_PC20 (GPIO_PIOC_BASE + 20)
+#define GPIO_PIN_PC21 (GPIO_PIOC_BASE + 21)
+#define GPIO_PIN_PC22 (GPIO_PIOC_BASE + 22)
+#define GPIO_PIN_PC23 (GPIO_PIOC_BASE + 23)
+#define GPIO_PIN_PC24 (GPIO_PIOC_BASE + 24)
+#define GPIO_PIN_PC25 (GPIO_PIOC_BASE + 25)
+#define GPIO_PIN_PC26 (GPIO_PIOC_BASE + 26)
+#define GPIO_PIN_PC27 (GPIO_PIOC_BASE + 27)
+#define GPIO_PIN_PC28 (GPIO_PIOC_BASE + 28)
+#define GPIO_PIN_PC29 (GPIO_PIOC_BASE + 29)
+#define GPIO_PIN_PC30 (GPIO_PIOC_BASE + 30)
+#define GPIO_PIN_PC31 (GPIO_PIOC_BASE + 31)
+
+#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)
+#define GPIO_PIN_PD0 (GPIO_PIOD_BASE + 0)
+#define GPIO_PIN_PD1 (GPIO_PIOD_BASE + 1)
+#define GPIO_PIN_PD2 (GPIO_PIOD_BASE + 2)
+#define GPIO_PIN_PD3 (GPIO_PIOD_BASE + 3)
+#define GPIO_PIN_PD4 (GPIO_PIOD_BASE + 4)
+#define GPIO_PIN_PD5 (GPIO_PIOD_BASE + 5)
+#define GPIO_PIN_PD6 (GPIO_PIOD_BASE + 6)
+#define GPIO_PIN_PD7 (GPIO_PIOD_BASE + 7)
+#define GPIO_PIN_PD8 (GPIO_PIOD_BASE + 8)
+#define GPIO_PIN_PD9 (GPIO_PIOD_BASE + 9)
+#define GPIO_PIN_PD10 (GPIO_PIOD_BASE + 10)
+#define GPIO_PIN_PD11 (GPIO_PIOD_BASE + 11)
+#define GPIO_PIN_PD12 (GPIO_PIOD_BASE + 12)
+#define GPIO_PIN_PD13 (GPIO_PIOD_BASE + 13)
+#define GPIO_PIN_PD14 (GPIO_PIOD_BASE + 14)
+#define GPIO_PIN_PD15 (GPIO_PIOD_BASE + 15)
+#define GPIO_PIN_PD16 (GPIO_PIOD_BASE + 16)
+#define GPIO_PIN_PD17 (GPIO_PIOD_BASE + 17)
+
+#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)
+#define GPIO_PIN_PE0 (GPIO_PIOE_BASE + 0)
+#define GPIO_PIN_PE1 (GPIO_PIOE_BASE + 1)
+#define GPIO_PIN_PE2 (GPIO_PIOE_BASE + 2)
+#define GPIO_PIN_PE3 (GPIO_PIOE_BASE + 3)
+#define GPIO_PIN_PE4 (GPIO_PIOE_BASE + 4)
+#define GPIO_PIN_PE5 (GPIO_PIOE_BASE + 5)
+#define GPIO_PIN_PE6 (GPIO_PIOE_BASE + 6)
+#define GPIO_PIN_PE7 (GPIO_PIOE_BASE + 7)
+#define GPIO_PIN_PE8 (GPIO_PIOE_BASE + 8)
+#define GPIO_PIN_PE9 (GPIO_PIOE_BASE + 9)
+#define GPIO_PIN_PE10 (GPIO_PIOE_BASE + 10)
+#define GPIO_PIN_PE11 (GPIO_PIOE_BASE + 11)
+#define GPIO_PIN_PE12 (GPIO_PIOE_BASE + 12)
+#define GPIO_PIN_PE13 (GPIO_PIOE_BASE + 13)
+#define GPIO_PIN_PE14 (GPIO_PIOE_BASE + 14)
+#define GPIO_PIN_PE15 (GPIO_PIOE_BASE + 15)
+#define GPIO_PIN_PE16 (GPIO_PIOE_BASE + 16)
+#define GPIO_PIN_PE17 (GPIO_PIOE_BASE + 17)
+#define GPIO_PIN_PE18 (GPIO_PIOE_BASE + 18)
+#define GPIO_PIN_PE19 (GPIO_PIOE_BASE + 19)
+#define GPIO_PIN_PE20 (GPIO_PIOE_BASE + 20)
+#define GPIO_PIN_PE21 (GPIO_PIOE_BASE + 21)
+#define GPIO_PIN_PE22 (GPIO_PIOE_BASE + 22)
+#define GPIO_PIN_PE23 (GPIO_PIOE_BASE + 23)
+#define GPIO_PIN_PE24 (GPIO_PIOE_BASE + 24)
+#define GPIO_PIN_PE25 (GPIO_PIOE_BASE + 25)
+#define GPIO_PIN_PE26 (GPIO_PIOE_BASE + 26)
+
+static inline void *gpio_pin_to_addr(unsigned int pin)
+{
+ switch (pin >> 5) {
+ case 0:
+ return (void *)PIOA_BASE;
+ case 1:
+ return (void *)PIOB_BASE;
+ case 2:
+ return (void *)PIOC_BASE;
+ case 3:
+ return (void *)PIOD_BASE;
+ case 4:
+ return (void *)PIOE_BASE;
+ default:
+ return NULL;
+ }
+}
+
+void gpio_select_periph_A(unsigned int pin, int use_pullup);
+void gpio_select_periph_B(unsigned int pin, int use_pullup);
+
+void gpio_enable_ebi(void);
+
+#ifdef AT32AP700x_CHIP_HAS_USART
+void gpio_enable_usart0(void);
+void gpio_enable_usart1(void);
+void gpio_enable_usart2(void);
+void gpio_enable_usart3(void);
+#endif
+#ifdef AT32AP700x_CHIP_HAS_MACB
+void gpio_enable_macb0(void);
+void gpio_enable_macb1(void);
+#endif
+#ifdef AT32AP700x_CHIP_HAS_MMCI
+void gpio_enable_mmci(void);
+#endif
+
+#endif /* __ASM_AVR32_ARCH_GPIO_H__ */
diff --git a/include/asm-avr32/arch-at32ap700x/hmatrix2.h b/include/asm-avr32/arch-at32ap700x/hmatrix2.h
new file mode 100644
index 0000000..b0e787a
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap700x/hmatrix2.h
@@ -0,0 +1,232 @@
+/*
+ * Register definition for the High-speed Bus Matrix
+ */
+#ifndef __ASM_AVR32_HMATRIX2_H__
+#define __ASM_AVR32_HMATRIX2_H__
+
+/* HMATRIX2 register offsets */
+#define HMATRIX2_MCFG0 0x0000
+#define HMATRIX2_MCFG1 0x0004
+#define HMATRIX2_MCFG2 0x0008
+#define HMATRIX2_MCFG3 0x000c
+#define HMATRIX2_MCFG4 0x0010
+#define HMATRIX2_MCFG5 0x0014
+#define HMATRIX2_MCFG6 0x0018
+#define HMATRIX2_MCFG7 0x001c
+#define HMATRIX2_MCFG8 0x0020
+#define HMATRIX2_MCFG9 0x0024
+#define HMATRIX2_MCFG10 0x0028
+#define HMATRIX2_MCFG11 0x002c
+#define HMATRIX2_MCFG12 0x0030
+#define HMATRIX2_MCFG13 0x0034
+#define HMATRIX2_MCFG14 0x0038
+#define HMATRIX2_MCFG15 0x003c
+#define HMATRIX2_SCFG0 0x0040
+#define HMATRIX2_SCFG1 0x0044
+#define HMATRIX2_SCFG2 0x0048
+#define HMATRIX2_SCFG3 0x004c
+#define HMATRIX2_SCFG4 0x0050
+#define HMATRIX2_SCFG5 0x0054
+#define HMATRIX2_SCFG6 0x0058
+#define HMATRIX2_SCFG7 0x005c
+#define HMATRIX2_SCFG8 0x0060
+#define HMATRIX2_SCFG9 0x0064
+#define HMATRIX2_SCFG10 0x0068
+#define HMATRIX2_SCFG11 0x006c
+#define HMATRIX2_SCFG12 0x0070
+#define HMATRIX2_SCFG13 0x0074
+#define HMATRIX2_SCFG14 0x0078
+#define HMATRIX2_SCFG15 0x007c
+#define HMATRIX2_PRAS0 0x0080
+#define HMATRIX2_PRBS0 0x0084
+#define HMATRIX2_PRAS1 0x0088
+#define HMATRIX2_PRBS1 0x008c
+#define HMATRIX2_PRAS2 0x0090
+#define HMATRIX2_PRBS2 0x0094
+#define HMATRIX2_PRAS3 0x0098
+#define HMATRIX2_PRBS3 0x009c
+#define HMATRIX2_PRAS4 0x00a0
+#define HMATRIX2_PRBS4 0x00a4
+#define HMATRIX2_PRAS5 0x00a8
+#define HMATRIX2_PRBS5 0x00ac
+#define HMATRIX2_PRAS6 0x00b0
+#define HMATRIX2_PRBS6 0x00b4
+#define HMATRIX2_PRAS7 0x00b8
+#define HMATRIX2_PRBS7 0x00bc
+#define HMATRIX2_PRAS8 0x00c0
+#define HMATRIX2_PRBS8 0x00c4
+#define HMATRIX2_PRAS9 0x00c8
+#define HMATRIX2_PRBS9 0x00cc
+#define HMATRIX2_PRAS10 0x00d0
+#define HMATRIX2_PRBS10 0x00d4
+#define HMATRIX2_PRAS11 0x00d8
+#define HMATRIX2_PRBS11 0x00dc
+#define HMATRIX2_PRAS12 0x00e0
+#define HMATRIX2_PRBS12 0x00e4
+#define HMATRIX2_PRAS13 0x00e8
+#define HMATRIX2_PRBS13 0x00ec
+#define HMATRIX2_PRAS14 0x00f0
+#define HMATRIX2_PRBS14 0x00f4
+#define HMATRIX2_PRAS15 0x00f8
+#define HMATRIX2_PRBS15 0x00fc
+#define HMATRIX2_MRCR 0x0100
+#define HMATRIX2_SFR0 0x0110
+#define HMATRIX2_SFR1 0x0114
+#define HMATRIX2_SFR2 0x0118
+#define HMATRIX2_SFR3 0x011c
+#define HMATRIX2_SFR4 0x0120
+#define HMATRIX2_SFR5 0x0124
+#define HMATRIX2_SFR6 0x0128
+#define HMATRIX2_SFR7 0x012c
+#define HMATRIX2_SFR8 0x0130
+#define HMATRIX2_SFR9 0x0134
+#define HMATRIX2_SFR10 0x0138
+#define HMATRIX2_SFR11 0x013c
+#define HMATRIX2_SFR12 0x0140
+#define HMATRIX2_SFR13 0x0144
+#define HMATRIX2_SFR14 0x0148
+#define HMATRIX2_SFR15 0x014c
+#define HMATRIX2_VERSION 0x01fc
+
+/* Bitfields in MCFG0 */
+#define HMATRIX2_ULBT_OFFSET 0
+#define HMATRIX2_ULBT_SIZE 3
+
+/* Bitfields in SCFG0 */
+#define HMATRIX2_SLOT_CYCLE_OFFSET 0
+#define HMATRIX2_SLOT_CYCLE_SIZE 8
+#define HMATRIX2_DEFMSTR_TYPE_OFFSET 16
+#define HMATRIX2_DEFMSTR_TYPE_SIZE 2
+#define HMATRIX2_FIXED_DEFMSTR_OFFSET 18
+#define HMATRIX2_FIXED_DEFMSTR_SIZE 4
+#define HMATRIX2_ARBT_OFFSET 24
+#define HMATRIX2_ARBT_SIZE 2
+
+/* Bitfields in PRAS0 */
+#define HMATRIX2_M0PR_OFFSET 0
+#define HMATRIX2_M0PR_SIZE 4
+#define HMATRIX2_M1PR_OFFSET 4
+#define HMATRIX2_M1PR_SIZE 4
+#define HMATRIX2_M2PR_OFFSET 8
+#define HMATRIX2_M2PR_SIZE 4
+#define HMATRIX2_M3PR_OFFSET 12
+#define HMATRIX2_M3PR_SIZE 4
+#define HMATRIX2_M4PR_OFFSET 16
+#define HMATRIX2_M4PR_SIZE 4
+#define HMATRIX2_M5PR_OFFSET 20
+#define HMATRIX2_M5PR_SIZE 4
+#define HMATRIX2_M6PR_OFFSET 24
+#define HMATRIX2_M6PR_SIZE 4
+#define HMATRIX2_M7PR_OFFSET 28
+#define HMATRIX2_M7PR_SIZE 4
+
+/* Bitfields in PRBS0 */
+#define HMATRIX2_M8PR_OFFSET 0
+#define HMATRIX2_M8PR_SIZE 4
+#define HMATRIX2_M9PR_OFFSET 4
+#define HMATRIX2_M9PR_SIZE 4
+#define HMATRIX2_M10PR_OFFSET 8
+#define HMATRIX2_M10PR_SIZE 4
+#define HMATRIX2_M11PR_OFFSET 12
+#define HMATRIX2_M11PR_SIZE 4
+#define HMATRIX2_M12PR_OFFSET 16
+#define HMATRIX2_M12PR_SIZE 4
+#define HMATRIX2_M13PR_OFFSET 20
+#define HMATRIX2_M13PR_SIZE 4
+#define HMATRIX2_M14PR_OFFSET 24
+#define HMATRIX2_M14PR_SIZE 4
+#define HMATRIX2_M15PR_OFFSET 28
+#define HMATRIX2_M15PR_SIZE 4
+
+/* Bitfields in MRCR */
+#define HMATRIX2_RBC0_OFFSET 0
+#define HMATRIX2_RBC0_SIZE 1
+#define HMATRIX2_RBC1_OFFSET 1
+#define HMATRIX2_RBC1_SIZE 1
+#define HMATRIX2_RBC2_OFFSET 2
+#define HMATRIX2_RBC2_SIZE 1
+#define HMATRIX2_RBC3_OFFSET 3
+#define HMATRIX2_RBC3_SIZE 1
+#define HMATRIX2_RBC4_OFFSET 4
+#define HMATRIX2_RBC4_SIZE 1
+#define HMATRIX2_RBC5_OFFSET 5
+#define HMATRIX2_RBC5_SIZE 1
+#define HMATRIX2_RBC6_OFFSET 6
+#define HMATRIX2_RBC6_SIZE 1
+#define HMATRIX2_RBC7_OFFSET 7
+#define HMATRIX2_RBC7_SIZE 1
+#define HMATRIX2_RBC8_OFFSET 8
+#define HMATRIX2_RBC8_SIZE 1
+#define HMATRIX2_RBC9_OFFSET 9
+#define HMATRIX2_RBC9_SIZE 1
+#define HMATRIX2_RBC10_OFFSET 10
+#define HMATRIX2_RBC10_SIZE 1
+#define HMATRIX2_RBC11_OFFSET 11
+#define HMATRIX2_RBC11_SIZE 1
+#define HMATRIX2_RBC12_OFFSET 12
+#define HMATRIX2_RBC12_SIZE 1
+#define HMATRIX2_RBC13_OFFSET 13
+#define HMATRIX2_RBC13_SIZE 1
+#define HMATRIX2_RBC14_OFFSET 14
+#define HMATRIX2_RBC14_SIZE 1
+#define HMATRIX2_RBC15_OFFSET 15
+#define HMATRIX2_RBC15_SIZE 1
+
+/* Bitfields in SFR0 */
+#define HMATRIX2_SFR_OFFSET 0
+#define HMATRIX2_SFR_SIZE 32
+
+/* Bitfields in SFR4 */
+#define HMATRIX2_CS1A_OFFSET 1
+#define HMATRIX2_CS1A_SIZE 1
+#define HMATRIX2_CS3A_OFFSET 3
+#define HMATRIX2_CS3A_SIZE 1
+#define HMATRIX2_CS4A_OFFSET 4
+#define HMATRIX2_CS4A_SIZE 1
+#define HMATRIX2_CS5A_OFFSET 5
+#define HMATRIX2_CS5A_SIZE 1
+#define HMATRIX2_DBPUC_OFFSET 8
+#define HMATRIX2_DBPUC_SIZE 1
+
+/* Bitfields in VERSION */
+#define HMATRIX2_VERSION_OFFSET 0
+#define HMATRIX2_VERSION_SIZE 12
+#define HMATRIX2_MFN_OFFSET 16
+#define HMATRIX2_MFN_SIZE 3
+
+/* Constants for ULBT */
+#define HMATRIX2_ULBT_INFINITE 0
+#define HMATRIX2_ULBT_SINGLE 1
+#define HMATRIX2_ULBT_FOUR_BEAT 2
+#define HMATRIX2_ULBT_SIXTEEN_BEAT 4
+
+/* Constants for DEFMSTR_TYPE */
+#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT 0
+#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT 1
+#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT 2
+
+/* Constants for ARBT */
+#define HMATRIX2_ARBT_ROUND_ROBIN 0
+#define HMATRIX2_ARBT_FIXED_PRIORITY 1
+
+/* Bit manipulation macros */
+#define HMATRIX2_BIT(name) \
+ (1 << HMATRIX2_##name##_OFFSET)
+#define HMATRIX2_BF(name,value) \
+ (((value) & ((1 << HMATRIX2_##name##_SIZE) - 1)) \
+ << HMATRIX2_##name##_OFFSET)
+#define HMATRIX2_BFEXT(name,value) \
+ (((value) >> HMATRIX2_##name##_OFFSET) \
+ & ((1 << HMATRIX2_##name##_SIZE) - 1))
+#define HMATRIX2_BFINS(name,value,old) \
+ (((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1) \
+ << HMATRIX2_##name##_OFFSET)) \
+ | HMATRIX2_BF(name,value))
+
+/* Register access macros */
+#define hmatrix2_readl(reg) \
+ readl((void *)HMATRIX_BASE + HMATRIX2_##reg)
+#define hmatrix2_writel(reg,value) \
+ writel((value), (void *)HMATRIX_BASE + HMATRIX2_##reg)
+
+#endif /* __ASM_AVR32_HMATRIX2_H__ */
diff --git a/include/asm-avr32/arch-at32ap700x/memory-map.h b/include/asm-avr32/arch-at32ap700x/memory-map.h
new file mode 100644
index 0000000..5513e88
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap700x/memory-map.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __AT32AP7000_MEMORY_MAP_H__
+#define __AT32AP7000_MEMORY_MAP_H__
+
+/* Devices on the High Speed Bus (HSB) */
+#define LCDC_BASE 0xFF000000
+#define DMAC_BASE 0xFF200000
+#define USB_FIFO 0xFF300000
+
+/* Devices on Peripheral Bus A (PBA) */
+#define SPI0_BASE 0xFFE00000
+#define SPI1_BASE 0xFFE00400
+#define TWI_BASE 0xFFE00800
+#define USART0_BASE 0xFFE00C00
+#define USART1_BASE 0xFFE01000
+#define USART2_BASE 0xFFE01400
+#define USART3_BASE 0xFFE01800
+#define SSC0_BASE 0xFFE01C00
+#define SSC1_BASE 0xFFE02000
+#define SSC2_BASE 0xFFE02400
+#define PIOA_BASE 0xFFE02800
+#define PIOB_BASE 0xFFE02C00
+#define PIOC_BASE 0xFFE03000
+#define PIOD_BASE 0xFFE03400
+#define PIOE_BASE 0xFFE03800
+#define PSIF_BASE 0xFFE03C00
+
+/* Devices on Peripheral Bus B (PBB) */
+#define SM_BASE 0xFFF00000
+#define INTC_BASE 0xFFF00400
+#define HMATRIX_BASE 0xFFF00800
+#define TIMER0_BASE 0xFFF00C00
+#define TIMER1_BASE 0xFFF01000
+#define PWM_BASE 0xFFF01400
+#define MACB0_BASE 0xFFF01800
+#define MACB1_BASE 0xFFF01C00
+#define DAC_BASE 0xFFF02000
+#define MMCI_BASE 0xFFF02400
+#define AUDIOC_BASE 0xFFF02800
+#define HISI_BASE 0xFFF02C00
+#define USB_BASE 0xFFF03000
+#define HSMC_BASE 0xFFF03400
+#define HSDRAMC_BASE 0xFFF03800
+#define ECC_BASE 0xFFF03C00
+
+#endif /* __AT32AP7000_MEMORY_MAP_H__ */
diff --git a/include/asm-avr32/arch-at32ap700x/mmc.h b/include/asm-avr32/arch-at32ap700x/mmc.h
new file mode 100644
index 0000000..fcfbbb3
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap700x/mmc.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_MMC_H
+#define __ASM_AVR32_MMC_H
+
+struct mmc_cid {
+ unsigned long psn;
+ unsigned short oid;
+ unsigned char mid;
+ unsigned char prv;
+ unsigned char mdt;
+ char pnm[7];
+};
+
+struct mmc_csd
+{
+ u8 csd_structure:2,
+ spec_vers:4,
+ rsvd1:2;
+ u8 taac;
+ u8 nsac;
+ u8 tran_speed;
+ u16 ccc:12,
+ read_bl_len:4;
+ u64 read_bl_partial:1,
+ write_blk_misalign:1,
+ read_blk_misalign:1,
+ dsr_imp:1,
+ rsvd2:2,
+ c_size:12,
+ vdd_r_curr_min:3,
+ vdd_r_curr_max:3,
+ vdd_w_curr_min:3,
+ vdd_w_curr_max:3,
+ c_size_mult:3,
+ sector_size:5,
+ erase_grp_size:5,
+ wp_grp_size:5,
+ wp_grp_enable:1,
+ default_ecc:2,
+ r2w_factor:3,
+ write_bl_len:4,
+ write_bl_partial:1,
+ rsvd3:5;
+ u8 file_format_grp:1,
+ copy:1,
+ perm_write_protect:1,
+ tmp_write_protect:1,
+ file_format:2,
+ ecc:2;
+ u8 crc:7;
+ u8 one:1;
+};
+
+/* MMC Command numbers */
+#define MMC_CMD_GO_IDLE_STATE 0
+#define MMC_CMD_SEND_OP_COND 1
+#define MMC_CMD_ALL_SEND_CID 2
+#define MMC_CMD_SET_RELATIVE_ADDR 3
+#define MMC_CMD_SD_SEND_RELATIVE_ADDR 3
+#define MMC_CMD_SET_DSR 4
+#define MMC_CMD_SELECT_CARD 7
+#define MMC_CMD_SEND_CSD 9
+#define MMC_CMD_SEND_CID 10
+#define MMC_CMD_SEND_STATUS 13
+#define MMC_CMD_SET_BLOCKLEN 16
+#define MMC_CMD_READ_SINGLE_BLOCK 17
+#define MMC_CMD_READ_MULTIPLE_BLOCK 18
+#define MMC_CMD_WRITE_BLOCK 24
+#define MMC_CMD_APP_CMD 55
+
+#define MMC_ACMD_SD_SEND_OP_COND 41
+
+#define R1_ILLEGAL_COMMAND (1 << 22)
+#define R1_APP_CMD (1 << 5)
+
+#endif /* __ASM_AVR32_MMC_H */