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-rw-r--r--include/asm-avr32/arch-at32ap700x/addrspace.h84
-rw-r--r--include/asm-avr32/arch-at32ap700x/clk.h101
-rw-r--r--include/asm-avr32/arch-at32ap700x/gpio-impl.h86
-rw-r--r--include/asm-avr32/arch-at32ap700x/gpio.h184
-rw-r--r--include/asm-avr32/arch-at32ap700x/portmux.h89
5 files changed, 365 insertions, 179 deletions
diff --git a/include/asm-avr32/arch-at32ap700x/addrspace.h b/include/asm-avr32/arch-at32ap700x/addrspace.h
new file mode 100644
index 0000000..409eee3
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap700x/addrspace.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_ADDRSPACE_H
+#define __ASM_AVR32_ADDRSPACE_H
+
+#include <asm/types.h>
+
+/* Memory segments when segmentation is enabled */
+#define P0SEG 0x00000000
+#define P1SEG 0x80000000
+#define P2SEG 0xa0000000
+#define P3SEG 0xc0000000
+#define P4SEG 0xe0000000
+
+/* Returns the privileged segment base of a given address */
+#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000)
+
+/* Returns the physical address of a PnSEG (n=1,2) address */
+#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
+
+/*
+ * Map an address to a certain privileged segment
+ */
+#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG))
+#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG))
+#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
+#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
+
+/* virt_to_phys will only work when address is in P1 or P2 */
+static inline unsigned long virt_to_phys(volatile void *address)
+{
+ return PHYSADDR(address);
+}
+
+static inline void * phys_to_virt(unsigned long address)
+{
+ return (void *)P1SEGADDR(address);
+}
+
+#define cached(addr) ((void *)P1SEGADDR(addr))
+#define uncached(addr) ((void *)P2SEGADDR(addr))
+
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ *
+ * This implementation works for memory below 512MiB (flash, etc.) as
+ * well as above 3.5GiB (internal peripherals.)
+ */
+#define MAP_NOCACHE (0)
+#define MAP_WRCOMBINE (1 << 7)
+#define MAP_WRBACK (MAP_WRCOMBINE | (1 << 9))
+#define MAP_WRTHROUGH (MAP_WRBACK | (1 << 0))
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+ if (flags == MAP_WRBACK)
+ return (void *)P1SEGADDR(paddr);
+ else
+ return (void *)P2SEGADDR(paddr);
+}
+
+#endif /* __ASM_AVR32_ADDRSPACE_H */
diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h
index 7817572..d83e93b 100644
--- a/include/asm-avr32/arch-at32ap700x/clk.h
+++ b/include/asm-avr32/arch-at32ap700x/clk.h
@@ -23,11 +23,14 @@
#define __ASM_AVR32_ARCH_CLK_H__
#include <asm/arch/chip-features.h>
+#include <asm/arch/portmux.h>
#ifdef CONFIG_PLL
-#define MAIN_CLK_RATE ((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV) * CONFIG_SYS_PLL0_MUL)
+#define PLL0_RATE ((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV) \
+ * CONFIG_SYS_PLL0_MUL)
+#define MAIN_CLK_RATE PLL0_RATE
#else
-#define MAIN_CLK_RATE (CONFIG_SYS_OSC0_HZ)
+#define MAIN_CLK_RATE (CONFIG_SYS_OSC0_HZ)
#endif
static inline unsigned long get_cpu_clk_rate(void)
@@ -82,9 +85,101 @@ static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
#endif
extern void clk_init(void);
-extern void gclk_init(void) __attribute__((weak));
/* Board code may need the SDRAM base clock as a compile-time constant */
#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB)
+/* Generic clock control */
+enum gclk_parent {
+ GCLK_PARENT_OSC0 = 0,
+ GCLK_PARENT_OSC1 = 1,
+ GCLK_PARENT_PLL0 = 2,
+ GCLK_PARENT_PLL1 = 3,
+};
+
+/* Some generic clocks have specific roles */
+#define GCLK_DAC_SAMPLE_CLK 6
+#define GCLK_LCDC_PIXCLK 7
+
+extern unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent,
+ unsigned long rate, unsigned long parent_rate);
+
+/**
+ * gclk_set_rate - configure and enable a generic clock
+ * @id: Which GCLK[id] to enable
+ * @parent: Parent clock feeding the GCLK
+ * @rate: Target rate of the GCLK in Hz
+ *
+ * Returns the actual GCLK rate in Hz, after rounding to the nearest
+ * supported rate.
+ *
+ * All three parameters are usually constant, hence the inline.
+ */
+static inline unsigned long gclk_set_rate(unsigned int id,
+ enum gclk_parent parent, unsigned long rate)
+{
+ unsigned long parent_rate;
+
+ if (id > 7)
+ return 0;
+
+ switch (parent) {
+ case GCLK_PARENT_OSC0:
+ parent_rate = CONFIG_SYS_OSC0_HZ;
+ break;
+#ifdef CONFIG_SYS_OSC1_HZ
+ case GCLK_PARENT_OSC1:
+ parent_rate = CONFIG_SYS_OSC1_HZ;
+ break;
+#endif
+#ifdef PLL0_RATE
+ case GCLK_PARENT_PLL0:
+ parent_rate = PLL0_RATE;
+ break;
+#endif
+#ifdef PLL1_RATE
+ case GCLK_PARENT_PLL1:
+ parent_rate = PLL1_RATE;
+ break;
+#endif
+ default:
+ parent_rate = 0;
+ break;
+ }
+
+ return __gclk_set_rate(id, parent, rate, parent_rate);
+}
+
+/**
+ * gclk_enable_output - enable output on a GCLK pin
+ * @id: Which GCLK[id] pin to enable
+ * @drive_strength: Drive strength of external GCLK pin, if applicable
+ */
+static inline void gclk_enable_output(unsigned int id,
+ unsigned long drive_strength)
+{
+ switch (id) {
+ case 0:
+ portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30,
+ PORTMUX_FUNC_A, drive_strength);
+ break;
+ case 1:
+ portmux_select_peripheral(PORTMUX_PORT_A, 1 << 31,
+ PORTMUX_FUNC_A, drive_strength);
+ break;
+ case 2:
+ portmux_select_peripheral(PORTMUX_PORT_B, 1 << 19,
+ PORTMUX_FUNC_A, drive_strength);
+ break;
+ case 3:
+ portmux_select_peripheral(PORTMUX_PORT_B, 1 << 29,
+ PORTMUX_FUNC_A, drive_strength);
+ break;
+ case 4:
+ portmux_select_peripheral(PORTMUX_PORT_B, 1 << 30,
+ PORTMUX_FUNC_A, drive_strength);
+ break;
+ }
+}
+
#endif /* __ASM_AVR32_ARCH_CLK_H__ */
diff --git a/include/asm-avr32/arch-at32ap700x/gpio-impl.h b/include/asm-avr32/arch-at32ap700x/gpio-impl.h
new file mode 100644
index 0000000..8801bd0
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap700x/gpio-impl.h
@@ -0,0 +1,86 @@
+#ifndef __ASM_AVR32_ARCH_GPIO_IMPL_H__
+#define __ASM_AVR32_ARCH_GPIO_IMPL_H__
+
+/* Register offsets */
+struct gpio_regs {
+ u32 GPER;
+ u32 GPERS;
+ u32 GPERC;
+ u32 GPERT;
+ u32 PMR0;
+ u32 PMR0S;
+ u32 PMR0C;
+ u32 PMR0T;
+ u32 PMR1;
+ u32 PMR1S;
+ u32 PMR1C;
+ u32 PMR1T;
+ u32 __reserved0[4];
+ u32 ODER;
+ u32 ODERS;
+ u32 ODERC;
+ u32 ODERT;
+ u32 OVR;
+ u32 OVRS;
+ u32 OVRC;
+ u32 OVRT;
+ u32 PVR;
+ u32 __reserved_PVRS;
+ u32 __reserved_PVRC;
+ u32 __reserved_PVRT;
+ u32 PUER;
+ u32 PUERS;
+ u32 PUERC;
+ u32 PUERT;
+ u32 PDER;
+ u32 PDERS;
+ u32 PDERC;
+ u32 PDERT;
+ u32 IER;
+ u32 IERS;
+ u32 IERC;
+ u32 IERT;
+ u32 IMR0;
+ u32 IMR0S;
+ u32 IMR0C;
+ u32 IMR0T;
+ u32 IMR1;
+ u32 IMR1S;
+ u32 IMR1C;
+ u32 IMR1T;
+ u32 GFER;
+ u32 GFERS;
+ u32 GFERC;
+ u32 GFERT;
+ u32 IFR;
+ u32 __reserved_IFRS;
+ u32 IFRC;
+ u32 __reserved_IFRT;
+ u32 ODMER;
+ u32 ODMERS;
+ u32 ODMERC;
+ u32 ODMERT;
+ u32 __reserved1[4];
+ u32 ODCR0;
+ u32 ODCR0S;
+ u32 ODCR0C;
+ u32 ODCR0T;
+ u32 ODCR1;
+ u32 ODCR1S;
+ u32 ODCR1C;
+ u32 ODCR1T;
+ u32 __reserved2[4];
+ u32 OSRR0;
+ u32 OSRR0S;
+ u32 OSRR0C;
+ u32 OSRR0T;
+ u32 __reserved3[8];
+ u32 STER;
+ u32 STERS;
+ u32 STERC;
+ u32 STERT;
+ u32 __reserved4[35];
+ u32 VERSION;
+};
+
+#endif /* __ASM_AVR32_ARCH_GPIO_IMPL_H__ */
diff --git a/include/asm-avr32/arch-at32ap700x/gpio.h b/include/asm-avr32/arch-at32ap700x/gpio.h
index 8c922c7..303e353 100644
--- a/include/asm-avr32/arch-at32ap700x/gpio.h
+++ b/include/asm-avr32/arch-at32ap700x/gpio.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006 Atmel Corporation
+ * Copyright (C) 2006, 2008 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -31,161 +31,17 @@
* Pin numbers identifying specific GPIO pins on the chip.
*/
#define GPIO_PIOA_BASE (0)
-#define GPIO_PIN_PA0 (GPIO_PIOA_BASE + 0)
-#define GPIO_PIN_PA1 (GPIO_PIOA_BASE + 1)
-#define GPIO_PIN_PA2 (GPIO_PIOA_BASE + 2)
-#define GPIO_PIN_PA3 (GPIO_PIOA_BASE + 3)
-#define GPIO_PIN_PA4 (GPIO_PIOA_BASE + 4)
-#define GPIO_PIN_PA5 (GPIO_PIOA_BASE + 5)
-#define GPIO_PIN_PA6 (GPIO_PIOA_BASE + 6)
-#define GPIO_PIN_PA7 (GPIO_PIOA_BASE + 7)
-#define GPIO_PIN_PA8 (GPIO_PIOA_BASE + 8)
-#define GPIO_PIN_PA9 (GPIO_PIOA_BASE + 9)
-#define GPIO_PIN_PA10 (GPIO_PIOA_BASE + 10)
-#define GPIO_PIN_PA11 (GPIO_PIOA_BASE + 11)
-#define GPIO_PIN_PA12 (GPIO_PIOA_BASE + 12)
-#define GPIO_PIN_PA13 (GPIO_PIOA_BASE + 13)
-#define GPIO_PIN_PA14 (GPIO_PIOA_BASE + 14)
-#define GPIO_PIN_PA15 (GPIO_PIOA_BASE + 15)
-#define GPIO_PIN_PA16 (GPIO_PIOA_BASE + 16)
-#define GPIO_PIN_PA17 (GPIO_PIOA_BASE + 17)
-#define GPIO_PIN_PA18 (GPIO_PIOA_BASE + 18)
-#define GPIO_PIN_PA19 (GPIO_PIOA_BASE + 19)
-#define GPIO_PIN_PA20 (GPIO_PIOA_BASE + 20)
-#define GPIO_PIN_PA21 (GPIO_PIOA_BASE + 21)
-#define GPIO_PIN_PA22 (GPIO_PIOA_BASE + 22)
-#define GPIO_PIN_PA23 (GPIO_PIOA_BASE + 23)
-#define GPIO_PIN_PA24 (GPIO_PIOA_BASE + 24)
-#define GPIO_PIN_PA25 (GPIO_PIOA_BASE + 25)
-#define GPIO_PIN_PA26 (GPIO_PIOA_BASE + 26)
-#define GPIO_PIN_PA27 (GPIO_PIOA_BASE + 27)
-#define GPIO_PIN_PA28 (GPIO_PIOA_BASE + 28)
-#define GPIO_PIN_PA29 (GPIO_PIOA_BASE + 29)
-#define GPIO_PIN_PA30 (GPIO_PIOA_BASE + 30)
-#define GPIO_PIN_PA31 (GPIO_PIOA_BASE + 31)
-
#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
-#define GPIO_PIN_PB0 (GPIO_PIOB_BASE + 0)
-#define GPIO_PIN_PB1 (GPIO_PIOB_BASE + 1)
-#define GPIO_PIN_PB2 (GPIO_PIOB_BASE + 2)
-#define GPIO_PIN_PB3 (GPIO_PIOB_BASE + 3)
-#define GPIO_PIN_PB4 (GPIO_PIOB_BASE + 4)
-#define GPIO_PIN_PB5 (GPIO_PIOB_BASE + 5)
-#define GPIO_PIN_PB6 (GPIO_PIOB_BASE + 6)
-#define GPIO_PIN_PB7 (GPIO_PIOB_BASE + 7)
-#define GPIO_PIN_PB8 (GPIO_PIOB_BASE + 8)
-#define GPIO_PIN_PB9 (GPIO_PIOB_BASE + 9)
-#define GPIO_PIN_PB10 (GPIO_PIOB_BASE + 10)
-#define GPIO_PIN_PB11 (GPIO_PIOB_BASE + 11)
-#define GPIO_PIN_PB12 (GPIO_PIOB_BASE + 12)
-#define GPIO_PIN_PB13 (GPIO_PIOB_BASE + 13)
-#define GPIO_PIN_PB14 (GPIO_PIOB_BASE + 14)
-#define GPIO_PIN_PB15 (GPIO_PIOB_BASE + 15)
-#define GPIO_PIN_PB16 (GPIO_PIOB_BASE + 16)
-#define GPIO_PIN_PB17 (GPIO_PIOB_BASE + 17)
-#define GPIO_PIN_PB18 (GPIO_PIOB_BASE + 18)
-#define GPIO_PIN_PB19 (GPIO_PIOB_BASE + 19)
-#define GPIO_PIN_PB20 (GPIO_PIOB_BASE + 20)
-#define GPIO_PIN_PB21 (GPIO_PIOB_BASE + 21)
-#define GPIO_PIN_PB22 (GPIO_PIOB_BASE + 22)
-#define GPIO_PIN_PB23 (GPIO_PIOB_BASE + 23)
-#define GPIO_PIN_PB24 (GPIO_PIOB_BASE + 24)
-#define GPIO_PIN_PB25 (GPIO_PIOB_BASE + 25)
-#define GPIO_PIN_PB26 (GPIO_PIOB_BASE + 26)
-#define GPIO_PIN_PB27 (GPIO_PIOB_BASE + 27)
-#define GPIO_PIN_PB28 (GPIO_PIOB_BASE + 28)
-#define GPIO_PIN_PB29 (GPIO_PIOB_BASE + 29)
-#define GPIO_PIN_PB30 (GPIO_PIOB_BASE + 30)
-
#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)
-#define GPIO_PIN_PC0 (GPIO_PIOC_BASE + 0)
-#define GPIO_PIN_PC1 (GPIO_PIOC_BASE + 1)
-#define GPIO_PIN_PC2 (GPIO_PIOC_BASE + 2)
-#define GPIO_PIN_PC3 (GPIO_PIOC_BASE + 3)
-#define GPIO_PIN_PC4 (GPIO_PIOC_BASE + 4)
-#define GPIO_PIN_PC5 (GPIO_PIOC_BASE + 5)
-#define GPIO_PIN_PC6 (GPIO_PIOC_BASE + 6)
-#define GPIO_PIN_PC7 (GPIO_PIOC_BASE + 7)
-#define GPIO_PIN_PC8 (GPIO_PIOC_BASE + 8)
-#define GPIO_PIN_PC9 (GPIO_PIOC_BASE + 9)
-#define GPIO_PIN_PC10 (GPIO_PIOC_BASE + 10)
-#define GPIO_PIN_PC11 (GPIO_PIOC_BASE + 11)
-#define GPIO_PIN_PC12 (GPIO_PIOC_BASE + 12)
-#define GPIO_PIN_PC13 (GPIO_PIOC_BASE + 13)
-#define GPIO_PIN_PC14 (GPIO_PIOC_BASE + 14)
-#define GPIO_PIN_PC15 (GPIO_PIOC_BASE + 15)
-#define GPIO_PIN_PC16 (GPIO_PIOC_BASE + 16)
-#define GPIO_PIN_PC17 (GPIO_PIOC_BASE + 17)
-#define GPIO_PIN_PC18 (GPIO_PIOC_BASE + 18)
-#define GPIO_PIN_PC19 (GPIO_PIOC_BASE + 19)
-#define GPIO_PIN_PC20 (GPIO_PIOC_BASE + 20)
-#define GPIO_PIN_PC21 (GPIO_PIOC_BASE + 21)
-#define GPIO_PIN_PC22 (GPIO_PIOC_BASE + 22)
-#define GPIO_PIN_PC23 (GPIO_PIOC_BASE + 23)
-#define GPIO_PIN_PC24 (GPIO_PIOC_BASE + 24)
-#define GPIO_PIN_PC25 (GPIO_PIOC_BASE + 25)
-#define GPIO_PIN_PC26 (GPIO_PIOC_BASE + 26)
-#define GPIO_PIN_PC27 (GPIO_PIOC_BASE + 27)
-#define GPIO_PIN_PC28 (GPIO_PIOC_BASE + 28)
-#define GPIO_PIN_PC29 (GPIO_PIOC_BASE + 29)
-#define GPIO_PIN_PC30 (GPIO_PIOC_BASE + 30)
-#define GPIO_PIN_PC31 (GPIO_PIOC_BASE + 31)
-
#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)
-#define GPIO_PIN_PD0 (GPIO_PIOD_BASE + 0)
-#define GPIO_PIN_PD1 (GPIO_PIOD_BASE + 1)
-#define GPIO_PIN_PD2 (GPIO_PIOD_BASE + 2)
-#define GPIO_PIN_PD3 (GPIO_PIOD_BASE + 3)
-#define GPIO_PIN_PD4 (GPIO_PIOD_BASE + 4)
-#define GPIO_PIN_PD5 (GPIO_PIOD_BASE + 5)
-#define GPIO_PIN_PD6 (GPIO_PIOD_BASE + 6)
-#define GPIO_PIN_PD7 (GPIO_PIOD_BASE + 7)
-#define GPIO_PIN_PD8 (GPIO_PIOD_BASE + 8)
-#define GPIO_PIN_PD9 (GPIO_PIOD_BASE + 9)
-#define GPIO_PIN_PD10 (GPIO_PIOD_BASE + 10)
-#define GPIO_PIN_PD11 (GPIO_PIOD_BASE + 11)
-#define GPIO_PIN_PD12 (GPIO_PIOD_BASE + 12)
-#define GPIO_PIN_PD13 (GPIO_PIOD_BASE + 13)
-#define GPIO_PIN_PD14 (GPIO_PIOD_BASE + 14)
-#define GPIO_PIN_PD15 (GPIO_PIOD_BASE + 15)
-#define GPIO_PIN_PD16 (GPIO_PIOD_BASE + 16)
-#define GPIO_PIN_PD17 (GPIO_PIOD_BASE + 17)
-
#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)
-#define GPIO_PIN_PE0 (GPIO_PIOE_BASE + 0)
-#define GPIO_PIN_PE1 (GPIO_PIOE_BASE + 1)
-#define GPIO_PIN_PE2 (GPIO_PIOE_BASE + 2)
-#define GPIO_PIN_PE3 (GPIO_PIOE_BASE + 3)
-#define GPIO_PIN_PE4 (GPIO_PIOE_BASE + 4)
-#define GPIO_PIN_PE5 (GPIO_PIOE_BASE + 5)
-#define GPIO_PIN_PE6 (GPIO_PIOE_BASE + 6)
-#define GPIO_PIN_PE7 (GPIO_PIOE_BASE + 7)
-#define GPIO_PIN_PE8 (GPIO_PIOE_BASE + 8)
-#define GPIO_PIN_PE9 (GPIO_PIOE_BASE + 9)
-#define GPIO_PIN_PE10 (GPIO_PIOE_BASE + 10)
-#define GPIO_PIN_PE11 (GPIO_PIOE_BASE + 11)
-#define GPIO_PIN_PE12 (GPIO_PIOE_BASE + 12)
-#define GPIO_PIN_PE13 (GPIO_PIOE_BASE + 13)
-#define GPIO_PIN_PE14 (GPIO_PIOE_BASE + 14)
-#define GPIO_PIN_PE15 (GPIO_PIOE_BASE + 15)
-#define GPIO_PIN_PE16 (GPIO_PIOE_BASE + 16)
-#define GPIO_PIN_PE17 (GPIO_PIOE_BASE + 17)
-#define GPIO_PIN_PE18 (GPIO_PIOE_BASE + 18)
-#define GPIO_PIN_PE19 (GPIO_PIOE_BASE + 19)
-#define GPIO_PIN_PE20 (GPIO_PIOE_BASE + 20)
-#define GPIO_PIN_PE21 (GPIO_PIOE_BASE + 21)
-#define GPIO_PIN_PE22 (GPIO_PIOE_BASE + 22)
-#define GPIO_PIN_PE23 (GPIO_PIOE_BASE + 23)
-#define GPIO_PIN_PE24 (GPIO_PIOE_BASE + 24)
-#define GPIO_PIN_PE25 (GPIO_PIOE_BASE + 25)
-#define GPIO_PIN_PE26 (GPIO_PIOE_BASE + 26)
+#define GPIO_PIN_PA(x) (GPIO_PIOA_BASE + (x))
+#define GPIO_PIN_PB(x) (GPIO_PIOB_BASE + (x))
+#define GPIO_PIN_PC(x) (GPIO_PIOC_BASE + (x))
+#define GPIO_PIN_PD(x) (GPIO_PIOD_BASE + (x))
+#define GPIO_PIN_PE(x) (GPIO_PIOE_BASE + (x))
-#define GPIOF_PULLUP 0x00000001 /* (not-OUT) Enable pull-up */
-#define GPIOF_OUTPUT 0x00000002 /* (OUT) Enable output driver */
-#define GPIOF_DEGLITCH 0x00000004 /* (IN) Filter glitches */
-#define GPIOF_MULTIDRV 0x00000008 /* Enable multidriver option */
-
-static inline void *gpio_pin_to_addr(unsigned int pin)
+static inline void *pio_pin_to_port(unsigned int pin)
{
switch (pin >> 5) {
case 0:
@@ -203,30 +59,6 @@ static inline void *gpio_pin_to_addr(unsigned int pin)
}
}
-void gpio_select_periph_A(unsigned int pin, int use_pullup);
-void gpio_select_periph_B(unsigned int pin, int use_pullup);
-void gpio_select_pio(unsigned int pin, unsigned long gpiof_flags);
-void gpio_set_value(unsigned int pin, int value);
-int gpio_get_value(unsigned int pin);
-
-void gpio_enable_ebi(void);
-
-#ifdef AT32AP700x_CHIP_HAS_USART
-void gpio_enable_usart0(void);
-void gpio_enable_usart1(void);
-void gpio_enable_usart2(void);
-void gpio_enable_usart3(void);
-#endif
-#ifdef AT32AP700x_CHIP_HAS_MACB
-void gpio_enable_macb0(void);
-void gpio_enable_macb1(void);
-#endif
-#ifdef AT32AP700x_CHIP_HAS_MMCI
-void gpio_enable_mmci(void);
-#endif
-#ifdef AT32AP700x_CHIP_HAS_SPI
-void gpio_enable_spi0(unsigned long cs_mask);
-void gpio_enable_spi1(unsigned long cs_mask);
-#endif
+#include <asm/arch-common/portmux-pio.h>
#endif /* __ASM_AVR32_ARCH_GPIO_H__ */
diff --git a/include/asm-avr32/arch-at32ap700x/portmux.h b/include/asm-avr32/arch-at32ap700x/portmux.h
new file mode 100644
index 0000000..96fe70d
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap700x/portmux.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2006, 2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_ARCH_PORTMUX_H__
+#define __ASM_AVR32_ARCH_PORTMUX_H__
+
+#include <asm/arch/gpio.h>
+
+#define PORTMUX_PORT_A ((void *)PIOA_BASE)
+#define PORTMUX_PORT_B ((void *)PIOB_BASE)
+#define PORTMUX_PORT_C ((void *)PIOC_BASE)
+#define PORTMUX_PORT_D ((void *)PIOD_BASE)
+#define PORTMUX_PORT_E ((void *)PIOE_BASE)
+
+void portmux_enable_ebi(unsigned int bus_width, unsigned int addr_width,
+ unsigned long flags, unsigned long drive_strength);
+
+#define PORTMUX_EBI_CS(x) (1 << (x))
+#define PORTMUX_EBI_NAND (1 << 6)
+#define PORTMUX_EBI_CF(x) (1 << ((x) + 7))
+#define PORTMUX_EBI_NWAIT (1 << 9)
+
+#ifdef AT32AP700x_CHIP_HAS_USART
+static inline void portmux_enable_usart0(unsigned long drive_strength)
+{
+ portmux_select_peripheral(PORTMUX_PORT_A, (1 << 8) | (1 << 9),
+ PORTMUX_FUNC_B, 0);
+}
+
+static inline void portmux_enable_usart1(unsigned long drive_strength)
+{
+ portmux_select_peripheral(PORTMUX_PORT_A, (1 << 17) | (1 << 18),
+ PORTMUX_FUNC_A, 0);
+}
+
+static inline void portmux_enable_usart2(unsigned long drive_strength)
+{
+ portmux_select_peripheral(PORTMUX_PORT_B, (1 << 26) | (1 << 27),
+ PORTMUX_FUNC_B, 0);
+}
+
+static inline void portmux_enable_usart3(unsigned long drive_strength)
+{
+ portmux_select_peripheral(PORTMUX_PORT_B, (1 << 17) | (1 << 18),
+ PORTMUX_FUNC_B, 0);
+}
+#endif
+#ifdef AT32AP700x_CHIP_HAS_MACB
+void portmux_enable_macb0(unsigned long flags, unsigned long drive_strength);
+void portmux_enable_macb1(unsigned long flags, unsigned long drive_strength);
+
+#define PORTMUX_MACB_RMII (0)
+#define PORTMUX_MACB_MII (1 << 0)
+#define PORTMUX_MACB_SPEED (1 << 1)
+
+#endif
+#ifdef AT32AP700x_CHIP_HAS_MMCI
+void portmux_enable_mmci(unsigned int slot, unsigned long flags,
+ unsigned long drive_strength);
+
+#define PORTMUX_MMCI_4BIT (1 << 0)
+#define PORTMUX_MMCI_8BIT (PORTMUX_MMCI_4BIT | (1 << 1))
+#define PORTMUX_MMCI_EXT_PULLUP (1 << 2)
+
+#endif
+#ifdef AT32AP700x_CHIP_HAS_SPI
+void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength);
+void portmux_enable_spi1(unsigned long cs_mask, unsigned long drive_strength);
+#endif
+
+#endif /* __ASM_AVR32_ARCH_PORTMUX_H__ */