diff options
Diffstat (limited to 'include/asm-arm')
| -rw-r--r-- | include/asm-arm/arch-mx6/mx6_pins.h | 58 | ||||
| -rw-r--r-- | include/asm-arm/mach-types.h | 15 |
2 files changed, 26 insertions, 47 deletions
diff --git a/include/asm-arm/arch-mx6/mx6_pins.h b/include/asm-arm/arch-mx6/mx6_pins.h index 539231b..9648aa9 100644 --- a/include/asm-arm/arch-mx6/mx6_pins.h +++ b/include/asm-arm/arch-mx6/mx6_pins.h @@ -36,9 +36,9 @@ typedef enum iomux_config { IOMUX_CONFIG_ALT5, IOMUX_CONFIG_ALT6, IOMUX_CONFIG_ALT7, - IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ - IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ - } iomux_pin_cfg_t; + IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ +} iomux_pin_cfg_t; #define NON_MUX_I 0x3FF #define NON_PAD_I 0x7FF @@ -47,6 +47,9 @@ typedef enum iomux_config { PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define MX6Q_ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + #define MX6Q_USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) @@ -3651,8 +3654,6 @@ typedef enum iomux_config { #define _MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 \ IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0) - - #define MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 (_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL)) #define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 (_MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 (_MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -3679,7 +3680,6 @@ typedef enum iomux_config { #define MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT (_MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 (_MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) - #define MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA (_MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC (_MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) #define MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK (_MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -3687,7 +3687,6 @@ typedef enum iomux_config { #define MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 (_MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT (_MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) - #define MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY (_MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 (_MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) #define MX6Q_PAD_RGMII_TD0__GPIO_6_20 (_MX6Q_PAD_RGMII_TD0__GPIO_6_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -3699,32 +3698,27 @@ typedef enum iomux_config { #define MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 (_MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP (_MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) - #define MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA (_MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 (_MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) #define MX6Q_PAD_RGMII_TD2__GPIO_6_22 (_MX6Q_PAD_RGMII_TD2__GPIO_6_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 (_MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP (_MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) - #define MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE (_MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 (_MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) #define MX6Q_PAD_RGMII_TD3__GPIO_6_23 (_MX6Q_PAD_RGMII_TD3__GPIO_6_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 (_MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) - #define MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA (_MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL (_MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) #define MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 (_MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 (_MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) - #define MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY (_MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 (_MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) #define MX6Q_PAD_RGMII_RD0__GPIO_6_25 (_MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 (_MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) - #define MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE (_MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL (_MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) #define MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 (_MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -3771,7 +3765,7 @@ typedef enum iomux_config { #define MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 (_MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 (_MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D16__ECSPI1_SCLK (_MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D16__ECSPI1_SCLK (_MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL)) #define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 (_MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 (_MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA (_MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -3779,7 +3773,7 @@ typedef enum iomux_config { #define MX6Q_PAD_EIM_D16__I2C2_SDA (_MX6Q_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) #define MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 (_MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D17__ECSPI1_MISO (_MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D17__ECSPI1_MISO (_MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL)) #define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 (_MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK (_MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT (_MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -3788,7 +3782,7 @@ typedef enum iomux_config { #define MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 (_MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 (_MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D18__ECSPI1_MOSI (_MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D18__ECSPI1_MOSI (_MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL)) #define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 (_MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 (_MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS (_MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -3797,7 +3791,7 @@ typedef enum iomux_config { #define MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 (_MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 (_MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_EIM_D19__ECSPI1_SS1 (_MX6Q_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_EIM_D19__ECSPI1_SS1 (_MX6Q_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL)) #define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 (_MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 (_MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D19__UART1_CTS (_MX6Q_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL)) @@ -4460,7 +4454,7 @@ typedef enum iomux_config { #define MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 (_MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED (_MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_MDIO__ENET_MDIO (_MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_MDIO__ENET_MDIO (_MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) #define MX6Q_PAD_ENET_MDIO__ESAI1_SCKR (_MX6Q_PAD_ENET_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 (_MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT (_MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -4530,7 +4524,7 @@ typedef enum iomux_config { #define MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD (_MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_ENET_MDC__MLB_MLBDAT (_MX6Q_PAD_ENET_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL)) -#define MX6Q_PAD_ENET_MDC__ENET_MDC (_MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(NO_PAD_CTRL)) +#define MX6Q_PAD_ENET_MDC__ENET_MDC (_MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) #define MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 (_MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN (_MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_ENET_MDC__GPIO_1_31 (_MX6Q_PAD_ENET_MDC__GPIO_1_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -5619,31 +5613,3 @@ typedef enum iomux_config { #define MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 (_MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) #endif - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index 4255c07..8d8e14c 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -3254,7 +3254,8 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_SWEDA_TMS2 3272 #define MACH_TYPE_MX53_LOCO 3273 #define MACH_TYPE_MX53_PCBA 3274 -#define MACH_TYPE_MX6Q_SABREAUTO 3529 +#define MACH_TYPE_MX6Q_SABREAUTO 3529 +#define MACH_TYPE_MX6Q_SABRELITE 3769 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -42160,6 +42161,18 @@ extern unsigned int __machine_arch_type; # define machine_is_mx6q_sabreauto() (0) #endif +#ifdef CONFIG_MACH_MX6Q_SABRELITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX6Q_SABRELITE +# endif +# define machine_is_mx6q_sabrelite() (machine_arch_type == MACH_TYPE_MX6Q_SABRELITE) +#else +# define machine_is_mx6q_sabrelite() (0) +#endif + /* * These have not yet been registered */ |