diff options
Diffstat (limited to 'include/asm-arm')
| -rw-r--r-- | include/asm-arm/apbh_dma.h | 79 | ||||
| -rw-r--r-- | include/asm-arm/arch-mx28/mx28.h | 4 |
2 files changed, 83 insertions, 0 deletions
diff --git a/include/asm-arm/apbh_dma.h b/include/asm-arm/apbh_dma.h index 5bb1f40..213f9f4 100644 --- a/include/asm-arm/apbh_dma.h +++ b/include/asm-arm/apbh_dma.h @@ -47,6 +47,22 @@ #define BM_APBH_CTRL0_CLKGATE_CHANNEL 0x0000FFFF #define BF_APBH_CTRL0_CLKGATE_CHANNEL(v) \ (((v) << 0) & BM_APBH_CTRL0_CLKGATE_CHANNEL) +#if defined(CONFIG_APBH_DMA_V1) +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP0 0x0001 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP1 0x0002 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP2 0x0004 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP3 0x0008 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0 0x0010 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1 0x0020 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2 0x0040 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3 0x0080 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND4 0x0100 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND5 0x0200 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND6 0x0400 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND7 0x0800 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__HSADC 0x1000 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__LCDIF 0x2000 +#elif defined(CONFIG_APBH_DMA_V2) #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0 0x0001 #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1 0x0002 #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2 0x0004 @@ -56,6 +72,7 @@ #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND6 0x0040 #define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND7 0x0080 #define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP 0x0100 +#endif #define HW_APBH_CTRL1 (0x00000010) #define HW_APBH_CTRL1_SET (0x00000014) @@ -174,6 +191,43 @@ #define BM_APBH_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000 #define BF_APBH_CHANNEL_CTRL_RESET_CHANNEL(v) \ (((v) << 16) & BM_APBH_CHANNEL_CTRL_RESET_CHANNEL) + +#if defined(CONFIG_APBH_DMA_V1) +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP0 0x0001 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP1 0x0002 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP2 0x0004 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__SSP3 0x0008 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND0 0x0010 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND1 0x0020 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND2 0x0040 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND3 0x0080 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND4 0x0100 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND5 0x0200 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND6 0x0400 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND7 0x0800 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__HSADC 0x1000 +#define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__LCDIF 0x2000 + +#define BP_APBH_CHANNEL_CTRL_FREEZE_CHANNEL 0 +#define BM_APBH_CHANNEL_CTRL_FREEZE_CHANNEL 0x0000FFFF +#define BF_APBH_CHANNEL_CTRL_FREEZE_CHANNEL(v) \ + (((v) << 0) & BM_APBH_CHANNEL_CTRL_FREEZE_CHANNEL) + +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP0 0x0001 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP1 0x0002 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP2 0x0004 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP3 0x0008 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND0 0x0010 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND1 0x0020 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND2 0x0040 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND3 0x0080 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND4 0x0100 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND5 0x0200 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND6 0x0400 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND7 0x0800 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__HSADC 0x1000 +#define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__LCDIF 0x2000 +#elif defined(CONFIG_APBH_DMA_V2) #define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND0 0x0001 #define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND1 0x0002 #define BV_APBH_CHANNEL_CTRL_RESET_CHANNEL__NAND2 0x0004 @@ -196,6 +250,7 @@ #define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND6 0x0040 #define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__NAND7 0x0080 #define BV_APBH_CHANNEL_CTRL_FREEZE_CHANNEL__SSP 0x0100 +#endif #define HW_APBH_DEVSEL (0x00000040) @@ -321,18 +376,32 @@ #define BM_APBH_DMA_BURST_SIZE_CH3 0x000000C0 #define BF_APBH_DMA_BURST_SIZE_CH3(v) \ (((v) << 6) & BM_APBH_DMA_BURST_SIZE_CH3) +#define BV_APBH_DMA_BURST_SIZE_CH3__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH3__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH3__BURST8 0x2 + #define BP_APBH_DMA_BURST_SIZE_CH2 4 #define BM_APBH_DMA_BURST_SIZE_CH2 0x00000030 #define BF_APBH_DMA_BURST_SIZE_CH2(v) \ (((v) << 4) & BM_APBH_DMA_BURST_SIZE_CH2) +#define BV_APBH_DMA_BURST_SIZE_CH2__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH2__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH2__BURST8 0x2 #define BP_APBH_DMA_BURST_SIZE_CH1 2 #define BM_APBH_DMA_BURST_SIZE_CH1 0x0000000C #define BF_APBH_DMA_BURST_SIZE_CH1(v) \ (((v) << 2) & BM_APBH_DMA_BURST_SIZE_CH1) +#define BV_APBH_DMA_BURST_SIZE_CH1__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH1__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH1__BURST8 0x2 + #define BP_APBH_DMA_BURST_SIZE_CH0 0 #define BM_APBH_DMA_BURST_SIZE_CH0 0x00000003 #define BF_APBH_DMA_BURST_SIZE_CH0(v) \ (((v) << 0) & BM_APBH_DMA_BURST_SIZE_CH0) +#define BV_APBH_DMA_BURST_SIZE_CH0__BURST0 0x0 +#define BV_APBH_DMA_BURST_SIZE_CH0__BURST4 0x1 +#define BV_APBH_DMA_BURST_SIZE_CH0__BURST8 0x2 #define HW_APBH_DEBUG (0x00000060) @@ -515,7 +584,17 @@ enum { MXS_DMA_CHANNEL_AHB_APBH = 0, +#if defined(CONFIG_APBH_DMA_V1) + MXS_DMA_CHANNEL_AHB_APBH_SSP0 = MXS_DMA_CHANNEL_AHB_APBH, + MXS_DMA_CHANNEL_AHB_APBH_SSP1, + MXS_DMA_CHANNEL_AHB_APBH_SSP2, + MXS_DMA_CHANNEL_AHB_APBH_SSP3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI0, +#elif defined(CONFIG_APBH_DMA_V2) MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = MXS_DMA_CHANNEL_AHB_APBH, +#else +# error "Undefined apbh dma version!" +#endif MXS_DMA_CHANNEL_AHB_APBH_GPMI1, MXS_DMA_CHANNEL_AHB_APBH_GPMI2, MXS_DMA_CHANNEL_AHB_APBH_GPMI3, diff --git a/include/asm-arm/arch-mx28/mx28.h b/include/asm-arm/arch-mx28/mx28.h index fc671ae..a21a3cc 100644 --- a/include/asm-arm/arch-mx28/mx28.h +++ b/include/asm-arm/arch-mx28/mx28.h @@ -25,6 +25,7 @@ enum mxc_clock { MXC_ARM_CLK = 0, MXC_AHB_CLK, MXC_IPG_CLK, + MXC_GPMI_CLK, }; unsigned int mxc_get_clock(enum mxc_clock clk); @@ -116,4 +117,7 @@ void enet_board_init(void); #define REGS_DRAM_BASE (0x800E0000) #define REGS_ENET_BASE (0x800F0000) +#define BCH_BASE_ADDR REGS_BCH_BASE +#define GPMI_BASE_ADDR REGS_GPMI_BASE +#define ABPHDMA_BASE_ADDR REGS_APBH_BASE #endif /* __MX28_H */ |