diff options
Diffstat (limited to 'include/asm-arm')
| -rw-r--r-- | include/asm-arm/arch-arm720t/netarm_mem_module.h | 18 | ||||
| -rw-r--r-- | include/asm-arm/arch-arm720t/netarm_ser_module.h | 32 | ||||
| -rw-r--r-- | include/asm-arm/arch-arm720t/s3c4510b.h | 10 | ||||
| -rw-r--r-- | include/asm-arm/arch-at91rm9200/AT91RM9200.h | 382 | ||||
| -rw-r--r-- | include/asm-arm/arch-at91sam9/gpio.h | 4 | ||||
| -rw-r--r-- | include/asm-arm/arch-ixp/ixp425.h | 76 | ||||
| -rw-r--r-- | include/asm-arm/arch-omap24xx/clocks.h | 12 | ||||
| -rw-r--r-- | include/asm-arm/arch-pxa/bitfield.h | 44 | ||||
| -rw-r--r-- | include/asm-arm/arch-pxa/mmc.h | 107 | ||||
| -rw-r--r-- | include/asm-arm/arch-s3c24x0/memory.h | 8 | ||||
| -rw-r--r-- | include/asm-arm/arch-sa1100/bitfield.h | 44 | ||||
| -rw-r--r-- | include/asm-arm/u-boot.h | 2 |
12 files changed, 369 insertions, 370 deletions
diff --git a/include/asm-arm/arch-arm720t/netarm_mem_module.h b/include/asm-arm/arch-arm720t/netarm_mem_module.h index f0529fd..c650c3b 100644 --- a/include/asm-arm/arch-arm720t/netarm_mem_module.h +++ b/include/asm-arm/arch-arm720t/netarm_mem_module.h @@ -170,15 +170,15 @@ /* Option B Registers (0xFFC0_00x8) */ #define NETARM_MEM_OPTB_SYNC_1_STAGE (0x00000001) #define NETARM_MEM_OPTB_SYNC_2_STAGE (0x00000002) -#define NETARM_MEM_OPTB_BCYC_PLUS0 (0x00000000) -#define NETARM_MEM_OPTB_BCYC_PLUS4 (0x00000004) -#define NETARM_MEM_OPTB_BCYC_PLUS8 (0x00000008) -#define NETARM_MEM_OPTB_BCYC_PLUS12 (0x0000000C) - -#define NETARM_MEM_OPTB_WAIT_PLUS0 (0x00000000) -#define NETARM_MEM_OPTB_WAIT_PLUS16 (0x00000010) -#define NETARM_MEM_OPTB_WAIT_PLUS32 (0x00000020) -#define NETARM_MEM_OPTB_WAIT_PLUS48 (0x00000030) +#define NETARM_MEM_OPTB_BCYC_PLUS0 (0x00000000) +#define NETARM_MEM_OPTB_BCYC_PLUS4 (0x00000004) +#define NETARM_MEM_OPTB_BCYC_PLUS8 (0x00000008) +#define NETARM_MEM_OPTB_BCYC_PLUS12 (0x0000000C) + +#define NETARM_MEM_OPTB_WAIT_PLUS0 (0x00000000) +#define NETARM_MEM_OPTB_WAIT_PLUS16 (0x00000010) +#define NETARM_MEM_OPTB_WAIT_PLUS32 (0x00000020) +#define NETARM_MEM_OPTB_WAIT_PLUS48 (0x00000030) #endif #endif diff --git a/include/asm-arm/arch-arm720t/netarm_ser_module.h b/include/asm-arm/arch-arm720t/netarm_ser_module.h index fceabd1..6fbae11 100644 --- a/include/asm-arm/arch-arm720t/netarm_ser_module.h +++ b/include/asm-arm/arch-arm720t/netarm_ser_module.h @@ -284,21 +284,21 @@ typedef struct { /* from section 7.5.4 of HW Ref Guide */ /* #ifdef CONFIG_NETARM_PLL_BYPASS */ -#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ - NETARM_SER_BR_RX_CLK_INT | \ - NETARM_SER_BR_TX_CLK_INT | \ - NETARM_SER_BR_CLK_EXT_5 | \ - ( ( ( ( NETARM_XTAL_FREQ / \ - ( x * 10 ) ) - 1 ) / 16 ) & \ +#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ + NETARM_SER_BR_RX_CLK_INT | \ + NETARM_SER_BR_TX_CLK_INT | \ + NETARM_SER_BR_CLK_EXT_5 | \ + ( ( ( ( NETARM_XTAL_FREQ / \ + ( x * 10 ) ) - 1 ) / 16 ) & \ NETARM_SER_BR_MASK ) ) /* #else -#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ - NETARM_SER_BR_RX_CLK_INT | \ - NETARM_SER_BR_TX_CLK_INT | \ - NETARM_SER_BR_CLK_SYSTEM | \ - ( ( ( ( NETARM_PLLED_SYSCLK_FREQ / \ - ( x * 2 ) ) - 1 ) / 16 ) & \ +#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ + NETARM_SER_BR_RX_CLK_INT | \ + NETARM_SER_BR_TX_CLK_INT | \ + NETARM_SER_BR_CLK_SYSTEM | \ + ( ( ( ( NETARM_PLLED_SYSCLK_FREQ / \ + ( x * 2 ) ) - 1 ) / 16 ) & \ NETARM_SER_BR_MASK ) ) #endif */ @@ -313,13 +313,13 @@ typedef struct { /* #ifdef CONFIG_NETARM_PLL_BYPASS */ #define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ ( ( ( ( 10 * NETARM_XTAL_FREQ ) / \ - ( x * 5 * 512 ) ) - 1 ) & \ + ( x * 5 * 512 ) ) - 1 ) & \ NETARM_SER_RX_GAP_MASK ) ) /* #else #define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \ - ( x * 512 ) ) - 1 ) & \ + ( x * 512 ) ) - 1 ) & \ NETARM_SER_RX_GAP_MASK ) ) #endif */ @@ -327,11 +327,11 @@ typedef struct { #if 0 #define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \ - ( x * 5 * 512 ) ) - 1 ) & \ + ( x * 5 * 512 ) ) - 1 ) & \ NETARM_SER_RX_GAP_MASK ) ) #define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ ( ( ( ( 10 * NETARM_XTAL_FREQ ) / \ - ( x * 512 ) ) - 1 ) & \ + ( x * 512 ) ) - 1 ) & \ NETARM_SER_RX_GAP_MASK ) ) #endif diff --git a/include/asm-arm/arch-arm720t/s3c4510b.h b/include/asm-arm/arch-arm720t/s3c4510b.h index 73a3b6d..6b8c8ed 100644 --- a/include/asm-arm/arch-arm720t/s3c4510b.h +++ b/include/asm-arm/arch-arm720t/s3c4510b.h @@ -35,7 +35,7 @@ /* Special Register Start Address After System Reset */ #define REG_BASE (0x03ff0000) -#define SPSTR (REG_BASE) +#define SPSTR (REG_BASE) /* *********************** */ /* System Manager Register */ @@ -100,7 +100,7 @@ #define REG_I2C_CON (REG_BASE+0xf000) #define REG_I2C_BUF (REG_BASE+0xf004) #define REG_I2C_PS (REG_BASE+0xf008) -#define REG_I2C_COUNT (REG_BASE+0xf00c) +#define REG_I2C_COUNT (REG_BASE+0xf00c) /********************/ /* GDMA 0 */ @@ -149,7 +149,7 @@ /********************/ /* Timer Register */ /********************/ -#define REG_TMOD (REG_BASE+0x6000) +#define REG_TMOD (REG_BASE+0x6000) #define REG_TDATA0 (REG_BASE+0x6004) #define REG_TDATA1 (REG_BASE+0x6008) #define REG_TCNT0 (REG_BASE+0x600c) @@ -159,8 +159,8 @@ /* I/O Port Interface */ /**********************/ #define REG_IOPMODE (REG_BASE+0x5000) -#define REG_IOPCON (REG_BASE+0x5004) -#define REG_IOPDATA (REG_BASE+0x5008) +#define REG_IOPCON (REG_BASE+0x5004) +#define REG_IOPDATA (REG_BASE+0x5008) /*********************************/ /* Interrupt Controller Register */ diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h index 0e01005..2f7f710 100644 --- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h +++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h @@ -32,17 +32,17 @@ typedef volatile unsigned int AT91_REG; /* Hardware register definition */ /*****************************************************************************/ typedef struct _AT91S_TC { - AT91_REG TC_CCR; /* Channel Control Register */ - AT91_REG TC_CMR; /* Channel Mode Register */ - AT91_REG Reserved0[2]; /* */ - AT91_REG TC_CV; /* Counter Value */ - AT91_REG TC_RA; /* Register A */ - AT91_REG TC_RB; /* Register B */ - AT91_REG TC_RC; /* Register C */ - AT91_REG TC_SR; /* Status Register */ - AT91_REG TC_IER; /* Interrupt Enable Register */ - AT91_REG TC_IDR; /* Interrupt Disable Register */ - AT91_REG TC_IMR; /* Interrupt Mask Register */ + AT91_REG TC_CCR; /* Channel Control Register */ + AT91_REG TC_CMR; /* Channel Mode Register */ + AT91_REG Reserved0[2]; /* */ + AT91_REG TC_CV; /* Counter Value */ + AT91_REG TC_RA; /* Register A */ + AT91_REG TC_RB; /* Register B */ + AT91_REG TC_RC; /* Register C */ + AT91_REG TC_SR; /* Status Register */ + AT91_REG TC_IER; /* Interrupt Enable Register */ + AT91_REG TC_IDR; /* Interrupt Disable Register */ + AT91_REG TC_IMR; /* Interrupt Mask Register */ } AT91S_TC, *AT91PS_TC; #define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */ @@ -65,33 +65,33 @@ typedef struct _AT91S_TC /*****************************************************************************/ typedef struct _AT91S_USART { - AT91_REG US_CR; /* Control Register */ - AT91_REG US_MR; /* Mode Register */ - AT91_REG US_IER; /* Interrupt Enable Register */ - AT91_REG US_IDR; /* Interrupt Disable Register */ - AT91_REG US_IMR; /* Interrupt Mask Register */ - AT91_REG US_CSR; /* Channel Status Register */ - AT91_REG US_RHR; /* Receiver Holding Register */ - AT91_REG US_THR; /* Transmitter Holding Register */ - AT91_REG US_BRGR; /* Baud Rate Generator Register */ - AT91_REG US_RTOR; /* Receiver Time-out Register */ - AT91_REG US_TTGR; /* Transmitter Time-guard Register */ - AT91_REG Reserved0[5]; /* */ - AT91_REG US_FIDI; /* FI_DI_Ratio Register */ - AT91_REG US_NER; /* Nb Errors Register */ - AT91_REG US_XXR; /* XON_XOFF Register */ - AT91_REG US_IF; /* IRDA_FILTER Register */ + AT91_REG US_CR; /* Control Register */ + AT91_REG US_MR; /* Mode Register */ + AT91_REG US_IER; /* Interrupt Enable Register */ + AT91_REG US_IDR; /* Interrupt Disable Register */ + AT91_REG US_IMR; /* Interrupt Mask Register */ + AT91_REG US_CSR; /* Channel Status Register */ + AT91_REG US_RHR; /* Receiver Holding Register */ + AT91_REG US_THR; /* Transmitter Holding Register */ + AT91_REG US_BRGR; /* Baud Rate Generator Register */ + AT91_REG US_RTOR; /* Receiver Time-out Register */ + AT91_REG US_TTGR; /* Transmitter Time-guard Register */ + AT91_REG Reserved0[5]; /* */ + AT91_REG US_FIDI; /* FI_DI_Ratio Register */ + AT91_REG US_NER; /* Nb Errors Register */ + AT91_REG US_XXR; /* XON_XOFF Register */ + AT91_REG US_IF; /* IRDA_FILTER Register */ AT91_REG Reserved1[44]; /* */ - AT91_REG US_RPR; /* Receive Pointer Register */ - AT91_REG US_RCR; /* Receive Counter Register */ - AT91_REG US_TPR; /* Transmit Pointer Register */ - AT91_REG US_TCR; /* Transmit Counter Register */ - AT91_REG US_RNPR; /* Receive Next Pointer Register */ - AT91_REG US_RNCR; /* Receive Next Counter Register */ - AT91_REG US_TNPR; /* Transmit Next Pointer Register */ - AT91_REG US_TNCR; /* Transmit Next Counter Register */ - AT91_REG US_PTCR; /* PDC Transfer Control Register */ - AT91_REG US_PTSR; /* PDC Transfer Status Register */ + AT91_REG US_RPR; /* Receive Pointer Register */ + AT91_REG US_RCR; /* Receive Counter Register */ + AT91_REG US_TPR; /* Transmit Pointer Register */ + AT91_REG US_TCR; /* Transmit Counter Register */ + AT91_REG US_RNPR; /* Receive Next Pointer Register */ + AT91_REG US_RNCR; /* Receive Next Counter Register */ + AT91_REG US_TNPR; /* Transmit Next Pointer Register */ + AT91_REG US_TNCR; /* Transmit Next Counter Register */ + AT91_REG US_PTCR; /* PDC Transfer Control Register */ + AT91_REG US_PTSR; /* PDC Transfer Status Register */ } AT91S_USART, *AT91PS_USART; /*****************************************************************************/ @@ -99,10 +99,10 @@ typedef struct _AT91S_USART /*****************************************************************************/ typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; /* Main Oscillator Register */ - AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ - AT91_REG CKGR_PLLAR; /* PLL A Register */ - AT91_REG CKGR_PLLBR; /* PLL B Register */ + AT91_REG CKGR_MOR; /* Main Oscillator Register */ + AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ + AT91_REG CKGR_PLLAR; /* PLL A Register */ + AT91_REG CKGR_PLLBR; /* PLL B Register */ } AT91S_CKGR, *AT91PS_CKGR; /* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ @@ -146,41 +146,41 @@ typedef struct _AT91S_CKGR /*****************************************************************************/ typedef struct _AT91S_PIO { - AT91_REG PIO_PER; /* PIO Enable Register */ - AT91_REG PIO_PDR; /* PIO Disable Register */ - AT91_REG PIO_PSR; /* PIO Status Register */ - AT91_REG Reserved0[1]; /* */ - AT91_REG PIO_OER; /* Output Enable Register */ - AT91_REG PIO_ODR; /* Output Disable Registerr */ - AT91_REG PIO_OSR; /* Output Status Register */ - AT91_REG Reserved1[1]; /* */ - AT91_REG PIO_IFER; /* Input Filter Enable Register */ - AT91_REG PIO_IFDR; /* Input Filter Disable Register */ - AT91_REG PIO_IFSR; /* Input Filter Status Register */ - AT91_REG Reserved2[1]; /* */ - AT91_REG PIO_SODR; /* Set Output Data Register */ - AT91_REG PIO_CODR; /* Clear Output Data Register */ - AT91_REG PIO_ODSR; /* Output Data Status Register */ - AT91_REG PIO_PDSR; /* Pin Data Status Register */ - AT91_REG PIO_IER; /* Interrupt Enable Register */ - AT91_REG PIO_IDR; /* Interrupt Disable Register */ - AT91_REG PIO_IMR; /* Interrupt Mask Register */ - AT91_REG PIO_ISR; /* Interrupt Status Register */ - AT91_REG PIO_MDER; /* Multi-driver Enable Register */ - AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ - AT91_REG PIO_MDSR; /* Multi-driver Status Register */ - AT91_REG Reserved3[1]; /* */ - AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ - AT91_REG PIO_PPUER; /* Pull-up Enable Register */ - AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */ - AT91_REG Reserved4[1]; /* */ - AT91_REG PIO_ASR; /* Select A Register */ - AT91_REG PIO_BSR; /* Select B Register */ - AT91_REG PIO_ABSR; /* AB Select Status Register */ - AT91_REG Reserved5[9]; /* */ - AT91_REG PIO_OWER; /* Output Write Enable Register */ - AT91_REG PIO_OWDR; /* Output Write Disable Register */ - AT91_REG PIO_OWSR; /* Output Write Status Register */ + AT91_REG PIO_PER; /* PIO Enable Register */ + AT91_REG PIO_PDR; /* PIO Disable Register */ + AT91_REG PIO_PSR; /* PIO Status Register */ + AT91_REG Reserved0[1]; /* */ + AT91_REG PIO_OER; /* Output Enable Register */ + AT91_REG PIO_ODR; /* Output Disable Registerr */ + AT91_REG PIO_OSR; /* Output Status Register */ + AT91_REG Reserved1[1]; /* */ + AT91_REG PIO_IFER; /* Input Filter Enable Register */ + AT91_REG PIO_IFDR; /* Input Filter Disable Register */ + AT91_REG PIO_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved2[1]; /* */ + AT91_REG PIO_SODR; /* Set Output Data Register */ + AT91_REG PIO_CODR; /* Clear Output Data Register */ + AT91_REG PIO_ODSR; /* Output Data Status Register */ + AT91_REG PIO_PDSR; /* Pin Data Status Register */ + AT91_REG PIO_IER; /* Interrupt Enable Register */ + AT91_REG PIO_IDR; /* Interrupt Disable Register */ + AT91_REG PIO_IMR; /* Interrupt Mask Register */ + AT91_REG PIO_ISR; /* Interrupt Status Register */ + AT91_REG PIO_MDER; /* Multi-driver Enable Register */ + AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIO_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved3[1]; /* */ + AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIO_PPUER; /* Pull-up Enable Register */ + AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */ + AT91_REG Reserved4[1]; /* */ + AT91_REG PIO_ASR; /* Select A Register */ + AT91_REG PIO_BSR; /* Select B Register */ + AT91_REG PIO_ABSR; /* AB Select Status Register */ + AT91_REG Reserved5[9]; /* */ + AT91_REG PIO_OWER; /* Output Write Enable Register */ + AT91_REG PIO_OWDR; /* Output Write Disable Register */ + AT91_REG PIO_OWSR; /* Output Write Status Register */ } AT91S_PIO, *AT91PS_PIO; @@ -189,30 +189,30 @@ typedef struct _AT91S_PIO /*****************************************************************************/ typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; /* Control Register */ - AT91_REG DBGU_MR; /* Mode Register */ - AT91_REG DBGU_IER; /* Interrupt Enable Register */ - AT91_REG DBGU_IDR; /* Interrupt Disable Register */ - AT91_REG DBGU_IMR; /* Interrupt Mask Register */ - AT91_REG DBGU_CSR; /* Channel Status Register */ - AT91_REG DBGU_RHR; /* Receiver Holding Register */ - AT91_REG DBGU_THR; /* Transmitter Holding Register */ - AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ - AT91_REG Reserved0[7]; /* */ - AT91_REG DBGU_C1R; /* Chip ID1 Register */ - AT91_REG DBGU_C2R; /* Chip ID2 Register */ - AT91_REG DBGU_FNTR; /* Force NTRST Register */ - AT91_REG Reserved1[45]; /* */ - AT91_REG DBGU_RPR; /* Receive Pointer Register */ - AT91_REG DBGU_RCR; /* Receive Counter Register */ - AT91_REG DBGU_TPR; /* Transmit Pointer Register */ - AT91_REG DBGU_TCR; /* Transmit Counter Register */ - AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ - AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ - AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ - AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ - AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ - AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved0[7]; /* */ + AT91_REG DBGU_C1R; /* Chip ID1 Register */ + AT91_REG DBGU_C2R; /* Chip ID2 Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved1[45]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ } AT91S_DBGU, *AT91PS_DBGU; /* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ @@ -247,7 +247,7 @@ typedef struct _AT91S_DBGU /*****************************************************************************/ typedef struct _AT91S_SMC2 { - AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */ + AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */ } AT91S_SMC2, *AT91PS_SMC2; /* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- */ @@ -272,21 +272,21 @@ typedef struct _AT91S_SMC2 /*****************************************************************************/ typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; /* System Clock Enable Register */ - AT91_REG PMC_SCDR; /* System Clock Disable Register */ - AT91_REG PMC_SCSR; /* System Clock Status Register */ - AT91_REG Reserved0[1]; /* */ - AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ - AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ - AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ - AT91_REG Reserved1[5]; /* */ - AT91_REG PMC_MCKR; /* Master Clock Register */ - AT91_REG Reserved2[3]; /* */ - AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */ - AT91_REG PMC_IER; /* Interrupt Enable Register */ - AT91_REG PMC_IDR; /* Interrupt Disable Register */ - AT91_REG PMC_SR; /* Status Register */ - AT91_REG PMC_IMR; /* Interrupt Mask Register */ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved0[1]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved1[5]; /* */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved2[3]; /* */ + AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ } AT91S_PMC, *AT91PS_PMC; /*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/ @@ -346,49 +346,49 @@ typedef struct _AT91S_PMC /*****************************************************************************/ typedef struct _AT91S_EMAC { - AT91_REG EMAC_CTL; /* Network Control Register */ - AT91_REG EMAC_CFG; /* Network Configuration Register */ - AT91_REG EMAC_SR; /* Network Status Register */ - AT91_REG EMAC_TAR; /* Transmit Address Register */ - AT91_REG EMAC_TCR; /* Transmit Control Register */ - AT91_REG EMAC_TSR; /* Transmit Status Register */ - AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */ - AT91_REG Reserved0[1]; /* */ - AT91_REG EMAC_RSR; /* Receive Status Register */ - AT91_REG EMAC_ISR; /* Interrupt Status Register */ - AT91_REG EMAC_IER; /* Interrupt Enable Register */ - AT91_REG EMAC_IDR; /* Interrupt Disable Register */ - AT91_REG EMAC_IMR; /* Interrupt Mask Register */ - AT91_REG EMAC_MAN; /* PHY Maintenance Register */ - AT91_REG Reserved1[2]; /* */ - AT91_REG EMAC_FRA; /* Frames Transmitted OK Register */ - AT91_REG EMAC_SCOL; /* Single Collision Frame Register */ - AT91_REG EMAC_MCOL; /* Multiple Collision Frame Register */ - AT91_REG EMAC_OK; /* Frames Received OK Register */ - AT91_REG EMAC_SEQE; /* Frame Check Sequence Error Register */ - AT91_REG EMAC_ALE; /* Alignment Error Register */ - AT91_REG EMAC_DTE; /* Deferred Transmission Frame Register */ - AT91_REG EMAC_LCOL; /* Late Collision Register */ - AT91_REG EMAC_ECOL; /* Excessive Collision Register */ - AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ - AT91_REG EMAC_TUE; /* Transmit Underrun Error Register */ - AT91_REG EMAC_CDE; /* Code Error Register */ - AT91_REG EMAC_ELR; /* Excessive Length Error Register */ - AT91_REG EMAC_RJB; /* Receive Jabber Register */ - AT91_REG EMAC_USF; /* Undersize Frame Register */ - AT91_REG EMAC_SQEE; /* SQE Test Error Register */ - AT91_REG EMAC_DRFC; /* Discarded RX Frame Register */ - AT91_REG Reserved2[3]; /* */ - AT91_REG EMAC_HSH; /* Hash Address High[63:32] */ - AT91_REG EMAC_HSL; /* Hash Address Low[31:0] */ - AT91_REG EMAC_SA1L; /* Specific Address 1 Low, First 4 bytes */ - AT91_REG EMAC_SA1H; /* Specific Address 1 High, Last 2 bytes */ - AT91_REG EMAC_SA2L; /* Specific Address 2 Low, First 4 bytes */ - AT91_REG EMAC_SA2H; /* Specific Address 2 High, Last 2 bytes */ - AT91_REG EMAC_SA3L; /* Specific Address 3 Low, First 4 bytes */ - AT91_REG EMAC_SA3H; /* Specific Address 3 High, Last 2 bytes */ - AT91_REG EMAC_SA4L; /* Specific Address 4 Low, First 4 bytes */ - AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */ + AT91_REG EMAC_CTL; /* Network Control Register */ + AT91_REG EMAC_CFG; /* Network Configuration Register */ + AT91_REG EMAC_SR; /* Network Status Register */ + AT91_REG EMAC_TAR; /* Transmit Address Register */ + AT91_REG EMAC_TCR; /* Transmit Control Register */ + AT91_REG EMAC_TSR; /* Transmit Status Register */ + AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */ + AT91_REG Reserved0[1]; /* */ + AT91_REG EMAC_RSR; /* Receive Status Register */ + AT91_REG EMAC_ISR; /* Interrupt Status Register */ + AT91_REG EMAC_IER; /* Interrupt Enable Register */ + AT91_REG EMAC_IDR; /* Interrupt Disable Register */ + AT91_REG EMAC_IMR; /* Interrupt Mask Register */ + AT91_REG EMAC_MAN; /* PHY Maintenance Register */ + AT91_REG Reserved1[2]; /* */ + AT91_REG EMAC_FRA; /* Frames Transmitted OK Register */ + AT91_REG EMAC_SCOL; /* Single Collision Frame Register */ + AT91_REG EMAC_MCOL; /* Multiple Collision Frame Register */ + AT91_REG EMAC_OK; /* Frames Received OK Register */ + AT91_REG EMAC_SEQE; /* Frame Check Sequence Error Register */ + AT91_REG EMAC_ALE; /* Alignment Error Register */ + AT91_REG EMAC_DTE; /* Deferred Transmission Frame Register */ + AT91_REG EMAC_LCOL; /* Late Collision Register */ + AT91_REG EMAC_ECOL; /* Excessive Collision Register */ + AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ + AT91_REG EMAC_TUE; /* Transmit Underrun Error Register */ + AT91_REG EMAC_CDE; /* Code Error Register */ + AT91_REG EMAC_ELR; /* Excessive Length Error Register */ + AT91_REG EMAC_RJB; /* Receive Jabber Register */ + AT91_REG EMAC_USF; /* Undersize Frame Register */ + AT91_REG EMAC_SQEE; /* SQE Test Error Register */ + AT91_REG EMAC_DRFC; /* Discarded RX Frame Register */ + AT91_REG Reserved2[3]; /* */ + AT91_REG EMAC_HSH; /* Hash Address High[63:32] */ + AT91_REG EMAC_HSL; /* Hash Address Low[31:0] */ + AT91_REG EMAC_SA1L; /* Specific Address 1 Low, First 4 bytes */ + AT91_REG EMAC_SA1H; /* Specific Address 1 High, Last 2 bytes */ + AT91_REG EMAC_SA2L; /* Specific Address 2 Low, First 4 bytes */ + AT91_REG EMAC_SA2H; /* Specific Address 2 High, Last 2 bytes */ + AT91_REG EMAC_SA3L; /* Specific Address 3 Low, First 4 bytes */ + AT91_REG EMAC_SA3H; /* Specific Address 3 High, Last 2 bytes */ + AT91_REG EMAC_SA4L; /* Specific Address 4 Low, First 4 bytes */ + AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */ } AT91S_EMAC, *AT91PS_EMAC; /* -------- EMAC_CTL : (EMAC Offset: 0x0) -------- */ @@ -476,27 +476,27 @@ typedef struct _AT91S_EMAC /*****************************************************************************/ typedef struct _AT91S_SPI { - AT91_REG SPI_CR; /* Control Register */ - AT91_REG SPI_MR; /* Mode Register */ - AT91_REG SPI_RDR; /* Receive Data Register */ - AT91_REG SPI_TDR; /* Transmit Data Register */ - AT91_REG SPI_SR; /* Status Register */ - AT91_REG SPI_IER; /* Interrupt Enable Register */ - AT91_REG SPI_IDR; /* Interrupt Disable Register */ - AT91_REG SPI_IMR; /* Interrupt Mask Register */ - AT91_REG Reserved0[4]; /* */ - AT91_REG SPI_CSR[4]; /* Chip Select Register */ + AT91_REG SPI_CR; /* Control Register */ + AT91_REG SPI_MR; /* Mode Register */ + AT91_REG SPI_RDR; /* Receive Data Register */ + AT91_REG SPI_TDR; /* Transmit Data Register */ + AT91_REG SPI_SR; /* Status Register */ + AT91_REG SPI_IER; /* Interrupt Enable Register */ + AT91_REG SPI_IDR; /* Interrupt Disable Register */ + AT91_REG SPI_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved0[4]; /* */ + AT91_REG SPI_CSR[4]; /* Chip Select Register */ AT91_REG Reserved1[48]; /* */ - AT91_REG SPI_RPR; /* Receive Pointer Register */ - AT91_REG SPI_RCR; /* Receive Counter Register */ - AT91_REG SPI_TPR; /* Transmit Pointer Register */ - AT91_REG SPI_TCR; /* Transmit Counter Register */ - AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ - AT91_REG SPI_RNCR; /* Receive Next Counter Register */ - AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ - AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ - AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ - AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ + AT91_REG SPI_RPR; /* Receive Pointer Register */ + AT91_REG SPI_RCR; /* Receive Counter Register */ + AT91_REG SPI_TPR; /* Transmit Pointer Register */ + AT91_REG SPI_TCR; /* Transmit Counter Register */ + AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ + AT91_REG SPI_RNCR; /* Receive Next Counter Register */ + AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ + AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ + AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ } AT91S_SPI, *AT91PS_SPI; /* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ @@ -560,16 +560,16 @@ typedef struct _AT91S_SPI /*****************************************************************************/ typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; /* Receive Pointer Register */ - AT91_REG PDC_RCR; /* Receive Counter Register */ - AT91_REG PDC_TPR; /* Transmit Pointer Register */ - AT91_REG PDC_TCR; /* Transmit Counter Register */ - AT91_REG PDC_RNPR; /* Receive Next Pointer Register */ - AT91_REG PDC_RNCR; /* Receive Next Counter Register */ - AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */ - AT91_REG PDC_TNCR; /* Transmit Next Counter Register */ - AT91_REG PDC_PTCR; /* PDC Transfer Control Register */ - AT91_REG PDC_PTSR; /* PDC Transfer Status Register */ + AT91_REG PDC_RPR; /* Receive Pointer Register */ + AT91_REG PDC_RCR; /* Receive Counter Register */ + AT91_REG PDC_TPR; /* Transmit Pointer Register */ + AT91_REG PDC_TCR; /* Transmit Counter Register */ + AT91_REG PDC_RNPR; /* Receive Next Pointer Register */ + AT91_REG PDC_RNCR; /* Receive Next Counter Register */ + AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG PDC_TNCR; /* Transmit Next Counter Register */ + AT91_REG PDC_PTCR; /* PDC Transfer Control Register */ + AT91_REG PDC_PTSR; /* PDC Transfer Status Register */ } AT91S_PDC, *AT91PS_PDC; /* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ @@ -700,7 +700,7 @@ typedef struct _AT91S_PDC #define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */ #define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */ #define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */ -#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) /* Pin Controlled by PB22 */ +#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) /* Pin Controlled by PB22 */ #define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */ #define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */ #define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */ @@ -775,7 +775,7 @@ typedef struct _AT91S_PDC #define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */ #define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */ #define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) /* (PIOC) PIO Enable Register */ -#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */ +#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */ #define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */ #define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */ #define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */ diff --git a/include/asm-arm/arch-at91sam9/gpio.h b/include/asm-arm/arch-at91sam9/gpio.h index c157e10..c4d7b97 100644 --- a/include/asm-arm/arch-at91sam9/gpio.h +++ b/include/asm-arm/arch-at91sam9/gpio.h @@ -218,7 +218,7 @@ static inline unsigned pin_to_mask(unsigned pin) */ static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup) { - void *pio = pin_to_controller(pin); + void *pio = pin_to_controller(pin); unsigned mask = pin_to_mask(pin); __raw_writel(mask, pio + PIO_IDR); @@ -232,7 +232,7 @@ static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup) */ static inline int at91_set_A_periph(unsigned pin, int use_pullup) { - void *pio = pin_to_controller(pin); + void *pio = pin_to_controller(pin); unsigned mask = pin_to_mask(pin); __raw_writel(mask, pio + PIO_IDR); diff --git a/include/asm-arm/arch-ixp/ixp425.h b/include/asm-arm/arch-ixp/ixp425.h index 11dc356..2114437 100644 --- a/include/asm-arm/arch-ixp/ixp425.h +++ b/include/asm-arm/arch-ixp/ixp425.h @@ -53,13 +53,13 @@ * * 0x6000000 0x00004000 0x4000 0xFFFEB000 QMgr * - * 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG + * 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG * * 0xC4000000 0x100 0x1000 0xFFFDE000 EXP CFG * * 0xC8000000 0xC000 0xC000 0xFFFDF000 PERIPHERAL * - * 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG + * 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG */ /* @@ -171,17 +171,17 @@ #define IXP425_SDR_REFRESH_OFFSET 0x04 #define IXP425_SDR_IR_OFFSET 0x08 -#define IXP425_SDRAM_REG(x) (IXP425_SDRAM_CFG_BASE_PHYS+(x)) +#define IXP425_SDRAM_REG(x) (IXP425_SDRAM_CFG_BASE_PHYS+(x)) #define IXP425_SDR_CONFIG IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET) -#define IXP425_SDR_REFRESH IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET) -#define IXP425_SDR_IR IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET) +#define IXP425_SDR_REFRESH IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET) +#define IXP425_SDR_IR IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET) /* * UART registers */ -#define IXP425_UART1 0 -#define IXP425_UART2 0x1000 +#define IXP425_UART1 0 +#define IXP425_UART2 0x1000 #define IXP425_UART_RBR_OFFSET 0x00 #define IXP425_UART_THR_OFFSET 0x00 @@ -476,49 +476,49 @@ */ /* CSR bit definitions */ -#define PCI_CSR_HOST BIT(0) -#define PCI_CSR_ARBEN BIT(1) -#define PCI_CSR_ADS BIT(2) -#define PCI_CSR_PDS BIT(3) -#define PCI_CSR_ABE BIT(4) -#define PCI_CSR_DBT BIT(5) -#define PCI_CSR_ASE BIT(8) -#define PCI_CSR_IC BIT(15) +#define PCI_CSR_HOST BIT(0) +#define PCI_CSR_ARBEN BIT(1) +#define PCI_CSR_ADS BIT(2) +#define PCI_CSR_PDS BIT(3) +#define PCI_CSR_ABE BIT(4) +#define PCI_CSR_DBT BIT(5) +#define PCI_CSR_ASE BIT(8) +#define PCI_CSR_IC BIT(15) /* ISR (Interrupt status) Register bit definitions */ -#define PCI_ISR_PSE BIT(0) -#define PCI_ISR_PFE BIT(1) -#define PCI_ISR_PPE BIT(2) -#define PCI_ISR_AHBE BIT(3) -#define PCI_ISR_APDC BIT(4) -#define PCI_ISR_PADC BIT(5) -#define PCI_ISR_ADB BIT(6) -#define PCI_ISR_PDB BIT(7) +#define PCI_ISR_PSE BIT(0) +#define PCI_ISR_PFE BIT(1) +#define PCI_ISR_PPE BIT(2) +#define PCI_ISR_AHBE BIT(3) +#define PCI_ISR_APDC BIT(4) +#define PCI_ISR_PADC BIT(5) +#define PCI_ISR_ADB BIT(6) +#define PCI_ISR_PDB BIT(7) /* INTEN (Interrupt Enable) Register bit definitions */ -#define PCI_INTEN_PSE BIT(0) -#define PCI_INTEN_PFE BIT(1) -#define PCI_INTEN_PPE BIT(2) -#define PCI_INTEN_AHBE BIT(3) -#define PCI_INTEN_APDC BIT(4) -#define PCI_INTEN_PADC BIT(5) -#define PCI_INTEN_ADB BIT(6) -#define PCI_INTEN_PDB BIT(7) +#define PCI_INTEN_PSE BIT(0) +#define PCI_INTEN_PFE BIT(1) +#define PCI_INTEN_PPE BIT(2) +#define PCI_INTEN_AHBE BIT(3) +#define PCI_INTEN_APDC BIT(4) +#define PCI_INTEN_PADC BIT(5) +#define PCI_INTEN_ADB BIT(6) +#define PCI_INTEN_PDB BIT(7) /* * Shift value for byte enable on NP cmd/byte enable register */ -#define IXP425_PCI_NP_CBE_BESL 4 +#define IXP425_PCI_NP_CBE_BESL 4 /* * PCI commands supported by NP access unit */ -#define NP_CMD_IOREAD 0x2 -#define NP_CMD_IOWRITE 0x3 -#define NP_CMD_CONFIGREAD 0xa -#define NP_CMD_CONFIGWRITE 0xb -#define NP_CMD_MEMREAD 0x6 -#define NP_CMD_MEMWRITE 0x7 +#define NP_CMD_IOREAD 0x2 +#define NP_CMD_IOWRITE 0x3 +#define NP_CMD_CONFIGREAD 0xa +#define NP_CMD_CONFIGWRITE 0xb +#define NP_CMD_MEMREAD 0x6 +#define NP_CMD_MEMWRITE 0x7 #if 0 #ifndef __ASSEMBLY__ diff --git a/include/asm-arm/arch-omap24xx/clocks.h b/include/asm-arm/arch-omap24xx/clocks.h index 2a95af1..2e92569 100644 --- a/include/asm-arm/arch-omap24xx/clocks.h +++ b/include/asm-arm/arch-omap24xx/clocks.h @@ -35,9 +35,9 @@ ; PRCM Scheme II ; ; Enable clocks and DPLL for: -; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50 -; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] -; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0] +; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50 +; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] +; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0] ; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0] ; DSPI=100 6 CM_CLKSEL_DSP[6:5] ; DSP_S bypass CM_CLKSEL_DSP[7] @@ -64,9 +64,9 @@ ; PRCM Scheme III ; ; Enable clocks and DPLL for: -; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266 -; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] -; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0] +; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266 +; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] +; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0] ; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0] ; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5] ; DSP_S ACTIVATED CM_CLKSEL_DSP[7] diff --git a/include/asm-arm/arch-pxa/bitfield.h b/include/asm-arm/arch-pxa/bitfield.h index 2ac5ea2..104a21c 100644 --- a/include/asm-arm/arch-pxa/bitfield.h +++ b/include/asm-arm/arch-pxa/bitfield.h @@ -1,13 +1,13 @@ /* - * FILE bitfield.h + * FILE bitfield.h * - * Version 1.1 - * Author Copyright (c) Marc A. Viredaz, 1998 - * DEC Western Research Laboratory, Palo Alto, CA - * Date April 1998 (April 1997) - * System Advanced RISC Machine (ARM) + * Version 1.1 + * Author Copyright (c) Marc A. Viredaz, 1998 + * DEC Western Research Laboratory, Palo Alto, CA + * Date April 1998 (April 1997) + * System Advanced RISC Machine (ARM) * Language C or ARM Assembly - * Purpose Definition of macros to operate on bit fields. + * Purpose Definition of macros to operate on bit fields. */ @@ -35,11 +35,11 @@ * line-size limit). * * Input - * Size Size of the bit field, in number of bits. - * Shft Shift value of the bit field with respect to bit 0. + * Size Size of the bit field, in number of bits. + * Shft Shift value of the bit field with respect to bit 0. * * Output - * Fld Encoded bit field. + * Fld Encoded bit field. */ #define Fld(Size, Shft) (((Size) << 16) + (Shft)) @@ -54,14 +54,14 @@ * bit field. * * Input - * Field Encoded bit field (using the macro "Fld"). + * Field Encoded bit field (using the macro "Fld"). * * Output - * FSize Size of the bit field, in number of bits. - * FShft Shift value of the bit field with respect to bit 0. - * FMsk Mask for the bit field. - * FAlnMsk Mask for the bit field, aligned on bit 0. - * F1stBit First bit of the bit field. + * FSize Size of the bit field, in number of bits. + * FShft Shift value of the bit field with respect to bit 0. + * FMsk Mask for the bit field. + * FAlnMsk Mask for the bit field, aligned on bit 0. + * F1stBit First bit of the bit field. */ #define FSize(Field) ((Field) >> 16) @@ -79,11 +79,11 @@ * former appropriately. * * Input - * Value Bit-field value. - * Field Encoded bit field (using the macro "Fld"). + * Value Bit-field value. + * Field Encoded bit field (using the macro "Fld"). * * Output - * FInsrt Bit-field value positioned appropriately. + * FInsrt Bit-field value positioned appropriately. */ #define FInsrt(Value, Field) \ @@ -98,11 +98,11 @@ * shifting it appropriately. * * Input - * Data Data containing the bit-field to be extracted. - * Field Encoded bit field (using the macro "Fld"). + * Data Data containing the bit-field to be extracted. + * Field Encoded bit field (using the macro "Fld"). * * Output - * FExtr Bit-field value. + * FExtr Bit-field value. */ #define FExtr(Data, Field) \ diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h index b9304b1..9440d80 100644 --- a/include/asm-arm/arch-pxa/mmc.h +++ b/include/asm-arm/arch-pxa/mmc.h @@ -16,95 +16,95 @@ /* PXA-250 MMC controller registers */ /* MMC_STRPCL */ -#define MMC_STRPCL_STOP_CLK (0x0001UL) +#define MMC_STRPCL_STOP_CLK (0x0001UL) #define MMC_STRPCL_START_CLK (0x0002UL) /* MMC_STAT */ #define MMC_STAT_END_CMD_RES (0x0001UL << 13) -#define MMC_STAT_PRG_DONE (0x0001UL << 12) -#define MMC_STAT_DATA_TRAN_DONE (0x0001UL << 11) -#define MMC_STAT_CLK_EN (0x0001UL << 8) -#define MMC_STAT_RECV_FIFO_FULL (0x0001UL << 7) -#define MMC_STAT_XMIT_FIFO_EMPTY (0x0001UL << 6) -#define MMC_STAT_RES_CRC_ERROR (0x0001UL << 5) +#define MMC_STAT_PRG_DONE (0x0001UL << 12) +#define MMC_STAT_DATA_TRAN_DONE (0x0001UL << 11) +#define MMC_STAT_CLK_EN (0x0001UL << 8) +#define MMC_STAT_RECV_FIFO_FULL (0x0001UL << 7) +#define MMC_STAT_XMIT_FIFO_EMPTY (0x0001UL << 6) +#define MMC_STAT_RES_CRC_ERROR (0x0001UL << 5) #define MMC_STAT_SPI_READ_ERROR_TOKEN (0x0001UL << 4) -#define MMC_STAT_CRC_READ_ERROR (0x0001UL << 3) -#define MMC_STAT_CRC_WRITE_ERROR (0x0001UL << 2) -#define MMC_STAT_TIME_OUT_RESPONSE (0x0001UL << 1) -#define MMC_STAT_READ_TIME_OUT (0x0001UL) +#define MMC_STAT_CRC_READ_ERROR (0x0001UL << 3) +#define MMC_STAT_CRC_WRITE_ERROR (0x0001UL << 2) +#define MMC_STAT_TIME_OUT_RESPONSE (0x0001UL << 1) +#define MMC_STAT_READ_TIME_OUT (0x0001UL) #define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\ |MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\ |MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR) /* MMC_CLKRT */ -#define MMC_CLKRT_20MHZ (0x0000UL) -#define MMC_CLKRT_10MHZ (0x0001UL) -#define MMC_CLKRT_5MHZ (0x0002UL) +#define MMC_CLKRT_20MHZ (0x0000UL) +#define MMC_CLKRT_10MHZ (0x0001UL) +#define MMC_CLKRT_5MHZ (0x0002UL) #define MMC_CLKRT_2_5MHZ (0x0003UL) -#define MMC_CLKRT_1_25MHZ (0x0004UL) -#define MMC_CLKRT_0_625MHZ (0x0005UL) -#define MMC_CLKRT_0_3125MHZ (0x0006UL) +#define MMC_CLKRT_1_25MHZ (0x0004UL) +#define MMC_CLKRT_0_625MHZ (0x0005UL) +#define MMC_CLKRT_0_3125MHZ (0x0006UL) /* MMC_SPI */ -#define MMC_SPI_DISABLE (0x00UL) -#define MMC_SPI_EN (0x01UL) -#define MMC_SPI_CS_EN (0x01UL << 2) -#define MMC_SPI_CS_ADDRESS (0x01UL << 3) -#define MMC_SPI_CRC_ON (0x01UL << 1) +#define MMC_SPI_DISABLE (0x00UL) +#define MMC_SPI_EN (0x01UL) +#define MMC_SPI_CS_EN (0x01UL << 2) +#define MMC_SPI_CS_ADDRESS (0x01UL << 3) +#define MMC_SPI_CRC_ON (0x01UL << 1) /* MMC_CMDAT */ #define MMC_CMDAT_SD_4DAT (0x0001UL << 8) #define MMC_CMDAT_MMC_DMA_EN (0x0001UL << 7) -#define MMC_CMDAT_INIT (0x0001UL << 6) -#define MMC_CMDAT_BUSY (0x0001UL << 5) -#define MMC_CMDAT_BCR (0x0003UL << 5) +#define MMC_CMDAT_INIT (0x0001UL << 6) +#define MMC_CMDAT_BUSY (0x0001UL << 5) +#define MMC_CMDAT_BCR (0x0003UL << 5) #define MMC_CMDAT_STREAM (0x0001UL << 4) -#define MMC_CMDAT_BLOCK (0x0000UL << 4) -#define MMC_CMDAT_WRITE (0x0001UL << 3) -#define MMC_CMDAT_READ (0x0000UL << 3) -#define MMC_CMDAT_DATA_EN (0x0001UL << 2) -#define MMC_CMDAT_R0 (0) -#define MMC_CMDAT_R1 (0x0001UL) -#define MMC_CMDAT_R2 (0x0002UL) -#define MMC_CMDAT_R3 (0x0003UL) +#define MMC_CMDAT_BLOCK (0x0000UL << 4) +#define MMC_CMDAT_WRITE (0x0001UL << 3) +#define MMC_CMDAT_READ (0x0000UL << 3) +#define MMC_CMDAT_DATA_EN (0x0001UL << 2) +#define MMC_CMDAT_R0 (0) +#define MMC_CMDAT_R1 (0x0001UL) +#define MMC_CMDAT_R2 (0x0002UL) +#define MMC_CMDAT_R3 (0x0003UL) /* MMC_RESTO */ -#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */ +#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */ /* MMC_RDTO */ -#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */ +#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */ /* MMC_BLKLEN */ -#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */ +#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */ /* MMC_PRTBUF */ -#define MMC_PRTBUF_BUF_PART_FULL (0x01UL) +#define MMC_PRTBUF_BUF_PART_FULL (0x01UL) #define MMC_PRTBUF_BUF_FULL (0x00UL ) /* MMC_I_MASK */ #define MMC_I_MASK_TXFIFO_WR_REQ (0x01UL << 6) #define MMC_I_MASK_RXFIFO_RD_REQ (0x01UL << 5) -#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4) -#define MMC_I_MASK_STOP_CMD (0x01UL << 3) -#define MMC_I_MASK_END_CMD_RES (0x01UL << 2) -#define MMC_I_MASK_PRG_DONE (0x01UL << 1) +#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4) +#define MMC_I_MASK_STOP_CMD (0x01UL << 3) +#define MMC_I_MASK_END_CMD_RES (0x01UL << 2) +#define MMC_I_MASK_PRG_DONE (0x01UL << 1) #define MMC_I_MASK_DATA_TRAN_DONE (0x01UL) -#define MMC_I_MASK_ALL (0x07fUL) +#define MMC_I_MASK_ALL (0x07fUL) /* MMC_I_REG */ -#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6) -#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5) +#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6) +#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5) #define MMC_I_REG_CLK_IS_OFF (0x01UL << 4) -#define MMC_I_REG_STOP_CMD (0x01UL << 3) -#define MMC_I_REG_END_CMD_RES (0x01UL << 2) -#define MMC_I_REG_PRG_DONE (0x01UL << 1) -#define MMC_I_REG_DATA_TRAN_DONE (0x01UL) -#define MMC_I_REG_ALL (0x007fUL) +#define MMC_I_REG_STOP_CMD (0x01UL << 3) +#define MMC_I_REG_END_CMD_RES (0x01UL << 2) +#define MMC_I_REG_PRG_DONE (0x01UL << 1) +#define MMC_I_REG_DATA_TRAN_DONE (0x01UL) +#define MMC_I_REG_ALL (0x007fUL) /* MMC_CMD */ -#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */ +#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */ #define CMD(x) (x) #define MMC_DEFAULT_RCA 1 @@ -112,11 +112,11 @@ #define MMC_BLOCK_SIZE 512 #define MMC_CMD_RESET 0 #define MMC_CMD_SEND_OP_COND 1 -#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_ALL_SEND_CID 2 #define MMC_CMD_SET_RCA 3 #define MMC_CMD_SELECT_CARD 7 -#define MMC_CMD_SEND_CSD 9 -#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 #define MMC_CMD_SEND_STATUS 13 #define MMC_CMD_SET_BLOCKLEN 16 #define MMC_CMD_READ_BLOCK 17 @@ -203,5 +203,4 @@ typedef struct mmc_csd ecc:2; } mmc_csd_t; - #endif /* __MMC_PXA_P_H__ */ diff --git a/include/asm-arm/arch-s3c24x0/memory.h b/include/asm-arm/arch-s3c24x0/memory.h index 333f218..5e254d2 100644 --- a/include/asm-arm/arch-s3c24x0/memory.h +++ b/include/asm-arm/arch-s3c24x0/memory.h @@ -103,10 +103,10 @@ extern unsigned long __phys_to_virt(unsigned long ppage); * The nodes are matched with the physical memory bank addresses which are * incidentally the same as virtual addresses. * - * node 0: 0xc0000000 - 0xc7ffffff - * node 1: 0xc8000000 - 0xcfffffff - * node 2: 0xd0000000 - 0xd7ffffff - * node 3: 0xd8000000 - 0xdfffffff + * node 0: 0xc0000000 - 0xc7ffffff + * node 1: 0xc8000000 - 0xcfffffff + * node 2: 0xd0000000 - 0xd7ffffff + * node 3: 0xd8000000 - 0xdfffffff */ #define NR_NODES 4 diff --git a/include/asm-arm/arch-sa1100/bitfield.h b/include/asm-arm/arch-sa1100/bitfield.h index 2ac5ea2..104a21c 100644 --- a/include/asm-arm/arch-sa1100/bitfield.h +++ b/include/asm-arm/arch-sa1100/bitfield.h @@ -1,13 +1,13 @@ /* - * FILE bitfield.h + * FILE bitfield.h * - * Version 1.1 - * Author Copyright (c) Marc A. Viredaz, 1998 - * DEC Western Research Laboratory, Palo Alto, CA - * Date April 1998 (April 1997) - * System Advanced RISC Machine (ARM) + * Version 1.1 + * Author Copyright (c) Marc A. Viredaz, 1998 + * DEC Western Research Laboratory, Palo Alto, CA + * Date April 1998 (April 1997) + * System Advanced RISC Machine (ARM) * Language C or ARM Assembly - * Purpose Definition of macros to operate on bit fields. + * Purpose Definition of macros to operate on bit fields. */ @@ -35,11 +35,11 @@ * line-size limit). * * Input - * Size Size of the bit field, in number of bits. - * Shft Shift value of the bit field with respect to bit 0. + * Size Size of the bit field, in number of bits. + * Shft Shift value of the bit field with respect to bit 0. * * Output - * Fld Encoded bit field. + * Fld Encoded bit field. */ #define Fld(Size, Shft) (((Size) << 16) + (Shft)) @@ -54,14 +54,14 @@ * bit field. * * Input - * Field Encoded bit field (using the macro "Fld"). + * Field Encoded bit field (using the macro "Fld"). * * Output - * FSize Size of the bit field, in number of bits. - * FShft Shift value of the bit field with respect to bit 0. - * FMsk Mask for the bit field. - * FAlnMsk Mask for the bit field, aligned on bit 0. - * F1stBit First bit of the bit field. + * FSize Size of the bit field, in number of bits. + * FShft Shift value of the bit field with respect to bit 0. + * FMsk Mask for the bit field. + * FAlnMsk Mask for the bit field, aligned on bit 0. + * F1stBit First bit of the bit field. */ #define FSize(Field) ((Field) >> 16) @@ -79,11 +79,11 @@ * former appropriately. * * Input - * Value Bit-field value. - * Field Encoded bit field (using the macro "Fld"). + * Value Bit-field value. + * Field Encoded bit field (using the macro "Fld"). * * Output - * FInsrt Bit-field value positioned appropriately. + * FInsrt Bit-field value positioned appropriately. */ #define FInsrt(Value, Field) \ @@ -98,11 +98,11 @@ * shifting it appropriately. * * Input - * Data Data containing the bit-field to be extracted. - * Field Encoded bit field (using the macro "Fld"). + * Data Data containing the bit-field to be extracted. + * Field Encoded bit field (using the macro "Fld"). * * Output - * FExtr Bit-field value. + * FExtr Bit-field value. */ #define FExtr(Data, Field) \ diff --git a/include/asm-arm/u-boot.h b/include/asm-arm/u-boot.h index c120312..b11d555 100644 --- a/include/asm-arm/u-boot.h +++ b/include/asm-arm/u-boot.h @@ -47,7 +47,7 @@ typedef struct bd_info { { ulong start; ulong size; - } bi_dram[CONFIG_NR_DRAM_BANKS]; + } bi_dram[CONFIG_NR_DRAM_BANKS]; #ifdef CONFIG_HAS_ETH1 /* second onboard ethernet port */ unsigned char bi_enet1addr[6]; |