diff options
Diffstat (limited to 'include/asm-arm/arch-a320')
| -rw-r--r-- | include/asm-arm/arch-a320/a320.h | 34 | ||||
| -rw-r--r-- | include/asm-arm/arch-a320/ftpmu010.h | 146 | ||||
| -rw-r--r-- | include/asm-arm/arch-a320/ftsdmc020.h | 103 | ||||
| -rw-r--r-- | include/asm-arm/arch-a320/ftsmc020.h | 79 | ||||
| -rw-r--r-- | include/asm-arm/arch-a320/fttmr010.h | 73 |
5 files changed, 0 insertions, 435 deletions
diff --git a/include/asm-arm/arch-a320/a320.h b/include/asm-arm/arch-a320/a320.h deleted file mode 100644 index fbd1583..0000000 --- a/include/asm-arm/arch-a320/a320.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __A320_H -#define __A320_H - -/* - * Hardware register bases - */ -#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller */ -#define CONFIG_DEBUG_LED 0x902ffffc /* Debug LED */ -#define CONFIG_FTSDMC020_BASE 0x90300000 /* SDRAM Controller */ -#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */ -#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */ -#define CONFIG_FTTMR010_BASE 0x98400000 /* Timer */ -#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock*/ - -#endif /* __A320_H */ diff --git a/include/asm-arm/arch-a320/ftpmu010.h b/include/asm-arm/arch-a320/ftpmu010.h deleted file mode 100644 index 8ef7a37..0000000 --- a/include/asm-arm/arch-a320/ftpmu010.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -/* - * Power Management Unit - */ -#ifndef __FTPMU010_H -#define __FTPMU010_H - -struct ftpmu010 { - unsigned int IDNMBR0; /* 0x00 */ - unsigned int reserved0; /* 0x04 */ - unsigned int OSCC; /* 0x08 */ - unsigned int PMODE; /* 0x0C */ - unsigned int PMCR; /* 0x10 */ - unsigned int PED; /* 0x14 */ - unsigned int PEDSR; /* 0x18 */ - unsigned int reserved1; /* 0x1C */ - unsigned int PMSR; /* 0x20 */ - unsigned int PGSR; /* 0x24 */ - unsigned int MFPSR; /* 0x28 */ - unsigned int MISC; /* 0x2C */ - unsigned int PDLLCR0; /* 0x30 */ - unsigned int PDLLCR1; /* 0x34 */ - unsigned int AHBMCLKOFF; /* 0x38 */ - unsigned int APBMCLKOFF; /* 0x3C */ - unsigned int DCSRCR0; /* 0x40 */ - unsigned int DCSRCR1; /* 0x44 */ - unsigned int DCSRCR2; /* 0x48 */ - unsigned int SDRAMHTC; /* 0x4C */ - unsigned int PSPR0; /* 0x50 */ - unsigned int PSPR1; /* 0x54 */ - unsigned int PSPR2; /* 0x58 */ - unsigned int PSPR3; /* 0x5C */ - unsigned int PSPR4; /* 0x60 */ - unsigned int PSPR5; /* 0x64 */ - unsigned int PSPR6; /* 0x68 */ - unsigned int PSPR7; /* 0x6C */ - unsigned int PSPR8; /* 0x70 */ - unsigned int PSPR9; /* 0x74 */ - unsigned int PSPR10; /* 0x78 */ - unsigned int PSPR11; /* 0x7C */ - unsigned int PSPR12; /* 0x80 */ - unsigned int PSPR13; /* 0x84 */ - unsigned int PSPR14; /* 0x88 */ - unsigned int PSPR15; /* 0x8C */ - unsigned int AHBDMA_RACCS; /* 0x90 */ - unsigned int reserved2; /* 0x94 */ - unsigned int reserved3; /* 0x98 */ - unsigned int JSS; /* 0x9C */ - unsigned int CFC_RACC; /* 0xA0 */ - unsigned int SSP1_RACC; /* 0xA4 */ - unsigned int UART1TX_RACC; /* 0xA8 */ - unsigned int UART1RX_RACC; /* 0xAC */ - unsigned int UART2TX_RACC; /* 0xB0 */ - unsigned int UART2RX_RACC; /* 0xB4 */ - unsigned int SDC_RACC; /* 0xB8 */ - unsigned int I2SAC97_RACC; /* 0xBC */ - unsigned int IRDATX_RACC; /* 0xC0 */ - unsigned int reserved4; /* 0xC4 */ - unsigned int USBD_RACC; /* 0xC8 */ - unsigned int IRDARX_RACC; /* 0xCC */ - unsigned int IRDA_RACC; /* 0xD0 */ - unsigned int ED0_RACC; /* 0xD4 */ - unsigned int ED1_RACC; /* 0xD8 */ -}; - -/* - * ID Number 0 Register - */ -#define FTPMU010_ID_A320A 0x03200000 -#define FTPMU010_ID_A320C 0x03200010 -#define FTPMU010_ID_A320D 0x03200030 - -/* - * OSC Control Register - */ -#define FTPMU010_OSCC_OSCH_TRI (1 << 11) -#define FTPMU010_OSCC_OSCH_STABLE (1 << 9) -#define FTPMU010_OSCC_OSCH_OFF (1 << 8) - -#define FTPMU010_OSCC_OSCL_TRI (1 << 3) -#define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2) -#define FTPMU010_OSCC_OSCL_STABLE (1 << 1) -#define FTPMU010_OSCC_OSCL_OFF (1 << 0) - -/* - * Power Mode Register - */ -#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4) -#define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7) -#define FTPMU010_PMODE_FCS (1 << 2) -#define FTPMU010_PMODE_TURBO (1 << 1) -#define FTPMU010_PMODE_SLEEP (1 << 0) - -/* - * Power Manager Status Register - */ -#define FTPMU010_PMSR_SMR (1 << 10) - -#define FTPMU010_PMSR_RDH (1 << 2) -#define FTPMU010_PMSR_PH (1 << 1) -#define FTPMU010_PMSR_CKEHLOW (1 << 0) - -/* - * Multi-Function Port Setting Register - */ -#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) -#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) -#define FTPMU010_MFPSR_AC97PINSEL (1 << 3) - -/* - * PLL/DLL Control Register 0 - */ -#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) >> 20) & 0xf) -#define FTPMU010_PDLLCR0_DLLFRAG (1 << 19) -#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18) -#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17) -#define FTPMU010_PDLLCR0_DLLDIS (1 << 16) -#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) >> 3) & 0x1ff) -#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2) -#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1) -#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) - -#endif /* __FTPMU010_H */ diff --git a/include/asm-arm/arch-a320/ftsdmc020.h b/include/asm-arm/arch-a320/ftsdmc020.h deleted file mode 100644 index 0699772..0000000 --- a/include/asm-arm/arch-a320/ftsdmc020.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -/* - * SDRAM Controller - */ -#ifndef __FTSDMC020_H -#define __FTSDMC020_H - -#define FTSDMC020_OFFSET_TP0 0x00 -#define FTSDMC020_OFFSET_TP1 0x04 -#define FTSDMC020_OFFSET_CR 0x08 -#define FTSDMC020_OFFSET_BANK0_BSR 0x0C -#define FTSDMC020_OFFSET_BANK1_BSR 0x10 -#define FTSDMC020_OFFSET_BANK2_BSR 0x14 -#define FTSDMC020_OFFSET_BANK3_BSR 0x18 -#define FTSDMC020_OFFSET_BANK4_BSR 0x1C -#define FTSDMC020_OFFSET_BANK5_BSR 0x20 -#define FTSDMC020_OFFSET_BANK6_BSR 0x24 -#define FTSDMC020_OFFSET_BANK7_BSR 0x28 -#define FTSDMC020_OFFSET_ACR 0x34 - -/* - * Timing Parametet 0 Register - */ -#define FTSDMC020_TP0_TCL(x) ((x) & 0x3) -#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4) -#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8) -#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12) -#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16) -#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20) - -/* - * Timing Parametet 1 Register - */ -#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff) -#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16) -#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20) - -/* - * Configuration Register - */ -#define FTSDMC020_CR_SREF (1 << 0) -#define FTSDMC020_CR_PWDN (1 << 1) -#define FTSDMC020_CR_ISMR (1 << 2) -#define FTSDMC020_CR_IREF (1 << 3) -#define FTSDMC020_CR_IPREC (1 << 4) -#define FTSDMC020_CR_REFTYPE (1 << 5) - -/* - * SDRAM External Bank Base/Size Register - */ -#define FTSDMC020_BANK_ENABLE (1 << 28) - -#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16) - -#define FTSDMC020_BANK_DDW_X4 (0 << 12) -#define FTSDMC020_BANK_DDW_X8 (1 << 12) -#define FTSDMC020_BANK_DDW_X16 (2 << 12) -#define FTSDMC020_BANK_DDW_X32 (3 << 12) - -#define FTSDMC020_BANK_DSZ_16M (0 << 8) -#define FTSDMC020_BANK_DSZ_64M (1 << 8) -#define FTSDMC020_BANK_DSZ_128M (2 << 8) -#define FTSDMC020_BANK_DSZ_256M (3 << 8) - -#define FTSDMC020_BANK_MBW_8 (0 << 4) -#define FTSDMC020_BANK_MBW_16 (1 << 4) -#define FTSDMC020_BANK_MBW_32 (2 << 4) - -#define FTSDMC020_BANK_SIZE_1M 0x0 -#define FTSDMC020_BANK_SIZE_2M 0x1 -#define FTSDMC020_BANK_SIZE_4M 0x2 -#define FTSDMC020_BANK_SIZE_8M 0x3 -#define FTSDMC020_BANK_SIZE_16M 0x4 -#define FTSDMC020_BANK_SIZE_32M 0x5 -#define FTSDMC020_BANK_SIZE_64M 0x6 -#define FTSDMC020_BANK_SIZE_128M 0x7 -#define FTSDMC020_BANK_SIZE_256M 0x8 - -/* - * Arbiter Control Register - */ -#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f) -#define FTSDMC020_ACR_TOE (1 << 8) - -#endif /* __FTSDMC020_H */ diff --git a/include/asm-arm/arch-a320/ftsmc020.h b/include/asm-arm/arch-a320/ftsmc020.h deleted file mode 100644 index 95d9500..0000000 --- a/include/asm-arm/arch-a320/ftsmc020.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -/* - * Static Memory Controller - */ -#ifndef __FTSMC020_H -#define __FTSMC020_H - -#ifndef __ASSEMBLY__ - -struct ftsmc020 { - struct { - unsigned int cr; /* 0x00, 0x08, 0x10, 0x18 */ - unsigned int tpr; /* 0x04, 0x0c, 0x14, 0x1c */ - } bank[4]; - unsigned int pad[8]; /* 0x20 - 0x3c */ - unsigned int ssr; /* 0x40 */ -}; - -void ftsmc020_init(void); - -#endif /* __ASSEMBLY__ */ - -/* - * Memory Bank Configuration Register - */ -#define FTSMC020_BANK_ENABLE (1 << 28) -#define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000) - -#define FTSMC020_BANK_WPROT (1 << 11) - -#define FTSMC020_BANK_SIZE_32K (0xb << 4) -#define FTSMC020_BANK_SIZE_64K (0xc << 4) -#define FTSMC020_BANK_SIZE_128K (0xd << 4) -#define FTSMC020_BANK_SIZE_256K (0xe << 4) -#define FTSMC020_BANK_SIZE_512K (0xf << 4) -#define FTSMC020_BANK_SIZE_1M (0x0 << 4) -#define FTSMC020_BANK_SIZE_2M (0x1 << 4) -#define FTSMC020_BANK_SIZE_4M (0x2 << 4) -#define FTSMC020_BANK_SIZE_8M (0x3 << 4) -#define FTSMC020_BANK_SIZE_16M (0x4 << 4) -#define FTSMC020_BANK_SIZE_32M (0x5 << 4) - -#define FTSMC020_BANK_MBW_8 (0x0 << 0) -#define FTSMC020_BANK_MBW_16 (0x1 << 0) -#define FTSMC020_BANK_MBW_32 (0x2 << 0) - -/* - * Memory Bank Timing Parameter Register - */ -#define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28) -#define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24) -#define FTSMC020_TPR_RBE (1 << 20) -#define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18) -#define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16) -#define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12) -#define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8) -#define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6) -#define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4) -#define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0) - -#endif /* __FTSMC020_H */ diff --git a/include/asm-arm/arch-a320/fttmr010.h b/include/asm-arm/arch-a320/fttmr010.h deleted file mode 100644 index 72abcb3..0000000 --- a/include/asm-arm/arch-a320/fttmr010.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -/* - * Timer - */ -#ifndef __FTTMR010_H -#define __FTTMR010_H - -struct fttmr010 { - unsigned int timer1_counter; /* 0x00 */ - unsigned int timer1_load; /* 0x04 */ - unsigned int timer1_match1; /* 0x08 */ - unsigned int timer1_match2; /* 0x0c */ - unsigned int timer2_counter; /* 0x10 */ - unsigned int timer2_load; /* 0x14 */ - unsigned int timer2_match1; /* 0x18 */ - unsigned int timer2_match2; /* 0x1c */ - unsigned int timer3_counter; /* 0x20 */ - unsigned int timer3_load; /* 0x24 */ - unsigned int timer3_match1; /* 0x28 */ - unsigned int timer3_match2; /* 0x2c */ - unsigned int cr; /* 0x30 */ - unsigned int interrupt_state; /* 0x34 */ - unsigned int interrupt_mask; /* 0x38 */ -}; - -/* - * Timer Control Register - */ -#define FTTMR010_TM3_UPDOWN (1 << 11) -#define FTTMR010_TM2_UPDOWN (1 << 10) -#define FTTMR010_TM1_UPDOWN (1 << 9) -#define FTTMR010_TM3_OFENABLE (1 << 8) -#define FTTMR010_TM3_CLOCK (1 << 7) -#define FTTMR010_TM3_ENABLE (1 << 6) -#define FTTMR010_TM2_OFENABLE (1 << 5) -#define FTTMR010_TM2_CLOCK (1 << 4) -#define FTTMR010_TM2_ENABLE (1 << 3) -#define FTTMR010_TM1_OFENABLE (1 << 2) -#define FTTMR010_TM1_CLOCK (1 << 1) -#define FTTMR010_TM1_ENABLE (1 << 0) - -/* - * Timer Interrupt State & Mask Registers - */ -#define FTTMR010_TM3_OVERFLOW (1 << 8) -#define FTTMR010_TM3_MATCH2 (1 << 7) -#define FTTMR010_TM3_MATCH1 (1 << 6) -#define FTTMR010_TM2_OVERFLOW (1 << 5) -#define FTTMR010_TM2_MATCH2 (1 << 4) -#define FTTMR010_TM2_MATCH1 (1 << 3) -#define FTTMR010_TM1_OVERFLOW (1 << 2) -#define FTTMR010_TM1_MATCH2 (1 << 1) -#define FTTMR010_TM1_MATCH1 (1 << 0) - -#endif /* __FTTMR010_H */ |