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-rw-r--r--drivers/gpio/Makefile2
-rw-r--r--drivers/gpio/mxc_gpio.c (renamed from drivers/gpio/mx31_gpio.c)47
-rw-r--r--drivers/hwmon/ds1621.c253
-rw-r--r--drivers/misc/fsl_pmic.c10
-rw-r--r--drivers/mtd/spi/spansion.c16
-rw-r--r--drivers/mtd/spi/winbond.c9
-rw-r--r--drivers/serial/serial_mxc.c7
-rw-r--r--drivers/spi/mxc_spi.c168
8 files changed, 313 insertions, 199 deletions
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 07d395d..a0f4552 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -27,7 +27,7 @@ LIB := $(obj)libgpio.a
COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o
COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
-COBJS-$(CONFIG_MX31_GPIO) += mx31_gpio.o
+COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o
COBJS-$(CONFIG_PCA953X) += pca953x.o
COBJS-$(CONFIG_S5P) += s5p_gpio.o
diff --git a/drivers/gpio/mx31_gpio.c b/drivers/gpio/mxc_gpio.c
index b07f038..663141f 100644
--- a/drivers/gpio/mx31_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -21,19 +21,29 @@
* MA 02111-1307 USA
*/
#include <common.h>
-#include <asm/arch/mx31.h>
+#ifdef CONFIG_MX31
#include <asm/arch/mx31-regs.h>
+#endif
+#ifdef CONFIG_MX51
+#include <asm/arch/imx-regs.h>
+#endif
+#include <asm/io.h>
+#include <mxc_gpio.h>
/* GPIO port description */
static unsigned long gpio_ports[] = {
- [0] = GPIO1_BASE,
- [1] = GPIO2_BASE,
- [2] = GPIO3_BASE,
+ [0] = GPIO1_BASE_ADDR,
+ [1] = GPIO2_BASE_ADDR,
+ [2] = GPIO3_BASE_ADDR,
+#ifdef CONFIG_MX51
+ [3] = GPIO4_BASE_ADDR,
+#endif
};
-int mx31_gpio_direction(unsigned int gpio, enum mx31_gpio_direction direction)
+int mxc_gpio_direction(unsigned int gpio, enum mxc_gpio_direction direction)
{
unsigned int port = gpio >> 5;
+ struct gpio_regs *regs;
u32 l;
if (port >= ARRAY_SIZE(gpio_ports))
@@ -41,22 +51,26 @@ int mx31_gpio_direction(unsigned int gpio, enum mx31_gpio_direction direction)
gpio &= 0x1f;
- l = __REG(gpio_ports[port] + GPIO_GDIR);
+ regs = (struct gpio_regs *)gpio_ports[port];
+
+ l = readl(&regs->gpio_dir);
+
switch (direction) {
- case MX31_GPIO_DIRECTION_OUT:
+ case MXC_GPIO_DIRECTION_OUT:
l |= 1 << gpio;
break;
- case MX31_GPIO_DIRECTION_IN:
+ case MXC_GPIO_DIRECTION_IN:
l &= ~(1 << gpio);
}
- __REG(gpio_ports[port] + GPIO_GDIR) = l;
+ writel(l, &regs->gpio_dir);
return 0;
}
-void mx31_gpio_set(unsigned int gpio, unsigned int value)
+void mxc_gpio_set(unsigned int gpio, unsigned int value)
{
unsigned int port = gpio >> 5;
+ struct gpio_regs *regs;
u32 l;
if (port >= ARRAY_SIZE(gpio_ports))
@@ -64,17 +78,20 @@ void mx31_gpio_set(unsigned int gpio, unsigned int value)
gpio &= 0x1f;
- l = __REG(gpio_ports[port] + GPIO_DR);
+ regs = (struct gpio_regs *)gpio_ports[port];
+
+ l = readl(&regs->gpio_dr);
if (value)
l |= 1 << gpio;
else
l &= ~(1 << gpio);
- __REG(gpio_ports[port] + GPIO_DR) = l;
+ writel(l, &regs->gpio_dr);
}
-int mx31_gpio_get(unsigned int gpio)
+int mxc_gpio_get(unsigned int gpio)
{
unsigned int port = gpio >> 5;
+ struct gpio_regs *regs;
u32 l;
if (port >= ARRAY_SIZE(gpio_ports))
@@ -82,7 +99,9 @@ int mx31_gpio_get(unsigned int gpio)
gpio &= 0x1f;
- l = (__REG(gpio_ports[port] + GPIO_DR) >> gpio) & 0x01;
+ regs = (struct gpio_regs *)gpio_ports[port];
+
+ l = (readl(&regs->gpio_dr) >> gpio) & 0x01;
return l;
}
diff --git a/drivers/hwmon/ds1621.c b/drivers/hwmon/ds1621.c
index d15a082..5a2ea62 100644
--- a/drivers/hwmon/ds1621.c
+++ b/drivers/hwmon/ds1621.c
@@ -22,7 +22,7 @@
*/
/*
- * Dallas Semiconductor's DS1621 Digital Thermometer and Thermostat.
+ * Dallas Semiconductor's DS1621/1631 Digital Thermometer and Thermostat.
*/
#include <common.h>
@@ -32,7 +32,7 @@
/*
* Device code
*/
-#define DTT_I2C_DEV_CODE 0x48 /* Dallas Semi's DS1621 */
+#define DTT_I2C_DEV_CODE 0x48 /* Dallas Semi's DS1621 */
#define DTT_READ_TEMP 0xAA
#define DTT_READ_COUNTER 0xA8
#define DTT_READ_SLOPE 0xA9
@@ -42,148 +42,147 @@
#define DTT_TEMP_LOW 0xA2
#define DTT_CONFIG 0xAC
+/*
+ * Config register bits
+ */
+#define DTT_CONFIG_1SHOT 0x01
+#define DTT_CONFIG_POLARITY 0x02
+#define DTT_CONFIG_R0 0x04 /* ds1631 only */
+#define DTT_CONFIG_R1 0x08 /* ds1631 only */
+#define DTT_CONFIG_NVB 0x10
+#define DTT_CONFIG_TLF 0x20
+#define DTT_CONFIG_THF 0x40
+#define DTT_CONFIG_DONE 0x80
+
+
int dtt_read(int sensor, int reg)
{
- int dlen;
- uchar data[2];
-
- /*
- * Calculate sensor address and command.
- *
- */
- sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* Calculate addr of ds1621*/
-
- /*
- * Prepare to handle 2 byte result.
- */
- if ((reg == DTT_READ_TEMP) ||
- (reg == DTT_TEMP_HIGH) || (reg == DTT_TEMP_LOW))
- dlen = 2;
- else
- dlen = 1;
-
- /*
- * Now try to read the register.
- */
- if (i2c_read(sensor, reg, 1, data, dlen) != 0)
- return 1;
-
- /*
- * Handle 2 byte result.
- */
- if (dlen == 2)
- return ((int)((short)data[1] + (((short)data[0]) << 8)));
-
- return (int)data[0];
-} /* dtt_read() */
+ int dlen;
+ uchar data[2];
+
+ /* Calculate sensor address and command */
+ sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* Calculate addr of ds1621*/
+
+ /* Prepare to handle 2 byte result */
+ switch(reg) {
+ case DTT_READ_TEMP:
+ case DTT_TEMP_HIGH:
+ case DTT_TEMP_LOW:
+ dlen = 2;
+ break;
+ default:
+ dlen = 1;
+ }
+
+ /* Now try to read the register */
+ if (i2c_read(sensor, reg, 1, data, dlen) != 0)
+ return 1;
+
+ /* Handle 2 byte result */
+ if (dlen == 2)
+ return (short)((data[0] << 8) | data[1]);
+
+ return (int)data[0];
+}
int dtt_write(int sensor, int reg, int val)
{
- int dlen;
- uchar data[2];
-
- /*
- * Calculate sensor address and register.
- *
- */
- sensor = DTT_I2C_DEV_CODE + (sensor & 0x07);
-
- /*
- * Handle various data sizes.
- */
- if ((reg == DTT_READ_TEMP) ||
- (reg == DTT_TEMP_HIGH) || (reg == DTT_TEMP_LOW)) {
- dlen = 2;
- data[0] = (char)((val >> 8) & 0xff); /* MSB first */
- data[1] = (char)(val & 0xff);
- }
- else if ((reg == DTT_WRITE_START_CONV) || (reg == DTT_WRITE_STOP_CONV)) {
- dlen = 0;
- data[0] = (char)0;
- data[1] = (char)0;
- }
- else {
- dlen = 1;
- data[0] = (char)(val & 0xff);
- }
-
- /*
- * Write value to device.
- */
- if (i2c_write(sensor, reg, 1, data, dlen) != 0)
- return 1;
-
- return 0;
-} /* dtt_write() */
+ int dlen;
+ uchar data[2];
+
+ /* Calculate sensor address and register */
+ sensor = DTT_I2C_DEV_CODE + (sensor & 0x07);
+
+ /* Handle various data sizes. */
+ switch(reg) {
+ case DTT_READ_TEMP:
+ case DTT_TEMP_HIGH:
+ case DTT_TEMP_LOW:
+ dlen = 2;
+ data[0] = (char)((val >> 8) & 0xff); /* MSB first */
+ data[1] = (char)(val & 0xff);
+ break;
+ case DTT_WRITE_START_CONV:
+ case DTT_WRITE_STOP_CONV:
+ dlen = 0;
+ data[0] = (char)0;
+ data[1] = (char)0;
+ break;
+ default:
+ dlen = 1;
+ data[0] = (char)(val & 0xff);
+ }
+
+ /* Write value to device */
+ if (i2c_write(sensor, reg, 1, data, dlen) != 0)
+ return 1;
+
+ /* Poll NV memory busy bit in case write was to register stored in EEPROM */
+ while(i2c_reg_read(sensor, DTT_CONFIG) & DTT_CONFIG_NVB)
+ ;
+
+ return 0;
+}
static int _dtt_init(int sensor)
{
- int val;
-
- /*
- * Setup High Temp.
- */
- val = ((CONFIG_SYS_DTT_MAX_TEMP * 2) << 7) & 0xff80;
- if (dtt_write(sensor, DTT_TEMP_HIGH, val) != 0)
- return 1;
- udelay(50000); /* Max 50ms */
-
- /*
- * Setup Low Temp - hysteresis.
- */
- val = (((CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS) * 2) << 7) & 0xff80;
- if (dtt_write(sensor, DTT_TEMP_LOW, val) != 0)
- return 1;
- udelay(50000); /* Max 50ms */
-
- /*
- * Setup configuraton register
- *
- * Clear THF & TLF, Reserved = 1, Polarity = Active Low, One Shot = YES
- *
- * We run in polled mode, since there isn't any way to know if this
- * lousy device is ready to provide temperature readings on power up.
- */
- val = 0x9;
- if (dtt_write(sensor, DTT_CONFIG, val) != 0)
- return 1;
- udelay(50000); /* Max 50ms */
-
- return 0;
-} /* _dtt_init() */
+ int val;
+
+ /* Setup High Temp */
+ val = ((CONFIG_SYS_DTT_MAX_TEMP * 2) << 7) & 0xff80;
+ if (dtt_write(sensor, DTT_TEMP_HIGH, val) != 0)
+ return 1;
+
+ /* Setup Low Temp - hysteresis */
+ val = (((CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS) * 2) << 7) & 0xff80;
+ if (dtt_write(sensor, DTT_TEMP_LOW, val) != 0)
+ return 1;
+
+ /*
+ * Setup configuraton register
+ *
+ * Clear THF & TLF, Reserved = 1, Polarity = Active Low, One Shot = YES
+ *
+ * We run in polled mode, since there isn't any way to know if this
+ * lousy device is ready to provide temperature readings on power up.
+ */
+ val = 0x9;
+ if (dtt_write(sensor, DTT_CONFIG, val) != 0)
+ return 1;
+
+ return 0;
+}
int dtt_init (void)
{
- int i;
- unsigned char sensors[] = CONFIG_DTT_SENSORS;
+ int i;
+ unsigned char sensors[] = CONFIG_DTT_SENSORS;
- for (i = 0; i < sizeof(sensors); i++) {
- if (_dtt_init(sensors[i]) != 0)
- printf("DTT%d: FAILED\n", i+1);
- else
- printf("DTT%d: %i C\n", i+1, dtt_get_temp(sensors[i]));
- }
+ for (i = 0; i < sizeof(sensors); i++) {
+ if (_dtt_init(sensors[i]) != 0)
+ printf("DTT%d: FAILED\n", i + 1);
+ else
+ printf("DTT%d: %i C\n", i + 1, dtt_get_temp(sensors[i]));
+ }
- return (0);
-} /* dtt_init() */
+ return (0);
+}
int dtt_get_temp(int sensor)
{
- int i;
-
- /*
- * Start a conversion, may take up to 1 second.
- */
- dtt_write(sensor, DTT_WRITE_START_CONV, 0);
- for (i = 0; i <= 10; i++) {
- udelay(100000);
- if (dtt_read(sensor, DTT_CONFIG) & 0x80)
- break;
- }
-
- return (dtt_read(sensor, DTT_READ_TEMP) / 256);
-} /* dtt_get_temp() */
+ int i;
+
+ /* Start a conversion, may take up to 1 second. */
+ dtt_write(sensor, DTT_WRITE_START_CONV, 0);
+ for (i = 0; i <= 10; i++) {
+ udelay(100000);
+ if (dtt_read(sensor, DTT_CONFIG) & DTT_CONFIG_DONE)
+ break;
+ }
+
+ return (dtt_read(sensor, DTT_READ_TEMP) / 256);
+}
diff --git a/drivers/misc/fsl_pmic.c b/drivers/misc/fsl_pmic.c
index dca0a1d..5ee1de1 100644
--- a/drivers/misc/fsl_pmic.c
+++ b/drivers/misc/fsl_pmic.c
@@ -46,6 +46,7 @@ void pmic_spi_free(struct spi_slave *slave)
u32 pmic_reg(u32 reg, u32 val, u32 write)
{
u32 pmic_tx, pmic_rx;
+ u32 tmp;
if (!slave) {
slave = pmic_spi_probe();
@@ -65,7 +66,9 @@ u32 pmic_reg(u32 reg, u32 val, u32 write)
pmic_tx = (write << 31) | (reg << 25) | (val & 0x00FFFFFF);
- if (spi_xfer(slave, 4 << 3, &pmic_tx, &pmic_rx,
+ tmp = cpu_to_be32(pmic_tx);
+
+ if (spi_xfer(slave, 4 << 3, &tmp, &pmic_rx,
SPI_XFER_BEGIN | SPI_XFER_END)) {
spi_release_bus(slave);
return -1;
@@ -73,7 +76,8 @@ u32 pmic_reg(u32 reg, u32 val, u32 write)
if (write) {
pmic_tx &= ~(1 << 31);
- if (spi_xfer(slave, 4 << 3, &pmic_tx, &pmic_rx,
+ tmp = cpu_to_be32(pmic_tx);
+ if (spi_xfer(slave, 4 << 3, &tmp, &pmic_rx,
SPI_XFER_BEGIN | SPI_XFER_END)) {
spi_release_bus(slave);
return -1;
@@ -81,7 +85,7 @@ u32 pmic_reg(u32 reg, u32 val, u32 write)
}
spi_release_bus(slave);
- return pmic_rx;
+ return cpu_to_be32(pmic_rx);
}
void pmic_reg_write(u32 reg, u32 value)
diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c
index d6c1a5f..c0900f9 100644
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
@@ -52,6 +52,7 @@
#define SPSN_ID_S25FL128P 0x2018
#define SPSN_EXT_ID_S25FL128P_256KB 0x0300
#define SPSN_EXT_ID_S25FL128P_64KB 0x0301
+#define SPSN_EXT_ID_S25FL032P 0x4d00
#define SPANSION_SR_WIP (1 << 0) /* Write-in-Progress */
@@ -124,6 +125,14 @@ static const struct spansion_spi_flash_params spansion_spi_flash_table[] = {
.nr_sectors = 64,
.name = "S25FL128P_256K",
},
+ {
+ .idcode1 = SPSN_ID_S25FL032A,
+ .idcode2 = SPSN_EXT_ID_S25FL032P,
+ .page_size = 256,
+ .pages_per_sector = 256,
+ .nr_sectors = 64,
+ .name = "S25FL032P",
+ },
};
static int spansion_wait_ready(struct spi_flash *flash, unsigned long timeout)
@@ -262,7 +271,6 @@ int spansion_erase(struct spi_flash *flash, u32 offset, size_t len)
return -1;
}
- len /= sector_size;
cmd[0] = CMD_S25FLXX_SE;
cmd[2] = 0x00;
cmd[3] = 0x00;
@@ -274,8 +282,8 @@ int spansion_erase(struct spi_flash *flash, u32 offset, size_t len)
}
ret = 0;
- for (actual = 0; actual < len; actual++) {
- cmd[1] = (offset / sector_size) + actual;
+ for (actual = 0; actual < len; actual += sector_size) {
+ cmd[1] = (offset + actual) >> 16;
ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0);
if (ret < 0) {
@@ -298,7 +306,7 @@ int spansion_erase(struct spi_flash *flash, u32 offset, size_t len)
}
debug("SF: SPANSION: Successfully erased %u bytes @ 0x%x\n",
- len * sector_size, offset);
+ len, offset);
spi_release_bus(flash->spi);
return ret;
diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c
index ff1df25..de3aeb8 100644
--- a/drivers/mtd/spi/winbond.c
+++ b/drivers/mtd/spi/winbond.c
@@ -27,6 +27,7 @@
#define WINBOND_ID_W25X16 0x3015
#define WINBOND_ID_W25X32 0x3016
#define WINBOND_ID_W25X64 0x3017
+#define WINBOND_ID_W25Q64 0x4017
#define WINBOND_SR_WIP (1 << 0) /* Write-in-Progress */
@@ -77,6 +78,14 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
.nr_blocks = 128,
.name = "W25X64",
},
+ {
+ .id = WINBOND_ID_W25Q64,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 128,
+ .name = "W25Q64",
+ },
};
static int winbond_wait_ready(struct spi_flash *flash, unsigned long timeout)
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 4b93e7b..f96b21f 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -18,6 +18,7 @@
*/
#include <common.h>
+#include <watchdog.h>
#ifdef CONFIG_MX31
#include <asm/arch/mx31.h>
#else
@@ -189,7 +190,8 @@ void serial_setbrg (void)
int serial_getc (void)
{
- while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY);
+ while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
+ WATCHDOG_RESET();
return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */
}
@@ -198,7 +200,8 @@ void serial_putc (const char c)
__REG(UART_PHYS + UTXD) = c;
/* wait for transmitter to be ready */
- while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY));
+ while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
+ WATCHDOG_RESET();
/* If \n, also do \r */
if (c == '\n')
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index e15a63c..d558137 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -23,6 +23,7 @@
#include <spi.h>
#include <asm/errno.h>
#include <asm/io.h>
+#include <mxc_gpio.h>
#ifdef CONFIG_MX27
/* i.MX27 has a completely wrong register layout and register definitions in the
@@ -61,6 +62,7 @@
#define MXC_CSPICTRL_MAXBITS 0x1f
#define MXC_CSPIPERIOD_32KHZ (1 << 15)
+#define MAX_SPI_BYTES 4
static unsigned long spi_bases[] = {
0x43fa4000,
@@ -68,9 +70,6 @@ static unsigned long spi_bases[] = {
0x53f84000,
};
-#define OUT MX31_GPIO_DIRECTION_OUT
-#define mxc_gpio_direction mx31_gpio_direction
-#define mxc_gpio_set mx31_gpio_set
#elif defined(CONFIG_MX51)
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
@@ -97,6 +96,7 @@ static unsigned long spi_bases[] = {
#define MXC_CSPICTRL_RXOVF (1 << 6)
#define MXC_CSPIPERIOD_32KHZ (1 << 15)
+#define MAX_SPI_BYTES 32
/* Bit position inside CTRL register to be associated with SS */
#define MXC_CSPICTRL_CHAN 18
@@ -111,13 +111,12 @@ static unsigned long spi_bases[] = {
CSPI2_BASE_ADDR,
CSPI3_BASE_ADDR,
};
-#define mxc_gpio_direction(gpio, dir) (0)
-#define mxc_gpio_set(gpio, value) {}
-#define OUT 1
#else
#error "Unsupported architecture"
#endif
+#define OUT MXC_GPIO_DIRECTION_OUT
+
struct mxc_spi_slave {
struct spi_slave slave;
unsigned long base;
@@ -126,6 +125,7 @@ struct mxc_spi_slave {
u32 cfg_reg;
#endif
int gpio;
+ int ss_pol;
};
static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
@@ -147,7 +147,7 @@ void spi_cs_activate(struct spi_slave *slave)
{
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
if (mxcs->gpio > 0)
- mxc_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL);
+ mxc_gpio_set(mxcs->gpio, mxcs->ss_pol);
}
void spi_cs_deactivate(struct spi_slave *slave)
@@ -155,7 +155,7 @@ void spi_cs_deactivate(struct spi_slave *slave)
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
if (mxcs->gpio > 0)
mxc_gpio_set(mxcs->gpio,
- !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
+ !(mxcs->ss_pol));
}
#ifdef CONFIG_MX51
@@ -217,7 +217,7 @@ static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs,
if (mode & SPI_CS_HIGH)
ss_pol = 1;
- if (!(mode & SPI_CPOL))
+ if (mode & SPI_CPOL)
sclkpol = 1;
if (mode & SPI_CPHA)
@@ -254,13 +254,15 @@ static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs,
}
#endif
-static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen,
- unsigned long flags)
+int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
+ const u8 *dout, u8 *din, unsigned long flags)
{
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
+ int nbytes = (bitlen + 7) / 8;
+ u32 data, cnt, i;
- if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
+ debug("%s: bitlen %d dout 0x%x din 0x%x\n",
+ __func__, bitlen, (u32)dout, (u32)din);
mxcs->ctrl_reg = (mxcs->ctrl_reg &
~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
@@ -275,8 +277,46 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen,
reg_write(mxcs->base + MXC_CSPISTAT,
MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
- debug("Sending SPI 0x%x\n", data);
- reg_write(mxcs->base + MXC_CSPITXDATA, data);
+ /*
+ * The SPI controller works only with words,
+ * check if less than a word is sent.
+ * Access to the FIFO is only 32 bit
+ */
+ if (bitlen % 32) {
+ data = 0;
+ cnt = (bitlen % 32) / 8;
+ if (dout) {
+ for (i = 0; i < cnt; i++) {
+ data = (data << 8) | (*dout++ & 0xFF);
+ }
+ }
+ debug("Sending SPI 0x%x\n", data);
+
+ reg_write(mxcs->base + MXC_CSPITXDATA, data);
+ nbytes -= cnt;
+ }
+
+ data = 0;
+
+ while (nbytes > 0) {
+ data = 0;
+ if (dout) {
+ /* Buffer is not 32-bit aligned */
+ if ((unsigned long)dout & 0x03) {
+ data = 0;
+ for (i = 0; i < 4; i++, data <<= 8) {
+ data = (data << 8) | (*dout++ & 0xFF);
+ }
+ } else {
+ data = *(u32 *)dout;
+ data = cpu_to_be32(data);
+ }
+ dout += 4;
+ }
+ debug("Sending SPI 0x%x\n", data);
+ reg_write(mxcs->base + MXC_CSPITXDATA, data);
+ nbytes -= 4;
+ }
/* FIFO is written, now starts the transfer setting the XCH bit */
reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg |
@@ -290,49 +330,78 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen,
reg_write(mxcs->base + MXC_CSPISTAT,
MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
- data = reg_read(mxcs->base + MXC_CSPIRXDATA);
- debug("SPI Rx: 0x%x\n", data);
+ nbytes = (bitlen + 7) / 8;
- if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
+ cnt = nbytes % 32;
+
+ if (bitlen % 32) {
+ data = reg_read(mxcs->base + MXC_CSPIRXDATA);
+ cnt = (bitlen % 32) / 8;
+ debug("SPI Rx unaligned: 0x%x\n", data);
+ if (din) {
+ for (i = 0; i < cnt; i++, data >>= 8) {
+ *din++ = data & 0xFF;
+ }
+ }
+ nbytes -= cnt;
+ }
- return data;
+ while (nbytes > 0) {
+ u32 tmp;
+ tmp = reg_read(mxcs->base + MXC_CSPIRXDATA);
+ data = cpu_to_be32(tmp);
+ debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
+ cnt = min(nbytes, sizeof(data));
+ if (din) {
+ memcpy(din, &data, cnt);
+ din += cnt;
+ }
+ nbytes -= cnt;
+ }
+
+ return 0;
}
+
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
- int n_blks = (bitlen + 31) / 32;
- u32 *out_l, *in_l;
- int i;
+ int n_bytes = (bitlen + 7) / 8;
+ int n_bits;
+ int ret;
+ u32 blk_size;
+ u8 *p_outbuf = (u8 *)dout;
+ u8 *p_inbuf = (u8 *)din;
- if ((int)dout & 3 || (int)din & 3) {
- printf("Error: unaligned buffers in: %p, out: %p\n", din, dout);
- return 1;
- }
+ if (!slave)
+ return -1;
+
+ if (flags & SPI_XFER_BEGIN)
+ spi_cs_activate(slave);
+
+ while (n_bytes > 0) {
+
+ if (n_bytes < MAX_SPI_BYTES)
+ blk_size = n_bytes;
+ else
+ blk_size = MAX_SPI_BYTES;
+
+ n_bits = blk_size * 8;
- /* This driver is currently partly broken, alert the user */
- if (bitlen > 16 && (bitlen % 32)) {
- printf("Error: SPI transfer with bitlen=%d is broken.\n",
- bitlen);
- return 1;
+ ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0);
+
+ if (ret)
+ return ret;
+ if (dout)
+ p_outbuf += blk_size;
+ if (din)
+ p_inbuf += blk_size;
+ n_bytes -= blk_size;
}
- for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout;
- i < n_blks;
- i++, in_l++, out_l++, bitlen -= 32) {
- u32 data = spi_xchg_single(slave, *out_l, bitlen, flags);
-
- /* Check if we're only transfering 8 or 16 bits */
- if (!i) {
- if (bitlen < 9)
- *(u8 *)din = data;
- else if (bitlen < 17)
- *(u16 *)din = data;
- else
- *in_l = data;
- }
+ if (flags & SPI_XFER_END) {
+ spi_cs_deactivate(slave);
}
return 0;
@@ -380,8 +449,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
return NULL;
mxcs = malloc(sizeof(struct mxc_spi_slave));
- if (!mxcs)
+ if (!mxcs) {
+ puts("mxc_spi: SPI Slave not allocated !\n");
return NULL;
+ }
ret = decode_cs(mxcs, cs);
if (ret < 0) {
@@ -394,6 +465,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
mxcs->slave.bus = bus;
mxcs->slave.cs = cs;
mxcs->base = spi_bases[bus];
+ mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
#ifdef CONFIG_MX51
/* Can be used for i.MX31 too ? */
@@ -413,7 +485,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
if (mode & SPI_CPHA)
ctrl_reg |= MXC_CSPICTRL_PHA;
- if (!(mode & SPI_CPOL))
+ if (mode & SPI_CPOL)
ctrl_reg |= MXC_CSPICTRL_POL;
if (mode & SPI_CS_HIGH)
ctrl_reg |= MXC_CSPICTRL_SSPOL;
generated by cgit v1.1 at 2024-07-20 03:25:11 +0000