16 files changed, 257 insertions, 70 deletions

diff --git a/drivers/dma/keystone_nav.c b/drivers/dma/keystone_nav.c
index 77707c2..dfca75a 100644
--- a/drivers/dma/keystone_nav.c
+++ b/drivers/dma/keystone_nav.c
@@ -81,9 +81,6 @@ void qm_close(void)
 {
 	u32	j;
 
-	if (qm_cfg == NULL)
-		return;
-
 	queue_close(qm_cfg->qpool_num);
 
 	qm_cfg->mngr_cfg->link_ram_base0	= 0;
@@ -105,9 +102,6 @@ void qm_push(struct qm_host_desc *hd, u32 qnum)
 {
 	u32 regd;
 
-	if (!qm_cfg)
-		return;
-
 	cpu_to_bus((u32 *)hd, sizeof(struct qm_host_desc)/4);
 	regd = (u32)hd | ((sizeof(struct qm_host_desc) >> 4) - 1);
 	writel(regd, &qm_cfg->queue[qnum].ptr_size_thresh);
@@ -127,9 +121,6 @@ struct qm_host_desc *qm_pop(u32 qnum)
 {
 	u32 uhd;
 
-	if (!qm_cfg)
-		return NULL;
-
 	uhd = readl(&qm_cfg->queue[qnum].ptr_size_thresh) & ~0xf;
 	if (uhd)
 		cpu_to_bus((u32 *)uhd, sizeof(struct qm_host_desc)/4);
@@ -139,9 +130,6 @@ struct qm_host_desc *qm_pop(u32 qnum)
 
 struct qm_host_desc *qm_pop_from_free_pool(void)
 {
-	if (!qm_cfg)
-		return NULL;
-
 	return qm_pop(qm_cfg->qpool_num);
 }
 
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 811033b..7bb1702 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -38,7 +38,7 @@
  * generic value.
  */
 #ifndef CONFIG_I2C_TIMEOUT
-#define CONFIG_I2C_TIMEOUT	10000
+#define CONFIG_I2C_TIMEOUT	100000
 #endif
 
 #define I2C_READ_BIT  1
diff --git a/drivers/i2c/ppc4xx_i2c.c b/drivers/i2c/ppc4xx_i2c.c
index e7a15ba..df88885 100644
--- a/drivers/i2c/ppc4xx_i2c.c
+++ b/drivers/i2c/ppc4xx_i2c.c
@@ -158,8 +158,7 @@ static void ppc4xx_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
  *
  * Typical case is a Write of an addr followd by a Read. The
  * IBM FAQ does not cover this. On the last byte of the write
- * we don't set the creg CHT bit, and on the first bytes of the
- * read we set the RPST bit.
+ * we don't set the creg CHT bit but the RPST bit.
  *
  * It does not support address only transfers, there must be
  * a data part. If you want to write the address yourself, put
@@ -247,6 +246,10 @@ static int _i2c_transfer(struct i2c_adapter *adap,
 		if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt))
 			creg |= IIC_CNTL_CHT;
 
+		/* last part of address, prepare for repeated start on read */
+		if (cmd_type && (ptr == addr) && ((tran + bc) == cnt))
+			creg |= IIC_CNTL_RPST;
+
 		if (reading) {
 			creg |= IIC_CNTL_READ;
 		} else {
@@ -286,6 +289,27 @@ static int _i2c_transfer(struct i2c_adapter *adap,
 			/* Transfer aborted? */
 			if (status & IIC_EXTSTS_XFRA)
 				result = IIC_NOK_XFRA;
+			/* Is bus free?
+			 * If error happened during combined xfer
+			 * IIC interface is usually stuck in some strange
+			 * state without a valid stop condition.
+			 * Brute, but working: generate stop, then soft reset.
+			 */
+			if ((status & IIC_EXTSTS_BCS_MASK)
+			    != IIC_EXTSTS_BCS_FREE){
+				u8 mdcntl = in_8(&i2c->mdcntl);
+
+				/* Generate valid stop condition */
+				out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST);
+				out_8(&i2c->directcntl, IIC_DIRCNTL_SCC);
+				udelay(10);
+				out_8(&i2c->directcntl,
+				      IIC_DIRCNTL_SCC | IIC_DIRCNTL_SDAC);
+				out_8(&i2c->xtcntlss, 0);
+
+				ppc4xx_i2c_init(adap, (mdcntl & IIC_MDCNTL_FSM)
+						? 400000 : 100000, 0);
+			}
 		} else if ( status & IIC_STS_PT) {
 			result = IIC_NOK_TOUT;
 		}
@@ -314,8 +338,6 @@ static int _i2c_transfer(struct i2c_adapter *adap,
 			cnt = data_len;
 			tran = 0;
 			reading = cmd_type;
-			if (reading)
-				creg = IIC_CNTL_RPST;
 		}
 	}
 	return result;
diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c
index 50cebd6..90ad116 100644
--- a/drivers/i2c/rcar_i2c.c
+++ b/drivers/i2c/rcar_i2c.c
@@ -119,10 +119,10 @@ rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr)
 
 	/* set slave address, receive */
 	writel((chip << 1) | 1, &dev->icmar);
-	/* clear status */
-	writel(0, &dev->icmsr);
 	/* start master receive */
 	writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr);
+	/* clear status */
+	writel(0, &dev->icmsr);
 
 	while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDR))
 		!= (MSR_MAT | MSR_MDR))
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 464cee1..461d7d8 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -5,37 +5,39 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
+obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o
 obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o
 obj-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
+obj-$(CONFIG_DWMMC) += dw_mmc.o
+obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
 obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
 obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
 obj-$(CONFIG_FTSDC021) += ftsdc021_sdhci.o
 obj-$(CONFIG_GENERIC_MMC) += mmc.o
 obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
+obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o
 obj-$(CONFIG_MMC_SPI) += mmc_spi.o
-obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
+obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
 obj-$(CONFIG_MV_SDHCI) += mv_sdhci.o
+obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o
 obj-$(CONFIG_MXC_MMC) += mxcmmc.o
 obj-$(CONFIG_MXS_MMC) += mxsmmc.o
 obj-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o
 obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
-obj-$(CONFIG_SDHCI) += sdhci.o
-obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o
-obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o
+obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
 obj-$(CONFIG_S3C_SDI) += s3c_sdi.o
 obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
+obj-$(CONFIG_SDHCI) += sdhci.o
 obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
+obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o
 obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
 obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
-obj-$(CONFIG_DWMMC) += dw_mmc.o
-obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
-obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
 obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
-obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o
-obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
+
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
 else
 obj-$(CONFIG_GENERIC_MMC) += mmc_write.o
 endif
-obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o
+
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index ef2cbf9..ffb5284 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -611,7 +611,8 @@ static int omap_hsmmc_getcd(struct mmc *mmc)
 	if (cd_gpio < 0)
 		return 1;
 
-	return gpio_get_value(cd_gpio);
+	/* NOTE: assumes card detect signal is active-low */
+	return !gpio_get_value(cd_gpio);
 }
 
 static int omap_hsmmc_getwp(struct mmc *mmc)
@@ -624,6 +625,7 @@ static int omap_hsmmc_getwp(struct mmc *mmc)
 	if (wp_gpio < 0)
 		return 0;
 
+	/* NOTE: assumes write protect signal is active-high */
 	return gpio_get_value(wp_gpio);
 }
 #endif
diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c
index c8681d0..bedab1d 100644
--- a/drivers/net/keystone_net.c
+++ b/drivers/net/keystone_net.c
@@ -315,7 +315,7 @@ int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
 	writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
 	writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
 
-#ifdef CONFIG_K2E_EVM
+#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
 	/* Map RX packet flow priority to 0 */
 	writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
 #endif
@@ -400,6 +400,9 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
 
 	keystone2_net_serdes_setup();
 
+	if (sys_has_mdio)
+		keystone2_mdio_reset(mdio_bus);
+
 	keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1,
 			      eth_priv->sgmii_link_type);
 
@@ -582,7 +585,7 @@ static void keystone2_net_serdes_setup(void)
 			&ks2_serdes_sgmii_156p25mhz,
 			CONFIG_KSNET_SERDES_LANES_PER_SGMII);
 
-#ifdef CONFIG_SOC_K2E
+#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
 	ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
 			&ks2_serdes_sgmii_156p25mhz,
 			CONFIG_KSNET_SERDES_LANES_PER_SGMII);
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index d2ecadc..9437c3b 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -276,6 +276,57 @@ static int m88e1111s_config(struct phy_device *phydev)
 	return 0;
 }
 
+/**
+ * m88e1518_phy_writebits - write bits to a register
+ */
+void m88e1518_phy_writebits(struct phy_device *phydev,
+		   u8 reg_num, u16 offset, u16 len, u16 data)
+{
+	u16 reg, mask;
+
+	if ((len + offset) >= 16)
+		mask = 0 - (1 << offset);
+	else
+		mask = (1 << (len + offset)) - (1 << offset);
+
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num);
+
+	reg &= ~mask;
+	reg |= data << offset;
+
+	phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg);
+}
+
+static int m88e1518_config(struct phy_device *phydev)
+{
+	/*
+	 * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512
+	 * /88E1514 Rev A0, Errata Section 3.1
+	 */
+	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
+		phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff);	/* page 0xff */
+		phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B);
+		phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144);
+		phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28);
+		phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146);
+		phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233);
+		phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D);
+		phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C);
+		phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159);
+		phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);	/* reg page 0 */
+		phy_write(phydev, MDIO_DEVAD_NONE, 22, 18);    /* reg page 18 */
+		/* Write HWCFG_MODE = SGMII to Copper */
+		m88e1518_phy_writebits(phydev, 20, 0, 3, 1);
+
+		/* Phy reset */
+		m88e1518_phy_writebits(phydev, 20, 15, 1, 1);
+		phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);     /* reg page 18 */
+		udelay(100);
+	}
+
+	return m88e1111s_config(phydev);
+}
+
 /* Marvell 88E1118 */
 static int m88e1118_config(struct phy_device *phydev)
 {
@@ -493,7 +544,7 @@ static struct phy_driver M88E1518_driver = {
 	.uid = 0x1410dd1,
 	.mask = 0xffffff0,
 	.features = PHY_GBIT_FEATURES,
-	.config = &m88e1111s_config,
+	.config = &m88e1518_config,
 	.startup = &m88e1011s_startup,
 	.shutdown = &genphy_shutdown,
 };
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index b097c1a..5959672 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -187,6 +187,7 @@ static int smc911x_send(struct eth_device *dev, void *packet, int length)
 static void smc911x_halt(struct eth_device *dev)
 {
 	smc911x_reset(dev);
+	smc911x_handle_mac_address(dev);
 }
 
 static int smc911x_rx(struct eth_device *dev)
diff --git a/drivers/net/uli526x.c b/drivers/net/uli526x.c
index 538f11e..9526faa 100644
--- a/drivers/net/uli526x.c
+++ b/drivers/net/uli526x.c
@@ -548,7 +548,7 @@ static int uli526x_rx_packet(struct eth_device *dev)
 
 	rdes0 = le32_to_cpu(rxptr->rdes0);
 #ifdef RX_DEBUG
-	printf("%s(): rxptr->rdes0=%x:%x\n", __FUNCTION__, rxptr->rdes0);
+	printf("%s(): rxptr->rdes0=%x\n", __FUNCTION__, rxptr->rdes0);
 #endif
 	if (!(rdes0 & 0x80000000)) {	/* packet owner check */
 		if ((rdes0 & 0x300) != 0x300) {
diff --git a/drivers/power/power_spi.c b/drivers/power/power_spi.c
index fb455a0..1e55446 100644
--- a/drivers/power/power_spi.c
+++ b/drivers/power/power_spi.c
@@ -17,27 +17,14 @@
 
 static struct spi_slave *slave;
 
-void pmic_spi_free(struct spi_slave *slave)
-{
-	if (slave)
-		spi_free_slave(slave);
-}
-
-struct spi_slave *pmic_spi_probe(struct pmic *p)
-{
-	return spi_setup_slave(p->bus,
-		p->hw.spi.cs,
-		p->hw.spi.clk,
-		p->hw.spi.mode);
-}
-
 static u32 pmic_reg(struct pmic *p, u32 reg, u32 *val, u32 write)
 {
 	u32 pmic_tx, pmic_rx;
 	u32 tmp;
 
 	if (!slave) {
-		slave = pmic_spi_probe(p);
+		slave = spi_setup_slave(p->bus, p->hw.spi.cs, p->hw.spi.clk,
+					p->hw.spi.mode);
 
 		if (!slave)
 			return -1;
@@ -54,25 +41,25 @@ static u32 pmic_reg(struct pmic *p, u32 reg, u32 *val, u32 write)
 	tmp = cpu_to_be32(pmic_tx);
 
 	if (spi_xfer(slave, pmic_spi_bitlen, &tmp, &pmic_rx,
-			pmic_spi_flags)) {
-		spi_release_bus(slave);
-		return -1;
-	}
+			pmic_spi_flags))
+		goto err;
 
 	if (write) {
 		pmic_tx = p->hw.spi.prepare_tx(reg, val, 0);
 		tmp = cpu_to_be32(pmic_tx);
 		if (spi_xfer(slave, pmic_spi_bitlen, &tmp, &pmic_rx,
-			pmic_spi_flags)) {
-			spi_release_bus(slave);
-			return -1;
-		}
+			pmic_spi_flags))
+			goto err;
 	}
 
 	spi_release_bus(slave);
 	*val = cpu_to_be32(pmic_rx);
 
 	return 0;
+
+err:
+	spi_release_bus(slave);
+	return -1;
 }
 
 int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c
index 3f3d415..6046efb 100644
--- a/drivers/serial/serial_uniphier.c
+++ b/drivers/serial/serial_uniphier.c
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <common.h>
+#include <linux/serial_reg.h>
 #include <asm/io.h>
 #include <asm/errno.h>
 #include <dm/device.h>
@@ -37,17 +37,6 @@ struct uniphier_serial {
 
 #define thr rbr
 
-/*
- * These are the definitions for the Line Control Register
- */
-#define UART_LCR_WLS_8	0x03		/* 8 bit character length */
-
-/*
- * These are the definitions for the Line Status Register
- */
-#define UART_LSR_DR	0x01		/* Data ready */
-#define UART_LSR_THRE	0x20		/* Xmit holding register empty */
-
 struct uniphier_serial_private_data {
 	struct uniphier_serial __iomem *membase;
 };
@@ -62,7 +51,7 @@ static int uniphier_serial_setbrg(struct udevice *dev, int baudrate)
 	const unsigned int mode_x_div = 16;
 	unsigned int divisor;
 
-	writeb(UART_LCR_WLS_8, &port->lcr);
+	writeb(UART_LCR_WLEN8, &port->lcr);
 
 	divisor = DIV_ROUND_CLOSEST(plat->uartclk, mode_x_div * baudrate);
 
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index e69de29..b4a9442 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -0,0 +1,46 @@
+config USB_ARCH_HAS_HCD
+	def_bool y
+
+config USB
+	bool "Support for Host-side USB"
+	depends on USB_ARCH_HAS_HCD
+	---help---
+	  Universal Serial Bus (USB) is a specification for a serial bus
+	  subsystem which offers higher speeds and more features than the
+	  traditional PC serial port.  The bus supplies power to peripherals
+	  and allows for hot swapping.  Up to 127 USB peripherals can be
+	  connected to a single USB host in a tree structure.
+
+	  The USB host is the root of the tree, the peripherals are the
+	  leaves and the inner nodes are special USB devices called hubs.
+	  Most PCs now have USB host ports, used to connect peripherals
+	  such as scanners, keyboards, mice, modems, cameras, disks,
+	  flash memory, network links, and printers to the PC.
+
+	  Say Y here if your computer has a host-side USB port and you want
+	  to use USB devices.  You then need to say Y to at least one of the
+	  Host Controller Driver (HCD) options below.  Choose a USB 1.1
+	  controller, such as "UHCI HCD support" or "OHCI HCD support",
+	  and "EHCI HCD (USB 2.0) support" except for older systems that
+	  do not have USB 2.0 support.  It doesn't normally hurt to select
+	  them all if you are not certain.
+
+	  If your system has a device-side USB port, used in the peripheral
+	  side of the USB protocol, see the "USB Gadget" framework instead.
+
+	  After choosing your HCD, then select drivers for the USB peripherals
+	  you'll be using.  You may want to check out the information provided
+	  in <file:Documentation/usb/> and especially the links given in
+	  <file:Documentation/usb/usb-help.txt>.
+
+if USB
+
+source "drivers/usb/host/Kconfig"
+
+config USB_STORAGE
+	bool "USB Mass Storage support"
+	---help---
+	  Say Y here if you want to connect USB mass storage devices to your
+	  board's USB port.
+
+endif
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
new file mode 100644
index 0000000..30d1457
--- /dev/null
+++ b/drivers/usb/host/Kconfig
@@ -0,0 +1,56 @@
+#
+# USB Host Controller Drivers
+#
+comment "USB Host Controller Drivers"
+
+config USB_XHCI_HCD
+	bool "xHCI HCD (USB 3.0) support"
+	---help---
+	  The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0
+	  "SuperSpeed" host controller hardware.
+
+config USB_XHCI
+	bool
+	default USB_XHCI_HCD
+	---help---
+	  TODO: rename after most boards switch to Kconfig
+
+if USB_XHCI_HCD
+
+endif
+
+config USB_EHCI_HCD
+	bool "EHCI HCD (USB 2.0) support"
+	---help---
+	  The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0
+	  "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware.
+	  If your USB host controller supports USB 2.0, you will likely want to
+	  configure this Host Controller Driver.
+
+	  EHCI controllers are packaged with "companion" host controllers (OHCI
+	  or UHCI) to handle USB 1.1 devices connected to root hub ports.  Ports
+	  will connect to EHCI if the device is high speed, otherwise they
+	  connect to a companion controller.  If you configure EHCI, you should
+	  probably configure the OHCI (for NEC and some other vendors) USB Host
+	  Controller Driver or UHCI (for Via motherboards) Host Controller
+	  Driver too.
+
+	  You may want to read <file:Documentation/usb/ehci.txt>.
+
+config USB_EHCI
+	bool
+	default USB_EHCI_HCD
+	---help---
+	  TODO: rename after most boards switch to Kconfig
+
+if USB_EHCI_HCD
+
+config USB_EHCI_UNIPHIER
+	bool "Support for Panasonic UniPhier on-chip EHCI USB controller"
+	depends on ARCH_UNIPHIER
+	default y
+	---help---
+	  Enables support for the on-chip EHCI controller on Panasonic
+	  UniPhier SoCs.
+
+endif
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 1c35929..c11b551 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
 obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
 obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
 obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
+obj-$(CONFIG_USB_EHCI_UNIPHIER) += ehci-uniphier.o
 obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
 obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
 obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
diff --git a/drivers/usb/host/ehci-uniphier.c b/drivers/usb/host/ehci-uniphier.c
new file mode 100644
index 0000000..77f6c9d
--- /dev/null
+++ b/drivers/usb/host/ehci-uniphier.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm/arch/ehci-uniphier.h>
+#include "ehci.h"
+
+/*
+ * Create the appropriate control structures to manage
+ * a new EHCI host controller.
+ */
+int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
+		  struct ehci_hcor **hcor)
+{
+	struct ehci_hccr *cr;
+	struct ehci_hcor *or;
+
+	uniphier_ehci_reset(index, 0);
+
+	cr = (struct ehci_hccr *)(uniphier_ehci_platdata[index].base);
+	or = (void *)cr + HC_LENGTH(ehci_readl(&cr->cr_capbase));
+
+	*hccr = cr;
+	*hcor = or;
+
+	return 0;
+}
+
+int ehci_hcd_stop(int index)
+{
+	uniphier_ehci_reset(index, 1);
+
+	return 0;
+}