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-rw-r--r--drivers/mtd/cfi_flash.c4
-rw-r--r--drivers/mtd/nand/fsl_upm.c82
-rw-r--r--drivers/mtd/nand/nand.c6
-rw-r--r--drivers/mtd/nand/nand_base.c2
-rw-r--r--drivers/spi/bfin_spi.c8
5 files changed, 79 insertions, 23 deletions
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index 391d169..631b969 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -2009,7 +2009,9 @@ unsigned long flash_init (void)
#endif
#ifdef CONFIG_SYS_FLASH_PROTECTION
- char *s = getenv("unlock");
+ /* read environment from EEPROM */
+ char s[64];
+ getenv_r ("unlock", s, sizeof(s));
#endif
#define BANK_BASE(i) (((phys_addr_t [CFI_MAX_FLASH_BANKS])CONFIG_SYS_FLASH_BANKS_LIST)[i])
diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c
index 1a1d8c4..7cb99cb 100644
--- a/drivers/mtd/nand/fsl_upm.c
+++ b/drivers/mtd/nand/fsl_upm.c
@@ -31,26 +31,59 @@ static void fsl_upm_end_pattern(struct fsl_upm *upm)
eieio();
}
-static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, u32 cmd)
+static void fsl_upm_run_pattern(struct fsl_upm *upm, int width,
+ void __iomem *io_addr, u32 mar)
{
- out_be32(upm->mar, cmd << (32 - width));
+ out_be32(upm->mar, mar);
switch (width) {
case 8:
- out_8(upm->io_addr, 0x0);
+ out_8(io_addr, 0x0);
break;
case 16:
- out_be16(upm->io_addr, 0x0);
+ out_be16(io_addr, 0x0);
break;
case 32:
- out_be32(upm->io_addr, 0x0);
+ out_be32(io_addr, 0x0);
break;
}
}
+static void fun_wait(struct fsl_upm_nand *fun)
+{
+ if (fun->dev_ready) {
+ while (!fun->dev_ready(fun->chip_nr))
+ debug("unexpected busy state\n");
+ } else {
+ /*
+ * If the R/B pin is not connected, like on the TQM8548,
+ * a short delay is necessary.
+ */
+ udelay(1);
+ }
+}
+
+#if CONFIG_SYS_NAND_MAX_CHIPS > 1
+static void fun_select_chip(struct mtd_info *mtd, int chip_nr)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct fsl_upm_nand *fun = chip->priv;
+
+ if (chip_nr >= 0) {
+ fun->chip_nr = chip_nr;
+ chip->IO_ADDR_R = chip->IO_ADDR_W =
+ fun->upm.io_addr + fun->chip_offset * chip_nr;
+ } else if (chip_nr == -1) {
+ chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
+ }
+}
+#endif
+
static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *chip = mtd->priv;
struct fsl_upm_nand *fun = chip->priv;
+ void __iomem *io_addr;
+ u32 mar;
if (!(ctrl & fun->last_ctrl)) {
fsl_upm_end_pattern(&fun->upm);
@@ -68,18 +101,25 @@ static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
}
- fsl_upm_run_pattern(&fun->upm, fun->width, cmd);
+ mar = cmd << (32 - fun->width);
+ io_addr = fun->upm.io_addr;
+#if CONFIG_SYS_NAND_MAX_CHIPS > 1
+ if (fun->chip_nr > 0) {
+ io_addr += fun->chip_offset * fun->chip_nr;
+ if (fun->upm_mar_chip_offset)
+ mar |= fun->upm_mar_chip_offset * fun->chip_nr;
+ }
+#endif
+ fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar);
/*
- * Some boards/chips needs this. At least on MPC8360E-RDK we
- * need it. Probably weird chip, because I don't see any need
- * for this on MPC8555E + Samsung K9F1G08U0A. Usually here are
- * 0-2 unexpected busy states per block read.
+ * Some boards/chips needs this. At least the MPC8360E-RDK and
+ * TQM8548 need it. Probably weird chip, because I don't see
+ * any need for this on MPC8555E + Samsung K9F1G08U0A. Usually
+ * here are 0-2 unexpected busy states per block read.
*/
- if (fun->wait_pattern) {
- while (!fun->dev_ready())
- debug("unexpected busy state\n");
- }
+ if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
+ fun_wait(fun);
}
static u8 nand_read_byte(struct mtd_info *mtd)
@@ -93,9 +133,16 @@ static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
{
int i;
struct nand_chip *chip = mtd->priv;
+ struct fsl_upm_nand *fun = chip->priv;
- for (i = 0; i < len; i++)
+ for (i = 0; i < len; i++) {
out_8(chip->IO_ADDR_W, buf[i]);
+ if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
+ fun_wait(fun);
+ }
+
+ if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
+ fun_wait(fun);
}
static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
@@ -125,7 +172,7 @@ static int nand_dev_ready(struct mtd_info *mtd)
struct nand_chip *chip = mtd->priv;
struct fsl_upm_nand *fun = chip->priv;
- return fun->dev_ready();
+ return fun->dev_ready(fun->chip_nr);
}
int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
@@ -139,6 +186,9 @@ int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
chip->chip_delay = fun->chip_delay;
chip->ecc.mode = NAND_ECC_SOFT;
chip->cmd_ctrl = fun_cmd_ctrl;
+#if CONFIG_SYS_NAND_MAX_CHIPS > 1
+ chip->select_chip = fun_select_chip;
+#endif
chip->read_byte = nand_read_byte;
chip->read_buf = nand_read_buf;
chip->write_buf = nand_write_buf;
diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
index 70b605f..9d83794 100644
--- a/drivers/mtd/nand/nand.c
+++ b/drivers/mtd/nand/nand.c
@@ -41,11 +41,15 @@ static const char default_nand_name[] = "nand";
static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand,
ulong base_addr)
{
+ int maxchips = CONFIG_SYS_NAND_MAX_CHIPS;
+
+ if (maxchips < 1)
+ maxchips = 1;
mtd->priv = nand;
nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
if (board_nand_init(nand) == 0) {
- if (nand_scan(mtd, 1) == 0) {
+ if (nand_scan(mtd, maxchips) == 0) {
if (!mtd->name)
mtd->name = (char *)default_nand_name;
else
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index d33fee2..e6ac859 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2652,8 +2652,10 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips)
type->id != chip->read_byte(mtd))
break;
}
+#ifdef DEBUG
if (i > 1)
printk(KERN_INFO "%d NAND chips detected\n", i);
+#endif
/* Store the number of chips and calc total size for mtd */
chip->numchips = i;
diff --git a/drivers/spi/bfin_spi.c b/drivers/spi/bfin_spi.c
index d22862a..0472c1a 100644
--- a/drivers/spi/bfin_spi.c
+++ b/drivers/spi/bfin_spi.c
@@ -191,21 +191,19 @@ static void spi_portmux(struct spi_slave *slave)
#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
u16 mux = bfin_read_PORT_MUX();
u16 f_fer = bfin_read_PORTF_FER();
- u16 j_fer = bfin_read_PORTJ_FER();
/* set SCK/MISO/MOSI */
f_fer |= PF11 | PF12 | PF13;
switch (slave->cs) {
case 1: f_fer |= PF10; break;
- case 2: mux |= PJSE; j_fer |= PJ11; break;
- case 3: mux |= PJSE; j_fer |= PJ10; break;
+ case 2: mux |= PJSE; break;
+ case 3: mux |= PJSE; break;
case 4: mux |= PFS4E; f_fer |= PF6; break;
case 5: mux |= PFS5E; f_fer |= PF5; break;
case 6: mux |= PFS6E; f_fer |= PF4; break;
- case 7: mux |= PJCE_SPI; j_fer |= PJ5; break;
+ case 7: mux |= PJCE_SPI; break;
}
bfin_write_PORT_MUX(mux);
bfin_write_PORTF_FER(f_fer);
- bfin_write_PORTJ_FER(j_fer);
#elif defined(__ADSPBF54x__)
#define DO_MUX(port, pin) \
mux = ((mux & ~PORT_x_MUX_##pin##_MASK) | PORT_x_MUX_##pin##_FUNC_1); \
generated by cgit v1.1 at 2024-12-21 11:12:58 +0000