diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/Makefile | 1 | ||||
| -rw-r--r-- | drivers/net/e1000.c | 88 | ||||
| -rw-r--r-- | drivers/net/ftmac100.c | 278 | ||||
| -rw-r--r-- | drivers/net/ftmac100.h | 154 | ||||
| -rw-r--r-- | drivers/net/kirkwood_egiga.c | 15 | ||||
| -rw-r--r-- | drivers/net/phy/mv88e61xx.c | 23 | ||||
| -rw-r--r-- | drivers/qe/uec.c | 17 | ||||
| -rw-r--r-- | drivers/qe/uec_phy.c | 36 |
8 files changed, 528 insertions, 84 deletions
diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 34b56d8..1c6e402 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -39,6 +39,7 @@ COBJS-$(CONFIG_EEPRO100) += eepro100.o COBJS-$(CONFIG_ENC28J60) += enc28j60.o COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o +COBJS-$(CONFIG_FTMAC100) += ftmac100.o COBJS-$(CONFIG_GRETH) += greth.o COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o COBJS-$(CONFIG_KIRKWOOD_EGIGA) += kirkwood_egiga.o diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index e3c6cea..777783a 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -126,9 +126,6 @@ static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, static int32_t e1000_phy_hw_reset(struct e1000_hw *hw); static int e1000_phy_reset(struct e1000_hw *hw); static int e1000_detect_gig_phy(struct e1000_hw *hw); -static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, - uint16_t words, - uint16_t *data); static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); static void e1000_set_media_type(struct e1000_hw *hw); @@ -143,6 +140,9 @@ static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);} #ifndef CONFIG_AP1000 /* remove for warnings */ +static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, + uint16_t words, + uint16_t *data); /****************************************************************************** * Raises the EEPROM's clock input. * @@ -896,6 +896,47 @@ e1000_validate_eeprom_checksum(struct eth_device *nic) return -E1000_ERR_EEPROM; } } + +/***************************************************************************** + * Set PHY to class A mode + * Assumes the following operations will follow to enable the new class mode. + * 1. Do a PHY soft reset + * 2. Restart auto-negotiation or force link. + * + * hw - Struct containing variables accessed by shared code + ****************************************************************************/ +static int32_t +e1000_set_phy_mode(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t eeprom_data; + + DEBUGFUNC(); + + if ((hw->mac_type == e1000_82545_rev_3) && + (hw->media_type == e1000_media_type_copper)) { + ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, + 1, &eeprom_data); + if (ret_val) + return ret_val; + + if ((eeprom_data != EEPROM_RESERVED_WORD) && + (eeprom_data & EEPROM_PHY_CLASS_A)) { + ret_val = e1000_write_phy_reg(hw, + M88E1000_PHY_PAGE_SELECT, 0x000B); + if (ret_val) + return ret_val; + ret_val = e1000_write_phy_reg(hw, + M88E1000_PHY_GEN_CONTROL, 0x8104); + if (ret_val) + return ret_val; + + hw->phy_reset_disable = FALSE; + } + } + + return E1000_SUCCESS; +} #endif /* #ifndef CONFIG_AP1000 */ /*************************************************************************** @@ -1999,47 +2040,6 @@ e1000_setup_fiber_link(struct eth_device *nic) return 0; } -/***************************************************************************** - * Set PHY to class A mode - * Assumes the following operations will follow to enable the new class mode. - * 1. Do a PHY soft reset - * 2. Restart auto-negotiation or force link. - * - * hw - Struct containing variables accessed by shared code - ****************************************************************************/ -static int32_t -e1000_set_phy_mode(struct e1000_hw *hw) -{ - int32_t ret_val; - uint16_t eeprom_data; - - DEBUGFUNC(); - - if ((hw->mac_type == e1000_82545_rev_3) && - (hw->media_type == e1000_media_type_copper)) { - ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, - 1, &eeprom_data); - if (ret_val) - return ret_val; - - if ((eeprom_data != EEPROM_RESERVED_WORD) && - (eeprom_data & EEPROM_PHY_CLASS_A)) { - ret_val = e1000_write_phy_reg(hw, - M88E1000_PHY_PAGE_SELECT, 0x000B); - if (ret_val) - return ret_val; - ret_val = e1000_write_phy_reg(hw, - M88E1000_PHY_GEN_CONTROL, 0x8104); - if (ret_val) - return ret_val; - - hw->phy_reset_disable = FALSE; - } - } - - return E1000_SUCCESS; -} - /****************************************************************************** * Make sure we have a valid PHY and change PHY mode before link setup. * diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c new file mode 100644 index 0000000..2328cb5 --- /dev/null +++ b/drivers/net/ftmac100.c @@ -0,0 +1,278 @@ +/* + * Faraday FTMAC100 Ethernet + * + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert@faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <malloc.h> +#include <net.h> +#include <asm/io.h> + +#include "ftmac100.h" + +#define ETH_ZLEN 60 + +struct ftmac100_data { + volatile struct ftmac100_txdes txdes[1]; + volatile struct ftmac100_rxdes rxdes[PKTBUFSRX]; + int rx_index; +}; + +/* + * Reset MAC + */ +static void ftmac100_reset (struct eth_device *dev) +{ + struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; + + debug ("%s()\n", __func__); + + writel (FTMAC100_MACCR_SW_RST, &ftmac100->maccr); + + while (readl (&ftmac100->maccr) & FTMAC100_MACCR_SW_RST) + ; +} + +/* + * Set MAC address + */ +static void ftmac100_set_mac (struct eth_device *dev, const unsigned char *mac) +{ + struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; + unsigned int maddr = mac[0] << 8 | mac[1]; + unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; + + debug ("%s(%x %x)\n", __func__, maddr, laddr); + + writel (maddr, &ftmac100->mac_madr); + writel (laddr, &ftmac100->mac_ladr); +} + +static void ftmac100_set_mac_from_env (struct eth_device *dev) +{ + eth_getenv_enetaddr ("ethaddr", dev->enetaddr); + + ftmac100_set_mac (dev, dev->enetaddr); +} + +/* + * disable transmitter, receiver + */ +static void ftmac100_halt (struct eth_device *dev) +{ + struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; + + debug ("%s()\n", __func__); + + writel (0, &ftmac100->maccr); +} + +static int ftmac100_init (struct eth_device *dev, bd_t *bd) +{ + struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; + struct ftmac100_data *priv = dev->priv; + volatile struct ftmac100_txdes *txdes = priv->txdes; + volatile struct ftmac100_rxdes *rxdes = priv->rxdes; + unsigned int maccr; + int i; + + debug ("%s()\n", __func__); + + ftmac100_reset (dev); + + /* set the ethernet address */ + + ftmac100_set_mac_from_env (dev); + + /* disable all interrupts */ + + writel (0, &ftmac100->imr); + + /* initialize descriptors */ + + priv->rx_index = 0; + + txdes[0].txdes1 = FTMAC100_TXDES1_EDOTR; + rxdes[PKTBUFSRX - 1].rxdes1 = FTMAC100_RXDES1_EDORR; + + for (i = 0; i < PKTBUFSRX; i++) { + /* RXBUF_BADR */ + rxdes[i].rxdes2 = (unsigned int)NetRxPackets[i]; + rxdes[i].rxdes1 |= FTMAC100_RXDES1_RXBUF_SIZE (PKTSIZE_ALIGN); + rxdes[i].rxdes0 = FTMAC100_RXDES0_RXDMA_OWN; + } + + /* transmit ring */ + + writel ((unsigned int)txdes, &ftmac100->txr_badr); + + /* receive ring */ + + writel ((unsigned int)rxdes, &ftmac100->rxr_badr); + + /* poll receive descriptor automatically */ + + writel (FTMAC100_APTC_RXPOLL_CNT (1), &ftmac100->aptc); + + /* enable transmitter, receiver */ + + maccr = FTMAC100_MACCR_XMT_EN | + FTMAC100_MACCR_RCV_EN | + FTMAC100_MACCR_XDMA_EN | + FTMAC100_MACCR_RDMA_EN | + FTMAC100_MACCR_CRC_APD | + FTMAC100_MACCR_ENRX_IN_HALFTX | + FTMAC100_MACCR_RX_RUNT | + FTMAC100_MACCR_RX_BROADPKT; + + writel (maccr, &ftmac100->maccr); + + return 0; +} + +/* + * Get a data block via Ethernet + */ +static int ftmac100_recv (struct eth_device *dev) +{ + struct ftmac100_data *priv = dev->priv; + volatile struct ftmac100_rxdes *curr_des; + unsigned short rxlen; + + curr_des = &priv->rxdes[priv->rx_index]; + + if (curr_des->rxdes0 & FTMAC100_RXDES0_RXDMA_OWN) + return -1; + + if (curr_des->rxdes0 & (FTMAC100_RXDES0_RX_ERR | + FTMAC100_RXDES0_CRC_ERR | + FTMAC100_RXDES0_FTL | + FTMAC100_RXDES0_RUNT | + FTMAC100_RXDES0_RX_ODD_NB)) { + return -1; + } + + rxlen = FTMAC100_RXDES0_RFL (curr_des->rxdes0); + + debug ("%s(): RX buffer %d, %x received\n", + __func__, priv->rx_index, rxlen); + + /* pass the packet up to the protocol layers. */ + + NetReceive ((void *)curr_des->rxdes2, rxlen); + + /* release buffer to DMA */ + + curr_des->rxdes0 |= FTMAC100_RXDES0_RXDMA_OWN; + + priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX; + + return 0; +} + +/* + * Send a data block via Ethernet + */ +static int +ftmac100_send (struct eth_device *dev, volatile void *packet, int length) +{ + struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; + struct ftmac100_data *priv = dev->priv; + volatile struct ftmac100_txdes *curr_des = priv->txdes; + int tmo; + + if (curr_des->txdes0 & FTMAC100_TXDES0_TXDMA_OWN) { + debug ("%s(): no TX descriptor available\n", __func__); + return -1; + } + + debug ("%s(%x, %x)\n", __func__, (int)packet, length); + + length = (length < ETH_ZLEN) ? ETH_ZLEN : length; + + /* initiate a transmit sequence */ + + curr_des->txdes2 = (unsigned int)packet; /* TXBUF_BADR */ + + curr_des->txdes1 &= FTMAC100_TXDES1_EDOTR; + curr_des->txdes1 |= FTMAC100_TXDES1_FTS | + FTMAC100_TXDES1_LTS | + FTMAC100_TXDES1_TXBUF_SIZE (length); + + curr_des->txdes0 = FTMAC100_TXDES0_TXDMA_OWN; + + /* start transmit */ + + writel (1, &ftmac100->txpd); + + /* wait for transfer to succeed */ + + tmo = get_timer (0) + 5 * CONFIG_SYS_HZ; + while (curr_des->txdes0 & FTMAC100_TXDES0_TXDMA_OWN) { + if (get_timer (0) >= tmo) { + debug ("%s(): timed out\n", __func__); + return -1; + } + } + + debug ("%s(): packet sent\n", __func__); + + return 0; +} + +int ftmac100_initialize (bd_t *bd) +{ + struct eth_device *dev; + struct ftmac100_data *priv; + + dev = malloc (sizeof *dev); + if (!dev) { + printf ("%s(): failed to allocate dev\n", __func__); + goto out; + } + + /* Transmit and receive descriptors should align to 16 bytes */ + + priv = memalign (16, sizeof (struct ftmac100_data)); + if (!priv) { + printf ("%s(): failed to allocate priv\n", __func__); + goto free_dev; + } + + memset (dev, 0, sizeof (*dev)); + memset (priv, 0, sizeof (*priv)); + + sprintf (dev->name, "FTMAC100"); + dev->iobase = CONFIG_FTMAC100_BASE; + dev->init = ftmac100_init; + dev->halt = ftmac100_halt; + dev->send = ftmac100_send; + dev->recv = ftmac100_recv; + dev->priv = priv; + + eth_register (dev); + + return 1; + +free_dev: + free (dev); +out: + return 0; +} diff --git a/drivers/net/ftmac100.h b/drivers/net/ftmac100.h new file mode 100644 index 0000000..21142d9 --- /dev/null +++ b/drivers/net/ftmac100.h @@ -0,0 +1,154 @@ +/* + * Faraday FTMAC100 Ethernet + * + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert@faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __FTMAC100_H +#define __FTMAC100_H + +struct ftmac100 { + unsigned int isr; /* 0x00 */ + unsigned int imr; /* 0x04 */ + unsigned int mac_madr; /* 0x08 */ + unsigned int mac_ladr; /* 0x0c */ + unsigned int maht0; /* 0x10 */ + unsigned int maht1; /* 0x14 */ + unsigned int txpd; /* 0x18 */ + unsigned int rxpd; /* 0x1c */ + unsigned int txr_badr; /* 0x20 */ + unsigned int rxr_badr; /* 0x24 */ + unsigned int itc; /* 0x28 */ + unsigned int aptc; /* 0x2c */ + unsigned int dblac; /* 0x30 */ + unsigned int pad1[3]; /* 0x34 - 0x3c */ + unsigned int pad2[16]; /* 0x40 - 0x7c */ + unsigned int pad3[2]; /* 0x80 - 0x84 */ + unsigned int maccr; /* 0x88 */ + unsigned int macsr; /* 0x8c */ + unsigned int phycr; /* 0x90 */ + unsigned int phywdata; /* 0x94 */ + unsigned int fcr; /* 0x98 */ + unsigned int bpr; /* 0x9c */ + unsigned int pad4[8]; /* 0xa0 - 0xbc */ + unsigned int pad5; /* 0xc0 */ + unsigned int ts; /* 0xc4 */ + unsigned int dmafifos; /* 0xc8 */ + unsigned int tm; /* 0xcc */ + unsigned int pad6; /* 0xd0 */ + unsigned int tx_mcol_scol; /* 0xd4 */ + unsigned int rpf_aep; /* 0xd8 */ + unsigned int xm_pg; /* 0xdc */ + unsigned int runt_tlcc; /* 0xe0 */ + unsigned int crcer_ftl; /* 0xe4 */ + unsigned int rlc_rcc; /* 0xe8 */ + unsigned int broc; /* 0xec */ + unsigned int mulca; /* 0xf0 */ + unsigned int rp; /* 0xf4 */ + unsigned int xp; /* 0xf8 */ +}; + +/* + * Interrupt status register & interrupt mask register + */ +#define FTMAC100_INT_RPKT_FINISH (1 << 0) +#define FTMAC100_INT_NORXBUF (1 << 1) +#define FTMAC100_INT_XPKT_FINISH (1 << 2) +#define FTMAC100_INT_NOTXBUF (1 << 3) +#define FTMAC100_INT_XPKT_OK (1 << 4) +#define FTMAC100_INT_XPKT_LOST (1 << 5) +#define FTMAC100_INT_RPKT_SAV (1 << 6) +#define FTMAC100_INT_RPKT_LOST (1 << 7) +#define FTMAC100_INT_AHB_ERR (1 << 8) +#define FTMAC100_INT_PHYSTS_CHG (1 << 9) + +/* + * Automatic polling timer control register + */ +#define FTMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) +#define FTMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) +#define FTMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) +#define FTMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) + +/* + * MAC control register + */ +#define FTMAC100_MACCR_XDMA_EN (1 << 0) +#define FTMAC100_MACCR_RDMA_EN (1 << 1) +#define FTMAC100_MACCR_SW_RST (1 << 2) +#define FTMAC100_MACCR_LOOP_EN (1 << 3) +#define FTMAC100_MACCR_CRC_DIS (1 << 4) +#define FTMAC100_MACCR_XMT_EN (1 << 5) +#define FTMAC100_MACCR_ENRX_IN_HALFTX (1 << 6) +#define FTMAC100_MACCR_RCV_EN (1 << 8) +#define FTMAC100_MACCR_HT_MULTI_EN (1 << 9) +#define FTMAC100_MACCR_RX_RUNT (1 << 10) +#define FTMAC100_MACCR_RX_FTL (1 << 11) +#define FTMAC100_MACCR_RCV_ALL (1 << 12) +#define FTMAC100_MACCR_CRC_APD (1 << 14) +#define FTMAC100_MACCR_FULLDUP (1 << 15) +#define FTMAC100_MACCR_RX_MULTIPKT (1 << 16) +#define FTMAC100_MACCR_RX_BROADPKT (1 << 17) + +/* + * Transmit descriptor, aligned to 16 bytes + */ +struct ftmac100_txdes { + unsigned int txdes0; + unsigned int txdes1; + unsigned int txdes2; /* TXBUF_BADR */ + unsigned int txdes3; /* not used by HW */ +} __attribute__ ((aligned(16))); + +#define FTMAC100_TXDES0_TXPKT_LATECOL (1 << 0) +#define FTMAC100_TXDES0_TXPKT_EXSCOL (1 << 1) +#define FTMAC100_TXDES0_TXDMA_OWN (1 << 31) + +#define FTMAC100_TXDES1_TXBUF_SIZE(x) ((x) & 0x7ff) +#define FTMAC100_TXDES1_LTS (1 << 27) +#define FTMAC100_TXDES1_FTS (1 << 28) +#define FTMAC100_TXDES1_TX2FIC (1 << 29) +#define FTMAC100_TXDES1_TXIC (1 << 30) +#define FTMAC100_TXDES1_EDOTR (1 << 31) + +/* + * Receive descriptor, aligned to 16 bytes + */ +struct ftmac100_rxdes { + unsigned int rxdes0; + unsigned int rxdes1; + unsigned int rxdes2; /* RXBUF_BADR */ + unsigned int rxdes3; /* not used by HW */ +} __attribute__ ((aligned(16))); + +#define FTMAC100_RXDES0_RFL(des) ((des) & 0x7ff) +#define FTMAC100_RXDES0_MULTICAST (1 << 16) +#define FTMAC100_RXDES0_BROADCAST (1 << 17) +#define FTMAC100_RXDES0_RX_ERR (1 << 18) +#define FTMAC100_RXDES0_CRC_ERR (1 << 19) +#define FTMAC100_RXDES0_FTL (1 << 20) +#define FTMAC100_RXDES0_RUNT (1 << 21) +#define FTMAC100_RXDES0_RX_ODD_NB (1 << 22) +#define FTMAC100_RXDES0_LRS (1 << 28) +#define FTMAC100_RXDES0_FRS (1 << 29) +#define FTMAC100_RXDES0_RXDMA_OWN (1 << 31) + +#define FTMAC100_RXDES1_RXBUF_SIZE(x) ((x) & 0x7ff) +#define FTMAC100_RXDES1_EDORR (1 << 31) + +#endif /* __FTMAC100_H */ diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/kirkwood_egiga.c index 701812b..f31fefc 100644 --- a/drivers/net/kirkwood_egiga.c +++ b/drivers/net/kirkwood_egiga.c @@ -592,7 +592,7 @@ int kirkwood_egiga_initialize(bd_t * bis) struct kwgbe_device *dkwgbe; struct eth_device *dev; int devnum; - char *s, buf[NAMESIZE * 2]; + char *s; u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS; for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) { @@ -650,11 +650,14 @@ int kirkwood_egiga_initialize(bd_t * bis) } while (!eth_getenv_enetaddr(s, dev->enetaddr)) { - /* Generate Ramdom MAC addresses if not set */ - sprintf(buf, "00:50:43:%02x:%02x:%02x", - get_random_hex(), get_random_hex(), - get_random_hex()); - setenv(s, buf); + /* Generate Random Private MAC addr if not set */ + dev->enetaddr[0] = 0x02; + dev->enetaddr[1] = 0x50; + dev->enetaddr[2] = 0x43; + dev->enetaddr[3] = get_random_hex(); + dev->enetaddr[4] = get_random_hex(); + dev->enetaddr[5] = get_random_hex(); + eth_setenv_enetaddr(s, dev->enetaddr); } dev->init = (void *)kwgbe_init; diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 29630f5..3754e8b 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -38,7 +38,7 @@ */ static int mv88e61xx_busychk_multic(char *name, u32 devaddr) { - u32 reg = 0; + u16 reg = 0; u32 timeout = MV88E61XX_PHY_TIMEOUT; /* Poll till SMIBusy bit is clear */ @@ -54,8 +54,7 @@ static int mv88e61xx_busychk_multic(char *name, u32 devaddr) static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data) { - u16 reg; - u32 mii_dev_addr; + u16 mii_dev_addr; /* command to read PHY dev address */ if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) { @@ -73,8 +72,7 @@ static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data) static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data) { - u16 reg; - u32 mii_dev_addr; + u16 mii_dev_addr; /* command to read PHY dev address */ if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) { @@ -357,15 +355,22 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) } RD_PHY(name, MV88E61XX_PRT_OFST, PHY_PHYIDR2, ®); - reg &= 0xfff0; - if (reg == 0x1610) + switch (reg &= 0xfff0) { + case 0x1610: idstr = "88E6161"; - if (reg == 0x1650) + break; + case 0x1650: idstr = "88E6165"; - if (reg == 0x1210) { + break; + case 0x1210: idstr = "88E6123"; /* ports 2,3,4 not available */ swconfig->ports_enabled &= 0x023; + break; + default: + /* Could not detect switch id */ + idstr = "88E61??"; + break; } /* Port based VLANs configuration */ diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index d48d22b..db95ada 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -31,6 +31,11 @@ #include "uec_phy.h" #include "miiphy.h" +/* Default UTBIPAR SMI address */ +#ifndef CONFIG_UTBIPAR_INIT_TBIPA +#define CONFIG_UTBIPAR_INIT_TBIPA 0x1F +#endif + static uec_info_t uec_info[] = { #ifdef CONFIG_UEC_ETH1 STD_UEC_INFO(1), /* UEC1 */ @@ -1071,15 +1076,11 @@ static int uec_startup(uec_private_t *uec) utbipar = in_be32(&uec_regs->utbipar); utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK; enet_interface = uec->uec_info->enet_interface; - if (enet_interface == ENET_1000_TBI || - enet_interface == ENET_1000_RTBI) { - utbipar |= (uec_info->phy_address + uec_info->uf_info.ucc_num) - << UTBIPAR_PHY_ADDRESS_SHIFT; - } else { - utbipar |= (0x10 + uec_info->uf_info.ucc_num) - << UTBIPAR_PHY_ADDRESS_SHIFT; - } + /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC. + * This frees up the remaining SMI addresses for use. + */ + utbipar |= CONFIG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT; out_be32(&uec_regs->utbipar, utbipar); /* Configure the TBI for SGMII operation */ diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index d613f3e..aa4eb5e 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -51,27 +51,28 @@ *--------------------------------------------------------------------*/ /* - * Some boards do not have a PHY for each ethernet port. These ports - * are known as Fixed PHY (or PHY-less) ports. For such ports, set - * the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and - * then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and - * duplex should be for these ports in the board configuration - * file. + * Some boards do not have a PHY for each ethernet port. These ports are known + * as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate + * CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address) + * When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned + * and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network + * speed and duplex should be for the port. * - * For Example: + * Example board header configuration file: * #define CONFIG_FIXED_PHY 0xFFFFFFFF + * #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address) * - * #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY - * #define CONFIG_PHY1_ADDR 1 - * #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY - * #define CONFIG_PHY3_ADDR 3 + * #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR + * #define CONFIG_SYS_UEC2_PHY_ADDR 0x02 + * #define CONFIG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR + * #define CONFIG_SYS_UEC4_PHY_ADDR 0x04 * - * #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \ - * {devnum, speed, duplex}, + * #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \ + * {name, speed, duplex}, * * #define CONFIG_SYS_FIXED_PHY_PORTS \ - * CONFIG_SYS_FIXED_PHY_PORT(0,SPEED_100,DUPLEX_FULL) \ - * CONFIG_SYS_FIXED_PHY_PORT(2,SPEED_100,DUPLEX_HALF) + * CONFIG_SYS_FIXED_PHY_PORT("FSL UEC0",SPEED_100,DUPLEX_FULL) \ + * CONFIG_SYS_FIXED_PHY_PORT("FSL UEC2",SPEED_100,DUPLEX_HALF) */ #ifndef CONFIG_FIXED_PHY @@ -83,7 +84,7 @@ #endif struct fixed_phy_port { - unsigned int devnum; /* ethernet port */ + char name[NAMESIZE]; /* ethernet port name */ unsigned int speed; /* specified speed 10,100 or 1000 */ unsigned int duplex; /* specified duplex FULL or HALF */ }; @@ -592,7 +593,8 @@ static int fixed_phy_read_status (struct uec_mii_info *mii_info) int i = 0; for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) { - if (mii_info->mii_id == fixed_phy_port[i].devnum) { + if (strncmp(mii_info->dev->name, fixed_phy_port[i].name, + strlen(mii_info->dev->name)) == 0) { mii_info->speed = fixed_phy_port[i].speed; mii_info->duplex = fixed_phy_port[i].duplex; mii_info->link = 1; /* Link is always UP */ |