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-rw-r--r--drivers/i2c/soft_i2c.c3
-rw-r--r--drivers/mmc/gen_atmel_mci.c15
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/netarm_eth.c352
-rw-r--r--drivers/net/netarm_eth.h42
-rw-r--r--drivers/serial/Makefile4
-rw-r--r--drivers/serial/s3c4510b_uart.c231
-rw-r--r--drivers/serial/s3c4510b_uart.h109
-rw-r--r--drivers/serial/serial.c6
-rw-r--r--drivers/serial/serial_clps7111.c134
-rw-r--r--drivers/serial/serial_lpc2292.c117
-rw-r--r--drivers/serial/serial_netarm.c204
-rw-r--r--drivers/spi/omap3_spi.c11
-rw-r--r--drivers/usb/musb/musb_udc.c11
14 files changed, 28 insertions, 1212 deletions
diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c
index 36c6114..1595c07 100644
--- a/drivers/i2c/soft_i2c.c
+++ b/drivers/i2c/soft_i2c.c
@@ -41,9 +41,6 @@
#ifdef CONFIG_IXP425 /* only valid for IXP425 */
#include <asm/arch/ixp425.h>
#endif
-#ifdef CONFIG_LPC2292
-#include <asm/arch/hardware.h>
-#endif
#if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866)
#include <asm/io.h>
#endif
diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c
index 4968c5e..67b2dbe 100644
--- a/drivers/mmc/gen_atmel_mci.c
+++ b/drivers/mmc/gen_atmel_mci.c
@@ -87,6 +87,11 @@ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
| MMCI_BF(BLKLEN, blklen)
| MMCI_BIT(RDPROOF)
| MMCI_BIT(WRPROOF)), &mci->mr);
+ /*
+ * On some new platforms BLKLEN in mci->mr is ignored.
+ * Should use the BLKLEN in the block register.
+ */
+ writel(MMCI_BF(BLKLEN, blklen), &mci->blkr);
initialized = 1;
}
@@ -183,6 +188,12 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
/* Figure out the transfer arguments */
cmdr = mci_encode_cmd(cmd, data, &error_flags);
+ /* For multi blocks read/write, set the block register */
+ if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)
+ || (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK))
+ writel(data->blocks | MMCI_BF(BLKLEN, mmc->read_bl_len),
+ &mci->blkr);
+
/* Send the command */
writel(cmd->cmdarg, &mci->argr);
writel(cmdr, &mci->cmdr);
@@ -310,8 +321,8 @@ static int mci_init(struct mmc *mmc)
writel(MMCI_BIT(MCIEN), &mci->cr); /* enable mci */
writel(MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); /* select port */
- /* Initial Time-outs */
- writel(0x5f, &mci->dtor);
+ /* This delay can be optimized, but stick with max value */
+ writel(0x7f, &mci->dtor);
/* Disable Interrupts */
writel(~0UL, &mci->idr);
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index e4abac7..786a656 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -59,7 +59,6 @@ COBJS-$(CONFIG_MVGBE) += mvgbe.o
COBJS-$(CONFIG_NATSEMI) += natsemi.o
COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
-COBJS-$(CONFIG_DRIVER_NETARMETH) += netarm_eth.o
COBJS-$(CONFIG_NETCONSOLE) += netconsole.o
COBJS-$(CONFIG_NS8382X) += ns8382x.o
COBJS-$(CONFIG_PCNET) += pcnet.o
diff --git a/drivers/net/netarm_eth.c b/drivers/net/netarm_eth.c
deleted file mode 100644
index 325f16c..0000000
--- a/drivers/net/netarm_eth.c
+++ /dev/null
@@ -1,352 +0,0 @@
-/*
- * Copyright (C) 2004 IMMS gGmbH <www.imms.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * author(s): Thomas Elste, <info@elste.org>
- * (some parts derived from uCLinux Netarm Ethernet Driver)
- */
-
-
-#include <common.h>
-#include <command.h>
-#include <net.h>
-#include "netarm_eth.h"
-#include <asm/arch/netarm_registers.h>
-
-static int na_mii_poll_busy (void);
-
-static void na_get_mac_addr (void)
-{
- unsigned short p[3];
- char *m_addr;
- char ethaddr[20];
-
- m_addr = (char *) p;
-
- p[0] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_1);
- p[1] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_2);
- p[2] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_3);
-
- sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
- m_addr[0], m_addr[1],
- m_addr[2], m_addr[3], m_addr[4], m_addr[5]);
-
- printf ("HW-MAC Address: %s\n", ethaddr);
-
- /* set env, todo: check if already an adress is set */
- setenv ("ethaddr", ethaddr);
-}
-
-static void na_mii_write (int reg, int value)
-{
- int mii_addr;
-
- /* Select register */
- mii_addr = CONFIG_SYS_ETH_PHY_ADDR + reg;
- SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr);
- /* Write value */
- SET_EADDR (NETARM_ETH_MII_WRITE, value);
- na_mii_poll_busy ();
-}
-
-static unsigned int na_mii_read (int reg)
-{
- int mii_addr, val;
-
- /* Select register */
- mii_addr = CONFIG_SYS_ETH_PHY_ADDR + reg;
- SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr);
- /* do one management cycle */
- SET_EADDR (NETARM_ETH_MII_CMD,
- GET_EADDR (NETARM_ETH_MII_CMD) | NETARM_ETH_MIIC_RSTAT);
- na_mii_poll_busy ();
- /* Return read value */
- val = GET_EADDR (NETARM_ETH_MII_READ);
- return val;
-}
-
-static int na_mii_poll_busy (void)
-{
- ulong start;
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0));
- while (get_timer(start) < NA_MII_POLL_BUSY_DELAY) {
- if (!(GET_EADDR (NETARM_ETH_MII_IND) & NETARM_ETH_MIII_BUSY)) {
- return 1;
- }
- }
- printf ("na_mii_busy timeout\n");
- return (0);
-}
-
-static int na_mii_identify_phy (void)
-{
- int id_reg_a = 0;
-
- /* get phy id register */
- id_reg_a = na_mii_read (MII_PHY_ID);
-
- if (id_reg_a == 0x0043) {
- /* This must be an Enable or a Lucent LU3X31 PHY chip */
- return 1;
- } else if (id_reg_a == 0x0013) {
- /* it is an Intel LXT971A */
- return 1;
- }
- return (0);
-}
-
-static int na_mii_negotiate (void)
-{
- int i = 0;
-
- /* Enable auto-negotiation */
- na_mii_write (MII_PHY_AUTONEGADV, 0x01e1);
- /* FIXME: 0x01E1 is 100Mb half and full duplex, 0x0061 is 10Mb only */
- /* Restart auto-negotiation */
- na_mii_write (MII_PHY_CONTROL, 0x1200);
-
- /* status register is 0xffff after setting the autoneg restart bit */
- while (na_mii_read (MII_PHY_STATUS) == 0xffff) {
- i++;
- }
-
- /* na_mii_read uses the timer already, so we can't use it again for
- timeout checking.
- Instead we just try some times.
- */
- for (i = 0; i < 40000; i++) {
- if ((na_mii_read (MII_PHY_STATUS) & 0x0024) == 0x0024) {
- return 0;
- }
- }
- /*
- printf("*Warning* autonegotiation timeout, status: 0x%x\n",na_mii_read(MII_PHY_STATUS));
- */
- return (1);
-}
-
-static unsigned int na_mii_check_speed (void)
-{
- unsigned int status;
-
- /* Read Status register */
- status = na_mii_read (MII_PHY_STATUS);
- /* Check link status. If 0, default to 100 Mbps. */
- if ((status & 0x0004) == 0) {
- printf ("*Warning* no link detected, set default speed to 100Mbs\n");
- return 1;
- } else {
- if ((na_mii_read (17) & 0x4000) != 0) {
- printf ("100Mbs link detected\n");
- return 1;
- } else {
- printf ("10Mbs link detected\n");
- return 0;
- }
- }
- return 0;
-}
-
-static int reset_eth (void)
-{
- int pt;
- ulong start;
-
- na_get_mac_addr ();
- pt = na_mii_identify_phy ();
-
- /* reset the phy */
- na_mii_write (MII_PHY_CONTROL, 0x8000);
- start = get_timer(0);
- while (get_timer(start) < NA_MII_NEGOTIATE_DELAY) {
- if ((na_mii_read (MII_PHY_STATUS) & 0x8000) == 0) {
- break;
- }
- }
- if (get_timer(start) >= NA_MII_NEGOTIATE_DELAY)
- printf ("phy reset timeout\n");
-
- /* set the PCS reg */
- SET_EADDR (NETARM_ETH_PCS_CFG, NETARM_ETH_PCSC_CLKS_25M |
- NETARM_ETH_PCSC_ENJAB | NETARM_ETH_PCSC_NOCFR);
-
- na_mii_negotiate ();
- na_mii_check_speed ();
-
- /* Delay 10 millisecond. (Maybe this should be 1 second.) */
- udelay (10000);
-
- /* Turn receive on.
- Enable statistics register autozero on read.
- Do not insert MAC address on transmit.
- Do not enable special test modes. */
- SET_EADDR (NETARM_ETH_STL_CFG,
- (NETARM_ETH_STLC_AUTOZ | NETARM_ETH_STLC_RXEN));
-
- /* Set the inter-packet gap delay to 0.96us for MII.
- The NET+ARM H/W Reference Guide indicates that the Back-to-back IPG
- Gap Timer Register should be set to 0x15 and the Non Back-to-back IPG
- Gap Timer Register should be set to 0x00000C12 for the MII PHY. */
- SET_EADDR (NETARM_ETH_B2B_IPG_GAP_TMR, 0x15);
- SET_EADDR (NETARM_ETH_NB2B_IPG_GAP_TMR, 0x00000C12);
-
- /* Add CRC to end of packets.
- Pad packets to minimum length of 64 bytes.
- Allow unlimited length transmit packets.
- Receive all broadcast packets.
- NOTE: Multicast addressing is NOT enabled here currently. */
- SET_EADDR (NETARM_ETH_MAC_CFG,
- (NETARM_ETH_MACC_CRCEN |
- NETARM_ETH_MACC_PADEN | NETARM_ETH_MACC_HUGEN));
- SET_EADDR (NETARM_ETH_SAL_FILTER, NETARM_ETH_SALF_BROAD);
-
- /* enable fifos */
- SET_EADDR (NETARM_ETH_GEN_CTRL,
- (NETARM_ETH_GCR_ERX | NETARM_ETH_GCR_ETX));
-
- return (0);
-}
-
-
-extern int eth_init (bd_t * bd)
-{
- reset_eth ();
- return 0;
-}
-
-extern void eth_halt (void)
-{
- SET_EADDR (NETARM_ETH_GEN_CTRL, 0);
-}
-
-/* Get a data block via Ethernet */
-extern int eth_rx (void)
-{
- int i;
- unsigned short rxlen;
- unsigned int *addr;
- unsigned int rxstatus, lastrxlen;
- char *pa;
-
- /* RXBR is 1, data block was received */
- if ((GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXBR) == 0)
- return 0;
-
- /* get status register and the length of received block */
- rxstatus = GET_EADDR (NETARM_ETH_RX_STAT);
- rxlen = (rxstatus & NETARM_ETH_RXSTAT_SIZE) >> 16;
-
- if (rxlen == 0)
- return 0;
-
- /* clear RXBR to make fifo available */
- SET_EADDR (NETARM_ETH_GEN_STAT,
- GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_RXBR);
-
- /* clear TXBC to make fifo available */
- /* According to NETARM50 data manual you just have to clear
- RXBR but that has no effect. Only after clearing TXBC the
- Fifo becomes readable. */
- SET_EADDR (NETARM_ETH_GEN_STAT,
- GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_TXBC);
-
- addr = (unsigned int *) NetRxPackets[0];
- pa = (char *) NetRxPackets[0];
-
- /* read the fifo */
- for (i = 0; i < rxlen / 4; i++) {
- *addr = GET_EADDR (NETARM_ETH_FIFO_DAT1);
- addr++;
- }
-
- if (GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXREGR) {
- /* RXFDB indicates wether the last word is 1,2,3 or 4 bytes long */
- lastrxlen =
- (GET_EADDR (NETARM_ETH_GEN_STAT) &
- NETARM_ETH_GST_RXFDB) >> 28;
- *addr = GET_EADDR (NETARM_ETH_FIFO_DAT1);
- switch (lastrxlen) {
- case 1:
- *addr &= 0xff000000;
- break;
- case 2:
- *addr &= 0xffff0000;
- break;
- case 3:
- *addr &= 0xffffff00;
- break;
- }
- }
-
- /* Pass the packet up to the protocol layers. */
- NetReceive (NetRxPackets[0], rxlen);
-
- return rxlen;
-}
-
-/* Send a data block via Ethernet. */
-extern int eth_send(void *packet, int length)
-{
- int i, length32;
- char *pa;
- unsigned int *pa32, lastp = 0, rest;
-
- pa = (char *) packet;
- pa32 = (unsigned int *) packet;
- length32 = length / 4;
- rest = length % 4;
-
- /* make sure there's no garbage in the last word */
- switch (rest) {
- case 0:
- lastp = pa32[length32];
- length32--;
- break;
- case 1:
- lastp = pa32[length32] & 0x000000ff;
- break;
- case 2:
- lastp = pa32[length32] & 0x0000ffff;
- break;
- case 3:
- lastp = pa32[length32] & 0x00ffffff;
- break;
- }
-
- /* write to the fifo */
- for (i = 0; i < length32; i++)
- SET_EADDR (NETARM_ETH_FIFO_DAT1, pa32[i]);
-
- /* the last word is written to an extra register, this
- starts the transmission */
- SET_EADDR (NETARM_ETH_FIFO_DAT2, lastp);
-
- /* NETARM_ETH_TXSTAT_TXOK should be checked, to know if the transmission
- went fine. But we can't use the timer for a timeout loop because
- of it is used already in upper layers. So we just try some times. */
- i = 0;
- while (i < 50000) {
- if ((GET_EADDR (NETARM_ETH_TX_STAT) & NETARM_ETH_TXSTAT_TXOK)
- == NETARM_ETH_TXSTAT_TXOK)
- return 0;
- i++;
- }
-
- printf ("eth_send timeout\n");
- return 1;
-}
diff --git a/drivers/net/netarm_eth.h b/drivers/net/netarm_eth.h
deleted file mode 100644
index 8edab82..0000000
--- a/drivers/net/netarm_eth.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2003 IMMS gGmbH <www.imms.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * author(s): Thomas Elste, <info@elste.org>
- */
-
-#include <asm/types.h>
-#include <config.h>
-
-#ifdef CONFIG_DRIVER_NETARMETH
-
-#define SET_EADDR(ad,val) *(volatile unsigned int*)(ad + NETARM_ETH_MODULE_BASE) = val
-#define GET_EADDR(ad) (*(volatile unsigned int*)(ad + NETARM_ETH_MODULE_BASE))
-
-#define NA_MII_POLL_BUSY_DELAY 900
-
-/* MII negotiation timeout value
- 500 jiffies = 5 seconds */
-#define NA_MII_NEGOTIATE_DELAY 30
-
-/* Registers in the physical layer chip */
-#define MII_PHY_CONTROL 0
-#define MII_PHY_STATUS 1
-#define MII_PHY_ID 2
-#define MII_PHY_AUTONEGADV 4
-
-#endif /* CONFIG_DRIVER_NETARMETH */
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 920ce69..5e8b648 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -36,18 +36,14 @@ COBJS-$(CONFIG_MCFUART) += mcfuart.o
COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o
COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
COBJS-$(CONFIG_SYS_NS16550) += ns16550.o
-COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o
COBJS-$(CONFIG_S3C64XX) += s3c64xx.o
COBJS-$(CONFIG_S5P) += serial_s5p.o
COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o
-COBJS-$(CONFIG_CLPS7111_SERIAL) += serial_clps7111.o
COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o
COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o
COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o
-COBJS-$(CONFIG_LPC2292_SERIAL) += serial_lpc2292.o
COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
COBJS-$(CONFIG_MXC_UART) += serial_mxc.o
-COBJS-$(CONFIG_NETARM_SERIAL) += serial_netarm.o
COBJS-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
COBJS-$(CONFIG_PXA_SERIAL) += serial_pxa.o
diff --git a/drivers/serial/s3c4510b_uart.c b/drivers/serial/s3c4510b_uart.c
deleted file mode 100644
index c460229..0000000
--- a/drivers/serial/s3c4510b_uart.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
- * Curt Brune <curt@cucy.com>
- *
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * (C) Copyright 2002-2004
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * MODULE: $Id:$
- * Description: UART/Serial interface for Samsung S3C4510B SoC
- * Runtime Env: ARM7TDMI
- * Change History:
- * 03-02-04 Create (Curt Brune) curt@cucy.com
- *
- */
-
-#include <common.h>
-
-#include <asm/hardware.h>
-#include "s3c4510b_uart.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static UART *uart;
-
-/* flush serial input queue. returns 0 on success or negative error
- * number otherwise
- */
-static int serial_flush_input(void)
-{
- volatile u32 tmp;
-
- /* keep on reading as long as the receiver is not empty */
- while( uart->m_stat.bf.rxReady) {
- tmp = uart->m_rx;
- }
-
- return 0;
-}
-
-
-/* flush output queue. returns 0 on success or negative error number
- * otherwise
- */
-static int serial_flush_output(void)
-{
- /* wait until the transmitter is no longer busy */
- while( !uart->m_stat.bf.txBufEmpty);
-
- return 0;
-}
-
-
-static void s3c4510b_serial_setbrg(void)
-{
- UART_LINE_CTRL ulctrl;
- UART_CTRL uctrl;
- UART_BAUD_DIV ubd;
-
- serial_flush_output();
- serial_flush_input();
-
- /* control register */
- uctrl.ui = 0x0;
- uctrl.bf.rxMode = 0x1;
- uctrl.bf.rxIrq = 0x0;
- uctrl.bf.txMode = 0x1;
- uctrl.bf.DSR = 0x0;
- uctrl.bf.sendBreak = 0x0;
- uctrl.bf.loopBack = 0x0;
- uart->m_ctrl.ui = uctrl.ui;
-
- /* line control register */
- ulctrl.ui = 0x0;
- ulctrl.bf.wordLen = 0x3; /* 8 bit data */
- ulctrl.bf.nStop = 0x0; /* 1 stop bit */
- ulctrl.bf.parity = 0x0; /* no parity */
- ulctrl.bf.clk = 0x0; /* internal clock */
- ulctrl.bf.infra_red = 0x0; /* no infra_red */
- uart->m_lineCtrl.ui = ulctrl.ui;
-
- ubd.ui = 0x0;
-
- /* see table on page 10-15 in SAMSUNG S3C4510B manual */
- /* get correct divisor */
- switch(gd->baudrate) {
- case 1200: ubd.bf.cnt0 = 1301; break;
- case 2400: ubd.bf.cnt0 = 650; break;
- case 4800: ubd.bf.cnt0 = 324; break;
- case 9600: ubd.bf.cnt0 = 162; break;
- case 19200: ubd.bf.cnt0 = 80; break;
- case 38400: ubd.bf.cnt0 = 40; break;
- case 57600: ubd.bf.cnt0 = 26; break;
- case 115200: ubd.bf.cnt0 = 13; break;
- }
-
- uart->m_baudDiv.ui = ubd.ui;
- uart->m_baudCnt = 0x0;
- uart->m_baudClk = 0x0;
-
-}
-
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-static int s3c4510b_serial_init(void)
-{
-
-#if CONFIG_SERIAL1 == 1
- uart = (UART *)UART0_BASE;
-#elif CONFIG_SERIAL1 == 2
- uart = (UART *)UART1_BASE;
-#else
-#error CONFIG_SERIAL1 not equal to 1 or 2
-#endif
-
- serial_setbrg ();
-
- return (0);
-}
-
-
-/*
- * Output a single byte to the serial port.
- */
-static void s3c4510_serial_putc(const char c)
-{
- /* wait for room in the transmit FIFO */
- while( !uart->m_stat.bf.txBufEmpty);
-
- uart->m_tx = c;
-
- /*
- to be polite with serial console add a line feed
- to the carriage return character
- */
- if (c=='\n')
- serial_putc('\r');
-}
-
-/*
- * Test if an input byte is ready from the serial port. Returns non-zero on
- * success, 0 otherwise.
- */
-static int s3c4510b_serial_tstc(void)
-{
- return uart->m_stat.bf.rxReady;
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-static int s3c4510b_serial_getc(void)
-{
- int rv;
-
- for(;;) {
- rv = serial_tstc();
-
- if (rv) {
- return uart->m_rx & 0xFF;
- }
- }
-}
-
-static void s3c4510b_serial_puts(const char *s)
-{
- default_serial_puts(s);
-
- /* busy wait for tx complete */
- while (!uart->m_stat.bf.txComplete);
-
- /* clear break */
- uart->m_ctrl.bf.sendBreak = 0;
-
-}
-
-static struct serial_device s3c4510b_serial_drv = {
- .name = "s3c4510b_serial",
- .start = s3c4510b_serial_init,
- .stop = NULL,
- .setbrg = s3c4510b_serial_setbrg,
- .putc = s3c4510b_serial_putc,
- .puts = s3c4510b_serial_puts,
- .getc = s3c4510b_serial_getc,
- .tstc = s3c4510b_serial_tstc,
-};
-
-void s3c4510b_serial_initialize(void)
-{
- serial_register(&s3c4510b_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &s3c4510b_serial_drv;
-}
diff --git a/drivers/serial/s3c4510b_uart.h b/drivers/serial/s3c4510b_uart.h
deleted file mode 100644
index b06c76d..0000000
--- a/drivers/serial/s3c4510b_uart.h
+++ /dev/null
@@ -1,109 +0,0 @@
-#ifndef __UART_H
-#define __UART_H
-
-/*
- * Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
- * Curt Brune <curt@cucy.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Description: S3C4510B UART register layout
- */
-
-/* UART LINE CONTROL register */
-typedef struct __BF_UART_LINE_CTRL {
- u32 wordLen: 2;
- u32 nStop: 1;
- u32 parity: 3;
- u32 clk: 1;
- u32 infra_red: 1;
- u32 unused:24;
-} BF_UART_LINE_CTRL;
-
-typedef union _UART_LINE_CTRL {
- u32 ui;
- BF_UART_LINE_CTRL bf;
-} UART_LINE_CTRL;
-
-/* UART CONTROL register */
-typedef struct __BF_UART_CTRL {
- u32 rxMode: 2;
- u32 rxIrq: 1;
- u32 txMode: 2;
- u32 DSR: 1;
- u32 sendBreak: 1;
- u32 loopBack: 1;
- u32 unused:24;
-} BF_UART_CTRL;
-
-typedef union _UART_CTRL {
- u32 ui;
- BF_UART_CTRL bf;
-} UART_CTRL;
-
-/* UART STATUS register */
-typedef struct __BF_UART_STAT {
- u32 overrun: 1;
- u32 parity: 1;
- u32 frame: 1;
- u32 breakIrq: 1;
- u32 DTR: 1;
- u32 rxReady: 1;
- u32 txBufEmpty: 1;
- u32 txComplete: 1;
- u32 unused:24;
-} BF_UART_STAT;
-
-typedef union _UART_STAT {
- u32 ui;
- BF_UART_STAT bf;
-} UART_STAT;
-
-/* UART BAUD_DIV register */
-typedef struct __BF_UART_BAUD_DIV {
- u32 cnt1: 4;
- u32 cnt0:12;
- u32 unused:16;
-} BF_UART_BAUD_DIV;
-
-typedef union _UART_BAUD_DIV {
- u32 ui;
- BF_UART_BAUD_DIV bf;
-} UART_BAUD_DIV;
-
-/* UART register block */
-typedef struct __UART {
- volatile UART_LINE_CTRL m_lineCtrl;
- volatile UART_CTRL m_ctrl;
- volatile UART_STAT m_stat;
- volatile u32 m_tx;
- volatile u32 m_rx;
- volatile UART_BAUD_DIV m_baudDiv;
- volatile u32 m_baudCnt;
- volatile u32 m_baudClk;
-} UART;
-
-#define NL 0x0A
-#define CR 0x0D
-#define BSP 0x08
-#define ESC 0x1B
-#define CTRLZ 0x1A
-#define RUBOUT 0x7F
-
-#endif
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index e0886d5..f5f43a6 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -96,7 +96,6 @@ serial_initfunc(lpc32xx_serial_initialize);
serial_initfunc(mcf_serial_initialize);
serial_initfunc(ns9750_serial_initialize);
serial_initfunc(oc_serial_initialize);
-serial_initfunc(s3c4510b_serial_initialize);
serial_initfunc(s3c64xx_serial_initialize);
serial_initfunc(sandbox_serial_initialize);
serial_initfunc(clps7111_serial_initialize);
@@ -104,10 +103,8 @@ serial_initfunc(imx_serial_initialize);
serial_initfunc(ixp_serial_initialize);
serial_initfunc(ks8695_serial_initialize);
serial_initfunc(lh7a40x_serial_initialize);
-serial_initfunc(lpc2292_serial_initialize);
serial_initfunc(max3100_serial_initialize);
serial_initfunc(mxc_serial_initialize);
-serial_initfunc(netarm_serial_initialize);
serial_initfunc(pl01x_serial_initialize);
serial_initfunc(s3c44b0_serial_initialize);
serial_initfunc(sa1100_serial_initialize);
@@ -194,7 +191,6 @@ void serial_initialize(void)
mcf_serial_initialize();
ns9750_serial_initialize();
oc_serial_initialize();
- s3c4510b_serial_initialize();
s3c64xx_serial_initialize();
sandbox_serial_initialize();
clps7111_serial_initialize();
@@ -202,10 +198,8 @@ void serial_initialize(void)
ixp_serial_initialize();
ks8695_serial_initialize();
lh7a40x_serial_initialize();
- lpc2292_serial_initialize();
max3100_serial_initialize();
mxc_serial_initialize();
- netarm_serial_initialize();
pl01x_serial_initialize();
s3c44b0_serial_initialize();
sa1100_serial_initialize();
diff --git a/drivers/serial/serial_clps7111.c b/drivers/serial/serial_clps7111.c
deleted file mode 100644
index c292ed8..0000000
--- a/drivers/serial/serial_clps7111.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * (C) Copyright 2002-2004
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <clps7111.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void clps7111_serial_setbrg(void)
-{
- unsigned int reg = 0;
-
- switch (gd->baudrate) {
- case 1200: reg = 191; break;
- case 9600: reg = 23; break;
- case 19200: reg = 11; break;
- case 38400: reg = 5; break;
- case 57600: reg = 3; break;
- case 115200: reg = 1; break;
- default: hang (); break;
- }
-
- /* init serial serial 1,2 */
- IO_SYSCON1 = SYSCON1_UART1EN;
- IO_SYSCON2 = SYSCON2_UART2EN;
-
- reg |= UBRLCR_WRDLEN8;
-
- IO_UBRLCR1 = reg;
- IO_UBRLCR2 = reg;
-}
-
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-static int clps7111_serial_init(void)
-{
- serial_setbrg ();
-
- return (0);
-}
-
-
-/*
- * Output a single byte to the serial port.
- */
-static void clps7111_serial_putc(const char c)
-{
- int tmo;
-
- /* If \n, also do \r */
- if (c == '\n')
- serial_putc ('\r');
-
- tmo = get_timer (0) + 1 * CONFIG_SYS_HZ;
- while (IO_SYSFLG1 & SYSFLG1_UTXFF)
- if (get_timer (0) > tmo)
- break;
-
- IO_UARTDR1 = c;
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-static int clps7111_serial_tstc(void)
-{
- return !(IO_SYSFLG1 & SYSFLG1_URXFE);
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-static int clps7111_serial_getc(void)
-{
- while (IO_SYSFLG1 & SYSFLG1_URXFE);
-
- return IO_UARTDR1 & 0xff;
-}
-
-static struct serial_device clps7111_serial_drv = {
- .name = "clps7111_serial",
- .start = clps7111_serial_init,
- .stop = NULL,
- .setbrg = clps7111_serial_setbrg,
- .putc = clps7111_serial_putc,
- .puts = default_serial_puts,
- .getc = clps7111_serial_getc,
- .tstc = clps7111_serial_tstc,
-};
-
-void clps7111_serial_initialize(void)
-{
- serial_register(&clps7111_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &clps7111_serial_drv;
-}
diff --git a/drivers/serial/serial_lpc2292.c b/drivers/serial/serial_lpc2292.c
deleted file mode 100644
index 8abc476..0000000
--- a/drivers/serial/serial_lpc2292.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * (C) Copyright 2002-2004
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void lpc2292_serial_setbrg(void)
-{
- unsigned short divisor = 0;
-
- switch (gd->baudrate) {
- case 1200: divisor = 3072; break;
- case 9600: divisor = 384; break;
- case 19200: divisor = 192; break;
- case 38400: divisor = 96; break;
- case 57600: divisor = 64; break;
- case 115200: divisor = 32; break;
- default: hang (); break;
- }
-
- /* init serial UART0 */
- PUT8(U0LCR, 0);
- PUT8(U0IER, 0);
- PUT8(U0LCR, 0x80); /* DLAB=1 */
- PUT8(U0DLL, (unsigned char)(divisor & 0x00FF));
- PUT8(U0DLM, (unsigned char)(divisor >> 8));
- PUT8(U0LCR, 0x03); /* 8N1, DLAB=0 */
- PUT8(U0FCR, 1); /* Enable RX and TX FIFOs */
-}
-
-static int lpc2292_serial_init(void)
-{
- unsigned long pinsel0;
-
- serial_setbrg ();
-
- pinsel0 = GET32(PINSEL0);
- pinsel0 &= ~(0x00000003);
- pinsel0 |= 5;
- PUT32(PINSEL0, pinsel0);
-
- return (0);
-}
-
-static void lpc2292_serial_putc(const char c)
-{
- if (c == '\n')
- {
- while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */
- PUT8(U0THR, '\r');
- }
-
- while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */
- PUT8(U0THR, c);
-}
-
-static int lpc2292_serial_getc(void)
-{
- while((GET8(U0LSR) & 1) == 0);
- return GET8(U0RBR);
-}
-
-/* Test if there is a byte to read */
-static int lpc2292_serial_tstc(void)
-{
- return (GET8(U0LSR) & 1);
-}
-
-static struct serial_device lpc2292_serial_drv = {
- .name = "lpc2292_serial",
- .start = lpc2292_serial_init,
- .stop = NULL,
- .setbrg = lpc2292_serial_setbrg,
- .putc = lpc2292_serial_putc,
- .puts = default_serial_puts,
- .getc = lpc2292_serial_getc,
- .tstc = lpc2292_serial_tstc,
-};
-
-void lpc2292_serial_initialize(void)
-{
- serial_register(&lpc2292_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &lpc2292_serial_drv;
-}
diff --git a/drivers/serial/serial_netarm.c b/drivers/serial/serial_netarm.c
deleted file mode 100644
index 44d7c50..0000000
--- a/drivers/serial/serial_netarm.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * Serial Port stuff - taken from Linux
- *
- * (C) Copyright 2002
- * MAZeT GmbH <www.mazet.de>
- * Stephan Linz <linz@mazet.de>, <linz@li-pro.net>
- *
- * (c) 2004
- * IMMS gGmbH <www.imms.de>
- * Thomas Elste <info@elste.org>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <asm/hardware.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define PORTA (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTA))
-#if !defined(CONFIG_NETARM_NS7520)
-#define PORTB (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTB))
-#else
-#define PORTC (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTC))
-#endif
-
-/* wait until transmitter is ready for another character */
-#define TXWAITRDY(registers) \
-{ \
- ulong tmo = get_timer(0) + 1 * CONFIG_SYS_HZ; \
- while (((registers)->status_a & NETARM_SER_STATA_TX_RDY) == 0 ) { \
- if (get_timer(0) > tmo) \
- break; \
- } \
-}
-
-
-volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(0);
-volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(1);
-
-extern void _netarm_led_FAIL1(void);
-
-/*
- * Setup both serial i/f with given baudrate
- */
-static void netarm_serial_setbrg(void)
-{
- /* set 0 ... make sure pins are configured for serial */
-#if !defined(CONFIG_NETARM_NS7520)
- PORTA = PORTB =
- NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0);
-#else
- PORTA = NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0);
- PORTC = NETARM_GEN_PORT_CSF (0xef) | NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0);
-#endif
-
- /* first turn em off */
- serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = 0;
-
- /* clear match register, we don't need it */
- serial_reg_ch1->rx_match = serial_reg_ch2->rx_match = 0;
-
- /* setup bit rate generator and rx buffer gap timer (1 byte only) */
- if ((gd->baudrate >= MIN_BAUD_RATE)
- && (gd->baudrate <= MAX_BAUD_RATE)) {
- serial_reg_ch1->bitrate = serial_reg_ch2->bitrate =
- NETARM_SER_BR_X16 (gd->baudrate);
- serial_reg_ch1->rx_buf_timer = serial_reg_ch2->rx_buf_timer =
- 0;
- serial_reg_ch1->rx_char_timer = serial_reg_ch2->rx_char_timer =
- NETARM_SER_RXGAP (gd->baudrate);
- } else {
- hang ();
- }
-
- /* setup port mode */
- serial_reg_ch1->ctrl_b = serial_reg_ch2->ctrl_b =
- ( NETARM_SER_CTLB_RCGT_EN |
- NETARM_SER_CTLB_UART_MODE);
- serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a =
- ( NETARM_SER_CTLA_ENABLE |
- NETARM_SER_CTLA_P_NONE |
- /* see errata */
- NETARM_SER_CTLA_2STOP |
- NETARM_SER_CTLA_8BITS |
- NETARM_SER_CTLA_DTR_EN |
- NETARM_SER_CTLA_RTS_EN);
-}
-
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- */
-static int netarm_serial_init(void)
-{
- serial_setbrg ();
- return 0;
-}
-
-
-/*
- * Output a single byte to the serial port.
- */
-static void netarm_serial_putc(const char c)
-{
- volatile unsigned char *fifo;
-
- /* If \n, also do \r */
- if (c == '\n')
- serial_putc ('\r');
-
- fifo = (volatile unsigned char *) &(serial_reg_ch1->fifo);
- TXWAITRDY (serial_reg_ch1);
- *fifo = c;
-}
-
-/*
- * Test of a single byte from the serial port. Returns 1 on success, 0
- * otherwise.
- */
-static int netarm_serial_tstc(void)
-{
- return serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY;
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise.
- */
-static int netarm_serial_getc(void)
-{
- unsigned int ch_uint;
- volatile unsigned int *fifo;
- volatile unsigned char *fifo_char = NULL;
- int buf_count = 0;
-
- while (!(serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY))
- /* NOP */ ;
-
- fifo = (volatile unsigned int *) &(serial_reg_ch1->fifo);
- fifo_char = (unsigned char *) &ch_uint;
- ch_uint = *fifo;
-
- buf_count = NETARM_SER_STATA_RXFDB (serial_reg_ch1->status_a);
- switch (buf_count) {
- case NETARM_SER_STATA_RXFDB_4BYTES:
- buf_count = 4;
- break;
- case NETARM_SER_STATA_RXFDB_3BYTES:
- buf_count = 3;
- break;
- case NETARM_SER_STATA_RXFDB_2BYTES:
- buf_count = 2;
- break;
- case NETARM_SER_STATA_RXFDB_1BYTES:
- buf_count = 1;
- break;
- default:
- /* panic, be never here */
- break;
- }
-
- serial_reg_ch1->status_a |= NETARM_SER_STATA_RX_CLOSED;
-
- return ch_uint & 0xff;
-}
-
-static struct serial_device netarm_serial_drv = {
- .name = "netarm_serial",
- .start = netarm_serial_init,
- .stop = NULL,
- .setbrg = netarm_serial_setbrg,
- .putc = netarm_serial_putc,
- .puts = default_serial_puts,
- .getc = netarm_serial_getc,
- .tstc = netarm_serial_tstc,
-};
-
-void netarm_serial_initialize(void)
-{
- serial_register(&netarm_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &netarm_serial_drv;
-}
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index e40a632..6791a7e 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -173,14 +173,13 @@ int spi_claim_bus(struct spi_slave *slave)
/* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
* REVISIT: this controller could support SPI_3WIRE mode.
*/
-#ifdef CONFIG_AM33XX
+#ifdef CONFIG_OMAP3_SPI_D0_D1_SWAPPED
/*
- * The reference design on AM33xx has D0 and D1 wired up opposite
- * of how it has been done on previous platforms. We assume that
- * custom hardware will also follow this convention.
+ * Some boards have D0 wired as MOSI / D1 as MISO instead of
+ * The normal D0 as MISO / D1 as MOSI.
*/
- conf &= OMAP3_MCSPI_CHCONF_DPE0;
- conf |= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
+ conf &= ~OMAP3_MCSPI_CHCONF_DPE0;
+ conf |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
#else
conf &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
conf |= OMAP3_MCSPI_CHCONF_DPE0;
diff --git a/drivers/usb/musb/musb_udc.c b/drivers/usb/musb/musb_udc.c
index 09cdec3..e0b4217 100644
--- a/drivers/usb/musb/musb_udc.c
+++ b/drivers/usb/musb/musb_udc.c
@@ -640,8 +640,17 @@ static void musb_peri_ep0(void)
static void musb_peri_rx_ep(unsigned int ep)
{
- u16 peri_rxcount = readw(&musbr->ep[ep].epN.rxcount);
+ u16 peri_rxcount;
+ u8 peri_rxcsr = readw(&musbr->ep[ep].epN.rxcsr);
+ if (!(peri_rxcsr & MUSB_RXCSR_RXPKTRDY)) {
+ if (debug_level > 0)
+ serial_printf("ERROR : %s %d without MUSB_RXCSR_RXPKTRDY set\n",
+ __PRETTY_FUNCTION__, ep);
+ return;
+ }
+
+ peri_rxcount = readw(&musbr->ep[ep].epN.rxcount);
if (peri_rxcount) {
struct usb_endpoint_instance *endpoint;
u32 length;
generated by cgit v1.1 at 2024-12-05 00:35:03 +0000