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-rw-r--r--drivers/serial/Makefile1
-rw-r--r--drivers/serial/serial_lh7a40x.c197
-rw-r--r--drivers/usb/gadget/gadget_chips.h34
-rw-r--r--drivers/usb/host/Makefile1
-rw-r--r--drivers/usb/host/ohci-s3c24xx.c1801
-rw-r--r--drivers/usb/host/ohci-s3c24xx.h409
-rw-r--r--drivers/watchdog/Makefile1
-rw-r--r--drivers/watchdog/tnetv107x_wdt.c180
8 files changed, 2405 insertions, 219 deletions
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 3c32f97..920ce69 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -45,7 +45,6 @@ COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o
COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o
COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o
COBJS-$(CONFIG_LPC2292_SERIAL) += serial_lpc2292.o
-COBJS-$(CONFIG_LH7A40X_SERIAL) += serial_lh7a40x.o
COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
COBJS-$(CONFIG_MXC_UART) += serial_mxc.o
COBJS-$(CONFIG_NETARM_SERIAL) += serial_netarm.o
diff --git a/drivers/serial/serial_lh7a40x.c b/drivers/serial/serial_lh7a40x.c
deleted file mode 100644
index 68e958b..0000000
--- a/drivers/serial/serial_lh7a40x.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <lh7a40x.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CONSOLE_UART1)
-# define UART_CONSOLE 1
-#elif defined(CONFIG_CONSOLE_UART2)
-# define UART_CONSOLE 2
-#elif defined(CONFIG_CONSOLE_UART3)
-# define UART_CONSOLE 3
-#else
-# error "No console configured ... "
-#endif
-
-static void lh7a40x_serial_setbrg(void)
-{
- lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
- int i;
- unsigned int reg = 0;
-
- /*
- * userguide 15.1.2.4
- *
- * BAUDDIV is (UART_REF_FREQ/(16 X BAUD))-1
- *
- * UART_REF_FREQ = external system clock input / 2 (Hz)
- * BAUD is desired baudrate (bits/s)
- *
- * NOTE: we add (divisor/2) to numerator to round for
- * more precision
- */
- reg = (((get_PLLCLK()/2) + ((16*gd->baudrate)/2)) / (16 * gd->baudrate)) - 1;
- uart->brcon = reg;
-
- for (i = 0; i < 100; i++);
-}
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-static int lh7a40x_serial_init(void)
-{
- lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-
- /* UART must be enabled before writing to any config registers */
- uart->con |= (UART_EN);
-
-#ifdef CONFIG_CONSOLE_UART1
- /* infrared disabled */
- uart->con |= UART_SIRD;
-#endif
- /* loopback disabled */
- uart->con &= ~(UART_LBE);
-
- /* modem lines and tx/rx polarities */
- uart->con &= ~(UART_MXP | UART_TXP | UART_RXP);
-
- /* FIFO enable, N81 */
- uart->fcon = (UART_WLEN_8 | UART_FEN | UART_STP2_1);
-
- /* set baudrate */
- serial_setbrg ();
-
- /* enable rx interrupt */
- uart->inten |= UART_RI;
-
- return (0);
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-static int lh7a40x_serial_getc(void)
-{
- lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-
- /* wait for character to arrive */
- while (uart->status & UART_RXFE);
-
- return(uart->data & 0xff);
-}
-
-#ifdef CONFIG_HWFLOW
-static int hwflow = 0; /* turned off by default */
-int hwflow_onoff(int on)
-{
- switch(on) {
- case 0:
- default:
- break; /* return current */
- case 1:
- hwflow = 1; /* turn on */
- break;
- case -1:
- hwflow = 0; /* turn off */
- break;
- }
- return hwflow;
-}
-#endif
-
-#ifdef CONFIG_MODEM_SUPPORT
-static int be_quiet = 0;
-void disable_putc(void)
-{
- be_quiet = 1;
-}
-
-void enable_putc(void)
-{
- be_quiet = 0;
-}
-#endif
-
-
-/*
- * Output a single byte to the serial port.
- */
-static void lh7a40x_serial_putc(const char c)
-{
- lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-
-#ifdef CONFIG_MODEM_SUPPORT
- if (be_quiet)
- return;
-#endif
-
- /* wait for room in the tx FIFO */
- while (!(uart->status & UART_TXFE));
-
-#ifdef CONFIG_HWFLOW
- /* Wait for CTS up */
- while(hwflow && !(uart->status & UART_CTS));
-#endif
-
- uart->data = c;
-
- /* If \n, also do \r */
- if (c == '\n')
- serial_putc ('\r');
-}
-
-/*
- * Test whether a character is in the RX buffer
- */
-static int lh7a40x_serial_tstc(void)
-{
- lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-
- return(!(uart->status & UART_RXFE));
-}
-
-static struct serial_device lh7a40x_serial_drv = {
- .name = "lh7a40x_serial",
- .start = lh7a40x_serial_init,
- .stop = NULL,
- .setbrg = lh7a40x_serial_setbrg,
- .putc = lh7a40x_serial_putc,
- .puts = default_serial_puts,
- .getc = lh7a40x_serial_getc,
- .tstc = lh7a40x_serial_tstc,
-};
-
-void lh7a40x_serial_initialize(void)
-{
- serial_register(&lh7a40x_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &lh7a40x_serial_drv;
-}
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
index 5d7b638..02cae0f 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -58,12 +58,6 @@
#define gadget_is_sa1100(g) 0
#endif
-#ifdef CONFIG_USB_GADGET_LH7A40X
-#define gadget_is_lh7a40x(g) (!strcmp("lh7a40x_udc", (g)->name))
-#else
-#define gadget_is_lh7a40x(g) 0
-#endif
-
/* handhelds.org tree (?) */
#ifdef CONFIG_USB_GADGET_MQ11XX
#define gadget_is_mq11xx(g) (!strcmp("mq11xx_udc", (g)->name))
@@ -195,33 +189,31 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
return 0x07;
else if (gadget_is_omap(gadget))
return 0x08;
- else if (gadget_is_lh7a40x(gadget))
- return 0x09;
else if (gadget_is_n9604(gadget))
- return 0x10;
+ return 0x09;
else if (gadget_is_pxa27x(gadget))
- return 0x11;
+ return 0x10;
else if (gadget_is_s3c2410(gadget))
- return 0x12;
+ return 0x11;
else if (gadget_is_at91(gadget))
- return 0x13;
+ return 0x12;
else if (gadget_is_imx(gadget))
- return 0x14;
+ return 0x13;
else if (gadget_is_musbhsfc(gadget))
- return 0x15;
+ return 0x14;
else if (gadget_is_musbhdrc(gadget))
- return 0x16;
+ return 0x15;
else if (gadget_is_mpc8272(gadget))
- return 0x17;
+ return 0x16;
else if (gadget_is_atmel_usba(gadget))
- return 0x18;
+ return 0x17;
else if (gadget_is_fsl_usb2(gadget))
- return 0x19;
+ return 0x18;
else if (gadget_is_amd5536udc(gadget))
- return 0x20;
+ return 0x19;
else if (gadget_is_m66592(gadget))
- return 0x21;
+ return 0x20;
else if (gadget_is_mv(gadget))
- return 0x22;
+ return 0x21;
return -ENOENT;
}
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index bcb4662..6c94794 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -33,6 +33,7 @@ COBJS-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o
COBJS-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
COBJS-$(CONFIG_USB_S3C64XX) += s3c64xx-hcd.o
COBJS-$(CONFIG_USB_SL811HS) += sl811-hcd.o
+COBJS-$(CONFIG_USB_OHCI_S3C24XX) += ohci-s3c24xx.o
# echi
COBJS-$(CONFIG_USB_EHCI) += ehci-hcd.o
diff --git a/drivers/usb/host/ohci-s3c24xx.c b/drivers/usb/host/ohci-s3c24xx.c
new file mode 100644
index 0000000..03cd4c3
--- /dev/null
+++ b/drivers/usb/host/ohci-s3c24xx.c
@@ -0,0 +1,1801 @@
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB on the S3C2400.
+ *
+ * (C) Copyright 2003
+ * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
+ *
+ * Note: Much of this code has been derived from Linux 2.4
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2002 David Brownell
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/*
+ * IMPORTANT NOTES
+ * 1 - this driver is intended for use with USB Mass Storage Devices
+ * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
+ */
+
+#include <common.h>
+/* #include <pci.h> no PCI on the S3C24X0 */
+
+#if defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0)
+
+#include <asm/arch/s3c24x0_cpu.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <usb.h>
+#include "ohci-s3c24xx.h"
+
+#define OHCI_USE_NPS /* force NoPowerSwitching mode */
+#undef OHCI_VERBOSE_DEBUG /* not always helpful */
+
+
+/* For initializing controller (mask in an HCFS mode too) */
+#define OHCI_CONTROL_INIT \
+ (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
+
+#define min_t(type, x, y) \
+ ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
+
+#undef DEBUG
+#ifdef DEBUG
+#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
+#else
+#define dbg(format, arg...) do {} while(0)
+#endif /* DEBUG */
+#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
+#undef SHOW_INFO
+#ifdef SHOW_INFO
+#define info(format, arg...) printf("INFO: " format "\n", ## arg)
+#else
+#define info(format, arg...) do {} while(0)
+#endif
+
+#define m16_swap(x) swap_16(x)
+#define m32_swap(x) swap_32(x)
+
+/* global struct ohci */
+static struct ohci gohci;
+/* this must be aligned to a 256 byte boundary */
+struct ohci_hcca ghcca[1];
+/* a pointer to the aligned storage */
+struct ohci_hcca *phcca;
+/* this allocates EDs for all possible endpoints */
+struct ohci_device ohci_dev;
+/* urb_priv */
+struct urb_priv urb_priv;
+/* RHSC flag */
+int got_rhsc;
+/* device which was disconnected */
+struct usb_device *devgone;
+/* flag guarding URB transation */
+int urb_finished = 0;
+
+/*-------------------------------------------------------------------------*/
+
+/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
+ * The erratum (#4) description is incorrect. AMD's workaround waits
+ * till some bits (mostly reserved) are clear; ok for all revs.
+ */
+#define OHCI_QUIRK_AMD756 0xabcd
+#define read_roothub(hc, register, mask) ({ \
+ u32 temp = readl (&hc->regs->roothub.register); \
+ if (hc->flags & OHCI_QUIRK_AMD756) \
+ while (temp & mask) \
+ temp = readl (&hc->regs->roothub.register); \
+ temp; })
+
+static u32 roothub_a(struct ohci *hc)
+{
+ return read_roothub(hc, a, 0xfc0fe000);
+}
+static inline u32 roothub_b(struct ohci *hc)
+{
+ return readl(&hc->regs->roothub.b);
+}
+static inline u32 roothub_status(struct ohci *hc)
+{
+ return readl(&hc->regs->roothub.status);
+}
+static u32 roothub_portstatus(struct ohci *hc, int i)
+{
+ return read_roothub(hc, portstatus[i], 0xffe0fce0);
+}
+
+/* forward declaration */
+static int hc_interrupt(void);
+static void td_submit_job(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len,
+ struct devrequest *setup, struct urb_priv *urb,
+ int interval);
+
+/*-------------------------------------------------------------------------*
+ * URB support functions
+ *-------------------------------------------------------------------------*/
+
+/* free HCD-private data associated with this URB */
+
+static void urb_free_priv(struct urb_priv *urb)
+{
+ int i;
+ int last;
+ struct td *td;
+
+ last = urb->length - 1;
+ if (last >= 0) {
+ for (i = 0; i <= last; i++) {
+ td = urb->td[i];
+ if (td) {
+ td->usb_dev = NULL;
+ urb->td[i] = NULL;
+ }
+ }
+ }
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef DEBUG
+static int sohci_get_current_frame_number(struct usb_device *dev);
+
+/* debug| print the main components of an URB
+ * small: 0) header + data packets 1) just header */
+
+static void pkt_print(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup, char *str,
+ int small)
+{
+ struct urb_priv *purb = &urb_priv;
+
+ dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
+ str,
+ sohci_get_current_frame_number(dev),
+ usb_pipedevice(pipe),
+ usb_pipeendpoint(pipe),
+ usb_pipeout(pipe) ? 'O' : 'I',
+ usb_pipetype(pipe) < 2 ?
+ (usb_pipeint(pipe) ? "INTR" : "ISOC") :
+ (usb_pipecontrol(pipe) ? "CTRL" : "BULK"),
+ purb->actual_length, transfer_len, dev->status);
+#ifdef OHCI_VERBOSE_DEBUG
+ if (!small) {
+ int i, len;
+
+ if (usb_pipecontrol(pipe)) {
+ printf(__FILE__ ": cmd(8):");
+ for (i = 0; i < 8; i++)
+ printf(" %02x", ((__u8 *) setup)[i]);
+ printf("\n");
+ }
+ if (transfer_len > 0 && buffer) {
+ printf(__FILE__ ": data(%d/%d):",
+ purb->actual_length, transfer_len);
+ len = usb_pipeout(pipe) ?
+ transfer_len : purb->actual_length;
+ for (i = 0; i < 16 && i < len; i++)
+ printf(" %02x", ((__u8 *) buffer)[i]);
+ printf("%s\n", i < len ? "..." : "");
+ }
+ }
+#endif
+}
+
+/* just for debugging; prints non-empty branches of the
+ int ed tree inclusive iso eds*/
+void ep_print_int_eds(struct ohci *ohci, char *str)
+{
+ int i, j;
+ __u32 *ed_p;
+ for (i = 0; i < 32; i++) {
+ j = 5;
+ ed_p = &(ohci->hcca->int_table[i]);
+ if (*ed_p == 0)
+ continue;
+ printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i);
+ while (*ed_p != 0 && j--) {
+ struct ed *ed = (struct ed *) m32_swap(ed_p);
+ printf(" ed: %4x;", ed->hwINFO);
+ ed_p = &ed->hwNextED;
+ }
+ printf("\n");
+ }
+}
+
+static void ohci_dump_intr_mask(char *label, __u32 mask)
+{
+ dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
+ label,
+ mask,
+ (mask & OHCI_INTR_MIE) ? " MIE" : "",
+ (mask & OHCI_INTR_OC) ? " OC" : "",
+ (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
+ (mask & OHCI_INTR_FNO) ? " FNO" : "",
+ (mask & OHCI_INTR_UE) ? " UE" : "",
+ (mask & OHCI_INTR_RD) ? " RD" : "",
+ (mask & OHCI_INTR_SF) ? " SF" : "",
+ (mask & OHCI_INTR_WDH) ? " WDH" : "",
+ (mask & OHCI_INTR_SO) ? " SO" : "");
+}
+
+static void maybe_print_eds(char *label, __u32 value)
+{
+ struct ed *edp = (struct ed *) value;
+
+ if (value) {
+ dbg("%s %08x", label, value);
+ dbg("%08x", edp->hwINFO);
+ dbg("%08x", edp->hwTailP);
+ dbg("%08x", edp->hwHeadP);
+ dbg("%08x", edp->hwNextED);
+ }
+}
+
+static char *hcfs2string(int state)
+{
+ switch (state) {
+ case OHCI_USB_RESET:
+ return "reset";
+ case OHCI_USB_RESUME:
+ return "resume";
+ case OHCI_USB_OPER:
+ return "operational";
+ case OHCI_USB_SUSPEND:
+ return "suspend";
+ }
+ return "?";
+}
+
+/* dump control and status registers */
+static void ohci_dump_status(struct ohci *controller)
+{
+ struct ohci_regs *regs = controller->regs;
+ __u32 temp;
+
+ temp = readl(&regs->revision) & 0xff;
+ if (temp != 0x10)
+ dbg("spec %d.%d", (temp >> 4), (temp & 0x0f));
+
+ temp = readl(&regs->control);
+ dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
+ (temp & OHCI_CTRL_RWE) ? " RWE" : "",
+ (temp & OHCI_CTRL_RWC) ? " RWC" : "",
+ (temp & OHCI_CTRL_IR) ? " IR" : "",
+ hcfs2string(temp & OHCI_CTRL_HCFS),
+ (temp & OHCI_CTRL_BLE) ? " BLE" : "",
+ (temp & OHCI_CTRL_CLE) ? " CLE" : "",
+ (temp & OHCI_CTRL_IE) ? " IE" : "",
+ (temp & OHCI_CTRL_PLE) ? " PLE" : "", temp & OHCI_CTRL_CBSR);
+
+ temp = readl(&regs->cmdstatus);
+ dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
+ (temp & OHCI_SOC) >> 16,
+ (temp & OHCI_OCR) ? " OCR" : "",
+ (temp & OHCI_BLF) ? " BLF" : "",
+ (temp & OHCI_CLF) ? " CLF" : "", (temp & OHCI_HCR) ? " HCR" : "");
+
+ ohci_dump_intr_mask("intrstatus", readl(&regs->intrstatus));
+ ohci_dump_intr_mask("intrenable", readl(&regs->intrenable));
+
+ maybe_print_eds("ed_periodcurrent", readl(&regs->ed_periodcurrent));
+
+ maybe_print_eds("ed_controlhead", readl(&regs->ed_controlhead));
+ maybe_print_eds("ed_controlcurrent", readl(&regs->ed_controlcurrent));
+
+ maybe_print_eds("ed_bulkhead", readl(&regs->ed_bulkhead));
+ maybe_print_eds("ed_bulkcurrent", readl(&regs->ed_bulkcurrent));
+
+ maybe_print_eds("donehead", readl(&regs->donehead));
+}
+
+static void ohci_dump_roothub(struct ohci *controller, int verbose)
+{
+ __u32 temp, ndp, i;
+
+ temp = roothub_a(controller);
+ ndp = (temp & RH_A_NDP);
+
+ if (verbose) {
+ dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
+ ((temp & RH_A_POTPGT) >> 24) & 0xff,
+ (temp & RH_A_NOCP) ? " NOCP" : "",
+ (temp & RH_A_OCPM) ? " OCPM" : "",
+ (temp & RH_A_DT) ? " DT" : "",
+ (temp & RH_A_NPS) ? " NPS" : "",
+ (temp & RH_A_PSM) ? " PSM" : "", ndp);
+ temp = roothub_b(controller);
+ dbg("roothub.b: %08x PPCM=%04x DR=%04x",
+ temp, (temp & RH_B_PPCM) >> 16, (temp & RH_B_DR)
+ );
+ temp = roothub_status(controller);
+ dbg("roothub.status: %08x%s%s%s%s%s%s",
+ temp,
+ (temp & RH_HS_CRWE) ? " CRWE" : "",
+ (temp & RH_HS_OCIC) ? " OCIC" : "",
+ (temp & RH_HS_LPSC) ? " LPSC" : "",
+ (temp & RH_HS_DRWE) ? " DRWE" : "",
+ (temp & RH_HS_OCI) ? " OCI" : "",
+ (temp & RH_HS_LPS) ? " LPS" : "");
+ }
+
+ for (i = 0; i < ndp; i++) {
+ temp = roothub_portstatus(controller, i);
+ dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
+ i,
+ temp,
+ (temp & RH_PS_PRSC) ? " PRSC" : "",
+ (temp & RH_PS_OCIC) ? " OCIC" : "",
+ (temp & RH_PS_PSSC) ? " PSSC" : "",
+ (temp & RH_PS_PESC) ? " PESC" : "",
+ (temp & RH_PS_CSC) ? " CSC" : "",
+ (temp & RH_PS_LSDA) ? " LSDA" : "",
+ (temp & RH_PS_PPS) ? " PPS" : "",
+ (temp & RH_PS_PRS) ? " PRS" : "",
+ (temp & RH_PS_POCI) ? " POCI" : "",
+ (temp & RH_PS_PSS) ? " PSS" : "",
+ (temp & RH_PS_PES) ? " PES" : "",
+ (temp & RH_PS_CCS) ? " CCS" : "");
+ }
+}
+
+static void ohci_dump(struct ohci *controller, int verbose)
+{
+ dbg("OHCI controller usb-%s state", controller->slot_name);
+
+ /* dumps some of the state we know about */
+ ohci_dump_status(controller);
+ if (verbose)
+ ep_print_int_eds(controller, "hcca");
+ dbg("hcca frame #%04x", controller->hcca->frame_no);
+ ohci_dump_roothub(controller, 1);
+}
+
+#endif /* DEBUG */
+
+/*-------------------------------------------------------------------------*
+ * Interface functions (URB)
+ *-------------------------------------------------------------------------*/
+
+/* get a transfer request */
+
+int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup, int interval)
+{
+ struct ohci *ohci;
+ struct ed *ed;
+ struct urb_priv *purb_priv;
+ int i, size = 0;
+
+ ohci = &gohci;
+
+ /* when controller's hung, permit only roothub cleanup attempts
+ * such as powering down ports */
+ if (ohci->disabled) {
+ err("sohci_submit_job: EPIPE");
+ return -1;
+ }
+
+ /* if we have an unfinished URB from previous transaction let's
+ * fail and scream as quickly as possible so as not to corrupt
+ * further communication */
+ if (!urb_finished) {
+ err("sohci_submit_job: URB NOT FINISHED");
+ return -1;
+ }
+ /* we're about to begin a new transaction here
+ so mark the URB unfinished */
+ urb_finished = 0;
+
+ /* every endpoint has a ed, locate and fill it */
+ ed = ep_add_ed(dev, pipe);
+ if (!ed) {
+ err("sohci_submit_job: ENOMEM");
+ return -1;
+ }
+
+ /* for the private part of the URB we need the number of TDs (size) */
+ switch (usb_pipetype(pipe)) {
+ case PIPE_BULK:
+ /* one TD for every 4096 Byte */
+ size = (transfer_len - 1) / 4096 + 1;
+ break;
+ case PIPE_CONTROL:
+ /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
+ size = (transfer_len == 0) ? 2 : (transfer_len - 1) / 4096 + 3;
+ break;
+ }
+
+ if (size >= (N_URB_TD - 1)) {
+ err("need %d TDs, only have %d", size, N_URB_TD);
+ return -1;
+ }
+ purb_priv = &urb_priv;
+ purb_priv->pipe = pipe;
+
+ /* fill the private part of the URB */
+ purb_priv->length = size;
+ purb_priv->ed = ed;
+ purb_priv->actual_length = 0;
+
+ /* allocate the TDs */
+ /* note that td[0] was allocated in ep_add_ed */
+ for (i = 0; i < size; i++) {
+ purb_priv->td[i] = td_alloc(dev);
+ if (!purb_priv->td[i]) {
+ purb_priv->length = i;
+ urb_free_priv(purb_priv);
+ err("sohci_submit_job: ENOMEM");
+ return -1;
+ }
+ }
+
+ if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
+ urb_free_priv(purb_priv);
+ err("sohci_submit_job: EINVAL");
+ return -1;
+ }
+
+ /* link the ed into a chain if is not already */
+ if (ed->state != ED_OPER)
+ ep_link(ohci, ed);
+
+ /* fill the TDs and link it to the ed */
+ td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv,
+ interval);
+
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef DEBUG
+/* tell us the current USB frame number */
+
+static int sohci_get_current_frame_number(struct usb_device *usb_dev)
+{
+ struct ohci *ohci = &gohci;
+
+ return m16_swap(ohci->hcca->frame_no);
+}
+#endif
+
+/*-------------------------------------------------------------------------*
+ * ED handling functions
+ *-------------------------------------------------------------------------*/
+
+/* link an ed into one of the HC chains */
+
+static int ep_link(struct ohci *ohci, struct ed *edi)
+{
+ struct ed *ed = edi;
+
+ ed->state = ED_OPER;
+
+ switch (ed->type) {
+ case PIPE_CONTROL:
+ ed->hwNextED = 0;
+ if (ohci->ed_controltail == NULL) {
+ writel((u32)ed, &ohci->regs->ed_controlhead);
+ } else {
+ ohci->ed_controltail->hwNextED = (__u32) m32_swap(ed);
+ }
+ ed->ed_prev = ohci->ed_controltail;
+ if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
+ !ohci->ed_rm_list[1] && !ohci->sleeping) {
+ ohci->hc_control |= OHCI_CTRL_CLE;
+ writel(ohci->hc_control, &ohci->regs->control);
+ }
+ ohci->ed_controltail = edi;
+ break;
+
+ case PIPE_BULK:
+ ed->hwNextED = 0;
+ if (ohci->ed_bulktail == NULL) {
+ writel((u32)ed, &ohci->regs->ed_bulkhead);
+ } else {
+ ohci->ed_bulktail->hwNextED = (__u32) m32_swap(ed);
+ }
+ ed->ed_prev = ohci->ed_bulktail;
+ if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
+ !ohci->ed_rm_list[1] && !ohci->sleeping) {
+ ohci->hc_control |= OHCI_CTRL_BLE;
+ writel(ohci->hc_control, &ohci->regs->control);
+ }
+ ohci->ed_bulktail = edi;
+ break;
+ }
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* unlink an ed from one of the HC chains.
+ * just the link to the ed is unlinked.
+ * the link from the ed still points to another operational ed or 0
+ * so the HC can eventually finish the processing of the unlinked ed */
+
+static int ep_unlink(struct ohci *ohci, struct ed *ed)
+{
+ struct ed *next;
+ ed->hwINFO |= m32_swap(OHCI_ED_SKIP);
+
+ switch (ed->type) {
+ case PIPE_CONTROL:
+ if (ed->ed_prev == NULL) {
+ if (!ed->hwNextED) {
+ ohci->hc_control &= ~OHCI_CTRL_CLE;
+ writel(ohci->hc_control, &ohci->regs->control);
+ }
+ writel(m32_swap(*((__u32 *) &ed->hwNextED)),
+ &ohci->regs->ed_controlhead);
+ } else {
+ ed->ed_prev->hwNextED = ed->hwNextED;
+ }
+ if (ohci->ed_controltail == ed) {
+ ohci->ed_controltail = ed->ed_prev;
+ } else {
+ next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED));
+ next->ed_prev = ed->ed_prev;
+ }
+ break;
+
+ case PIPE_BULK:
+ if (ed->ed_prev == NULL) {
+ if (!ed->hwNextED) {
+ ohci->hc_control &= ~OHCI_CTRL_BLE;
+ writel(ohci->hc_control, &ohci->regs->control);
+ }
+ writel(m32_swap(*((__u32 *) &ed->hwNextED)),
+ &ohci->regs->ed_bulkhead);
+ } else {
+ ed->ed_prev->hwNextED = ed->hwNextED;
+ }
+ if (ohci->ed_bulktail == ed) {
+ ohci->ed_bulktail = ed->ed_prev;
+ } else {
+ next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED));
+ next->ed_prev = ed->ed_prev;
+ }
+ break;
+ }
+ ed->state = ED_UNLINK;
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* add/reinit an endpoint; this should be done once at the usb_set_configuration
+ * command, but the USB stack is a little bit stateless so we do it at every
+ * transaction. If the state of the ed is ED_NEW then a dummy td is added and
+ * the state is changed to ED_UNLINK. In all other cases the state is left
+ * unchanged. The ed info fields are setted anyway even though most of them
+ * should not change */
+
+static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe)
+{
+ struct td *td;
+ struct ed *ed_ret;
+ struct ed *ed;
+
+ ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint(pipe) << 1) |
+ (usb_pipecontrol(pipe) ? 0 :
+ usb_pipeout(pipe))];
+
+ if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
+ err("ep_add_ed: pending delete");
+ /* pending delete request */
+ return NULL;
+ }
+
+ if (ed->state == ED_NEW) {
+ ed->hwINFO = m32_swap(OHCI_ED_SKIP); /* skip ed */
+ /* dummy td; end of td list for ed */
+ td = td_alloc(usb_dev);
+ ed->hwTailP = (__u32) m32_swap(td);
+ ed->hwHeadP = ed->hwTailP;
+ ed->state = ED_UNLINK;
+ ed->type = usb_pipetype(pipe);
+ ohci_dev.ed_cnt++;
+ }
+
+ ed->hwINFO = m32_swap(usb_pipedevice(pipe)
+ | usb_pipeendpoint(pipe) << 7
+ | (usb_pipeisoc(pipe) ? 0x8000 : 0)
+ | (usb_pipecontrol(pipe) ? 0 :
+ (usb_pipeout(pipe) ? 0x800 : 0x1000))
+ | usb_pipeslow(pipe) << 13 |
+ usb_maxpacket(usb_dev, pipe) << 16);
+
+ return ed_ret;
+}
+
+/*-------------------------------------------------------------------------*
+ * TD handling functions
+ *-------------------------------------------------------------------------*/
+
+/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
+
+static void td_fill(struct ohci *ohci, unsigned int info, void *data, int len,
+ struct usb_device *dev, int index,
+ struct urb_priv *urb_priv)
+{
+ struct td *td, *td_pt;
+#ifdef OHCI_FILL_TRACE
+ int i;
+#endif
+
+ if (index > urb_priv->length) {
+ err("index > length");
+ return;
+ }
+ /* use this td as the next dummy */
+ td_pt = urb_priv->td[index];
+ td_pt->hwNextTD = 0;
+
+ /* fill the old dummy TD */
+ td = urb_priv->td[index] =
+ (struct td *) (m32_swap(urb_priv->ed->hwTailP) & ~0xf);
+
+ td->ed = urb_priv->ed;
+ td->next_dl_td = NULL;
+ td->index = index;
+ td->data = (__u32) data;
+#ifdef OHCI_FILL_TRACE
+ if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
+ for (i = 0; i < len; i++)
+ printf("td->data[%d] %#2x ", i,
+ ((unsigned char *)td->data)[i]);
+ printf("\n");
+ }
+#endif
+ if (!len)
+ data = 0;
+
+ td->hwINFO = (__u32) m32_swap(info);
+ td->hwCBP = (__u32) m32_swap(data);
+ if (data)
+ td->hwBE = (__u32) m32_swap(data + len - 1);
+ else
+ td->hwBE = 0;
+ td->hwNextTD = (__u32) m32_swap(td_pt);
+
+ /* append to queue */
+ td->ed->hwTailP = td->hwNextTD;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* prepare all TDs of a transfer */
+
+static void td_submit_job(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len,
+ struct devrequest *setup, struct urb_priv *urb,
+ int interval)
+{
+ struct ohci *ohci = &gohci;
+ int data_len = transfer_len;
+ void *data;
+ int cnt = 0;
+ __u32 info = 0;
+ unsigned int toggle = 0;
+
+ /* OHCI handles the DATA-toggles itself, we just
+ use the USB-toggle bits for reseting */
+ if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
+ toggle = TD_T_TOGGLE;
+ } else {
+ toggle = TD_T_DATA0;
+ usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe),
+ 1);
+ }
+ urb->td_cnt = 0;
+ if (data_len)
+ data = buffer;
+ else
+ data = 0;
+
+ switch (usb_pipetype(pipe)) {
+ case PIPE_BULK:
+ info = usb_pipeout(pipe) ? TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN;
+ while (data_len > 4096) {
+ td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data,
+ 4096, dev, cnt, urb);
+ data += 4096;
+ data_len -= 4096;
+ cnt++;
+ }
+ info = usb_pipeout(pipe) ?
+ TD_CC | TD_DP_OUT :
+ TD_CC | TD_R | TD_DP_IN;
+ td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data,
+ data_len, dev, cnt, urb);
+ cnt++;
+
+ if (!ohci->sleeping)
+ /* start bulk list */
+ writel(OHCI_BLF, &ohci->regs->cmdstatus);
+ break;
+
+ case PIPE_CONTROL:
+ info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
+ td_fill(ohci, info, setup, 8, dev, cnt++, urb);
+ if (data_len > 0) {
+ info = usb_pipeout(pipe) ?
+ TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 :
+ TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
+ /* NOTE: mishandles transfers >8K, some >4K */
+ td_fill(ohci, info, data, data_len, dev, cnt++, urb);
+ }
+ info = usb_pipeout(pipe) ?
+ TD_CC | TD_DP_IN | TD_T_DATA1 :
+ TD_CC | TD_DP_OUT | TD_T_DATA1;
+ td_fill(ohci, info, data, 0, dev, cnt++, urb);
+ if (!ohci->sleeping)
+ /* start Control list */
+ writel(OHCI_CLF, &ohci->regs->cmdstatus);
+ break;
+ }
+ if (urb->length != cnt)
+ dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
+}
+
+/*-------------------------------------------------------------------------*
+ * Done List handling functions
+ *-------------------------------------------------------------------------*/
+
+
+/* calculate the transfer length and update the urb */
+
+static void dl_transfer_length(struct td *td)
+{
+ __u32 tdBE, tdCBP;
+ struct urb_priv *lurb_priv = &urb_priv;
+
+ tdBE = m32_swap(td->hwBE);
+ tdCBP = m32_swap(td->hwCBP);
+
+ if (!(usb_pipecontrol(lurb_priv->pipe) &&
+ ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
+ if (tdBE != 0) {
+ if (td->hwCBP == 0)
+ lurb_priv->actual_length += tdBE - td->data + 1;
+ else
+ lurb_priv->actual_length += tdCBP - td->data;
+ }
+ }
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* replies to the request have to be on a FIFO basis so
+ * we reverse the reversed done-list */
+
+static struct td *dl_reverse_done_list(struct ohci *ohci)
+{
+ __u32 td_list_hc;
+ __u32 tmp;
+ struct td *td_rev = NULL;
+ struct td *td_list = NULL;
+ struct urb_priv *lurb_priv = NULL;
+
+ td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0;
+ ohci->hcca->done_head = 0;
+
+ while (td_list_hc) {
+ td_list = (struct td *) td_list_hc;
+
+ if (TD_CC_GET(m32_swap(td_list->hwINFO))) {
+ lurb_priv = &urb_priv;
+ dbg(" USB-error/status: %x : %p",
+ TD_CC_GET(m32_swap(td_list->hwINFO)), td_list);
+ if (td_list->ed->hwHeadP & m32_swap(0x1)) {
+ if (lurb_priv &&
+ ((td_list->index+1) < lurb_priv->length)) {
+ tmp = lurb_priv->length - 1;
+ td_list->ed->hwHeadP =
+ (lurb_priv->td[tmp]->hwNextTD &
+ m32_swap(0xfffffff0)) |
+ (td_list->ed->hwHeadP &
+ m32_swap(0x2));
+ lurb_priv->td_cnt += lurb_priv->length -
+ td_list->index - 1;
+ } else
+ td_list->ed->hwHeadP &=
+ m32_swap(0xfffffff2);
+ }
+ }
+
+ td_list->next_dl_td = td_rev;
+ td_rev = td_list;
+ td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0;
+ }
+
+ return td_list;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* td done list */
+static int dl_done_list(struct ohci *ohci, struct td *td_list)
+{
+ struct td *td_list_next = NULL;
+ struct ed *ed;
+ int cc = 0;
+ int stat = 0;
+ /* urb_t *urb; */
+ struct urb_priv *lurb_priv;
+ __u32 tdINFO, edHeadP, edTailP;
+
+ while (td_list) {
+ td_list_next = td_list->next_dl_td;
+
+ lurb_priv = &urb_priv;
+ tdINFO = m32_swap(td_list->hwINFO);
+
+ ed = td_list->ed;
+
+ dl_transfer_length(td_list);
+
+ /* error code of transfer */
+ cc = TD_CC_GET(tdINFO);
+ if (cc != 0) {
+ dbg("ConditionCode %#x", cc);
+ stat = cc_to_error[cc];
+ }
+
+ /* see if this done list makes for all TD's of current URB,
+ * and mark the URB finished if so */
+ if (++(lurb_priv->td_cnt) == lurb_priv->length) {
+ if ((ed->state & (ED_OPER | ED_UNLINK)))
+ urb_finished = 1;
+ else
+ dbg("dl_done_list: strange.., ED state %x, "
+ "ed->state\n");
+ } else
+ dbg("dl_done_list: processing TD %x, len %x\n",
+ lurb_priv->td_cnt, lurb_priv->length);
+
+ if (ed->state != ED_NEW) {
+ edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0;
+ edTailP = m32_swap(ed->hwTailP);
+
+ /* unlink eds if they are not busy */
+ if ((edHeadP == edTailP) && (ed->state == ED_OPER))
+ ep_unlink(ohci, ed);
+ }
+
+ td_list = td_list_next;
+ }
+ return stat;
+}
+
+/*-------------------------------------------------------------------------*
+ * Virtual Root Hub
+ *-------------------------------------------------------------------------*/
+
+/* Device descriptor */
+static __u8 root_hub_dev_des[] = {
+ 0x12, /* __u8 bLength; */
+ 0x01, /* __u8 bDescriptorType; Device */
+ 0x10, /* __u16 bcdUSB; v1.1 */
+ 0x01,
+ 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
+ 0x00, /* __u8 bDeviceSubClass; */
+ 0x00, /* __u8 bDeviceProtocol; */
+ 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
+ 0x00, /* __u16 idVendor; */
+ 0x00,
+ 0x00, /* __u16 idProduct; */
+ 0x00,
+ 0x00, /* __u16 bcdDevice; */
+ 0x00,
+ 0x00, /* __u8 iManufacturer; */
+ 0x01, /* __u8 iProduct; */
+ 0x00, /* __u8 iSerialNumber; */
+ 0x01 /* __u8 bNumConfigurations; */
+};
+
+/* Configuration descriptor */
+static __u8 root_hub_config_des[] = {
+ 0x09, /* __u8 bLength; */
+ 0x02, /* __u8 bDescriptorType; Configuration */
+ 0x19, /* __u16 wTotalLength; */
+ 0x00,
+ 0x01, /* __u8 bNumInterfaces; */
+ 0x01, /* __u8 bConfigurationValue; */
+ 0x00, /* __u8 iConfiguration; */
+ 0x40, /* __u8 bmAttributes;
+ Bit 7: Bus-powered, 6: Self-powered,
+ 5 Remote-wakwup, 4..0: resvd */
+ 0x00, /* __u8 MaxPower; */
+
+ /* interface */
+ 0x09, /* __u8 if_bLength; */
+ 0x04, /* __u8 if_bDescriptorType; Interface */
+ 0x00, /* __u8 if_bInterfaceNumber; */
+ 0x00, /* __u8 if_bAlternateSetting; */
+ 0x01, /* __u8 if_bNumEndpoints; */
+ 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
+ 0x00, /* __u8 if_bInterfaceSubClass; */
+ 0x00, /* __u8 if_bInterfaceProtocol; */
+ 0x00, /* __u8 if_iInterface; */
+
+ /* endpoint */
+ 0x07, /* __u8 ep_bLength; */
+ 0x05, /* __u8 ep_bDescriptorType; Endpoint */
+ 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
+ 0x03, /* __u8 ep_bmAttributes; Interrupt */
+ 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+ 0x00,
+ 0xff /* __u8 ep_bInterval; 255 ms */
+};
+
+static unsigned char root_hub_str_index0[] = {
+ 0x04, /* __u8 bLength; */
+ 0x03, /* __u8 bDescriptorType; String-descriptor */
+ 0x09, /* __u8 lang ID */
+ 0x04, /* __u8 lang ID */
+};
+
+static unsigned char root_hub_str_index1[] = {
+ 28, /* __u8 bLength; */
+ 0x03, /* __u8 bDescriptorType; String-descriptor */
+ 'O', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'H', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'C', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'I', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ ' ', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'R', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 't', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ ' ', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'H', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'u', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'b', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+};
+
+/* Hub class-specific descriptor is constructed dynamically */
+
+
+/*-------------------------------------------------------------------------*/
+
+#define OK(x) len = (x); break
+#ifdef DEBUG
+#define WR_RH_STAT(x) \
+{ \
+ info("WR:status %#8x", (x)); \
+ writel((x), &gohci.regs->roothub.status); \
+}
+#define WR_RH_PORTSTAT(x) \
+{ \
+ info("WR:portstatus[%d] %#8x", wIndex-1, (x)); \
+ writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); \
+}
+#else
+#define WR_RH_STAT(x) \
+ writel((x), &gohci.regs->roothub.status)
+#define WR_RH_PORTSTAT(x)\
+ writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
+#endif
+#define RD_RH_STAT roothub_status(&gohci)
+#define RD_RH_PORTSTAT roothub_portstatus(&gohci, wIndex-1)
+
+/* request to virtual root hub */
+
+int rh_check_port_status(struct ohci *controller)
+{
+ __u32 temp, ndp, i;
+ int res;
+
+ res = -1;
+ temp = roothub_a(controller);
+ ndp = (temp & RH_A_NDP);
+ for (i = 0; i < ndp; i++) {
+ temp = roothub_portstatus(controller, i);
+ /* check for a device disconnect */
+ if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
+ (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) {
+ res = i;
+ break;
+ }
+ }
+ return res;
+}
+
+static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len,
+ struct devrequest *cmd)
+{
+ void *data = buffer;
+ int leni = transfer_len;
+ int len = 0;
+ int stat = 0;
+ union {
+ __u32 word[4];
+ __u16 hword[8];
+ __u8 byte[16];
+ } datab;
+ __u8 *data_buf = datab.byte;
+ __u16 bmRType_bReq;
+ __u16 wValue;
+ __u16 wIndex;
+ __u16 wLength;
+
+#ifdef DEBUG
+ urb_priv.actual_length = 0;
+ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)",
+ usb_pipein(pipe));
+#else
+ mdelay(1);
+#endif
+ if (usb_pipeint(pipe)) {
+ info("Root-Hub submit IRQ: NOT implemented");
+ return 0;
+ }
+
+ bmRType_bReq = cmd->requesttype | (cmd->request << 8);
+ wValue = m16_swap(cmd->value);
+ wIndex = m16_swap(cmd->index);
+ wLength = m16_swap(cmd->length);
+
+ info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
+ dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
+
+ switch (bmRType_bReq) {
+ /* Request Destination:
+ without flags: Device,
+ RH_INTERFACE: interface,
+ RH_ENDPOINT: endpoint,
+ RH_CLASS means HUB here,
+ RH_OTHER | RH_CLASS almost ever means HUB_PORT here
+ */
+
+ case RH_GET_STATUS:
+ datab.hword[0] = m16_swap(1);
+ OK(2);
+ case RH_GET_STATUS | RH_INTERFACE:
+ datab.hword[0] = m16_swap(0);
+ OK(2);
+ case RH_GET_STATUS | RH_ENDPOINT:
+ datab.hword[0] = m16_swap(0);
+ OK(2);
+ case RH_GET_STATUS | RH_CLASS:
+ datab.word[0] =
+ m32_swap(RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
+ OK(4);
+ case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+ datab.word[0] = m32_swap(RD_RH_PORTSTAT);
+ OK(4);
+
+ case RH_CLEAR_FEATURE | RH_ENDPOINT:
+ switch (wValue) {
+ case (RH_ENDPOINT_STALL):
+ OK(0);
+ }
+ break;
+
+ case RH_CLEAR_FEATURE | RH_CLASS:
+ switch (wValue) {
+ case RH_C_HUB_LOCAL_POWER:
+ OK(0);
+ case (RH_C_HUB_OVER_CURRENT):
+ WR_RH_STAT(RH_HS_OCIC);
+ OK(0);
+ }
+ break;
+
+ case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+ switch (wValue) {
+ case (RH_PORT_ENABLE):
+ WR_RH_PORTSTAT(RH_PS_CCS);
+ OK(0);
+ case (RH_PORT_SUSPEND):
+ WR_RH_PORTSTAT(RH_PS_POCI);
+ OK(0);
+ case (RH_PORT_POWER):
+ WR_RH_PORTSTAT(RH_PS_LSDA);
+ OK(0);
+ case (RH_C_PORT_CONNECTION):
+ WR_RH_PORTSTAT(RH_PS_CSC);
+ OK(0);
+ case (RH_C_PORT_ENABLE):
+ WR_RH_PORTSTAT(RH_PS_PESC);
+ OK(0);
+ case (RH_C_PORT_SUSPEND):
+ WR_RH_PORTSTAT(RH_PS_PSSC);
+ OK(0);
+ case (RH_C_PORT_OVER_CURRENT):
+ WR_RH_PORTSTAT(RH_PS_OCIC);
+ OK(0);
+ case (RH_C_PORT_RESET):
+ WR_RH_PORTSTAT(RH_PS_PRSC);
+ OK(0);
+ }
+ break;
+
+ case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+ switch (wValue) {
+ case (RH_PORT_SUSPEND):
+ WR_RH_PORTSTAT(RH_PS_PSS);
+ OK(0);
+ case (RH_PORT_RESET): /* BUG IN HUP CODE ******** */
+ if (RD_RH_PORTSTAT & RH_PS_CCS)
+ WR_RH_PORTSTAT(RH_PS_PRS);
+ OK(0);
+ case (RH_PORT_POWER):
+ WR_RH_PORTSTAT(RH_PS_PPS);
+ OK(0);
+ case (RH_PORT_ENABLE): /* BUG IN HUP CODE ******** */
+ if (RD_RH_PORTSTAT & RH_PS_CCS)
+ WR_RH_PORTSTAT(RH_PS_PES);
+ OK(0);
+ }
+ break;
+
+ case RH_SET_ADDRESS:
+ gohci.rh.devnum = wValue;
+ OK(0);
+
+ case RH_GET_DESCRIPTOR:
+ switch ((wValue & 0xff00) >> 8) {
+ case (0x01): /* device descriptor */
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof(root_hub_dev_des), wLength));
+ data_buf = root_hub_dev_des;
+ OK(len);
+ case (0x02): /* configuration descriptor */
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof(root_hub_config_des),
+ wLength));
+ data_buf = root_hub_config_des;
+ OK(len);
+ case (0x03): /* string descriptors */
+ if (wValue == 0x0300) {
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof(root_hub_str_index0),
+ wLength));
+ data_buf = root_hub_str_index0;
+ OK(len);
+ }
+ if (wValue == 0x0301) {
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof(root_hub_str_index1),
+ wLength));
+ data_buf = root_hub_str_index1;
+ OK(len);
+ }
+ default:
+ stat = USB_ST_STALLED;
+ }
+ break;
+
+ case RH_GET_DESCRIPTOR | RH_CLASS:
+ {
+ __u32 temp = roothub_a(&gohci);
+
+ data_buf[0] = 9; /* min length; */
+ data_buf[1] = 0x29;
+ data_buf[2] = temp & RH_A_NDP;
+ data_buf[3] = 0;
+ if (temp & RH_A_PSM)
+ /* per-port power switching? */
+ data_buf[3] |= 0x1;
+ if (temp & RH_A_NOCP)
+ /* no overcurrent reporting? */
+ data_buf[3] |= 0x10;
+ else if (temp & RH_A_OCPM)
+ /* per-port overcurrent reporting? */
+ data_buf[3] |= 0x8;
+
+ /* corresponds to data_buf[4-7] */
+ datab.word[1] = 0;
+ data_buf[5] = (temp & RH_A_POTPGT) >> 24;
+ temp = roothub_b(&gohci);
+ data_buf[7] = temp & RH_B_DR;
+ if (data_buf[2] < 7) {
+ data_buf[8] = 0xff;
+ } else {
+ data_buf[0] += 2;
+ data_buf[8] = (temp & RH_B_DR) >> 8;
+ data_buf[10] = data_buf[9] = 0xff;
+ }
+
+ len = min_t(unsigned int, leni,
+ min_t(unsigned int, data_buf[0], wLength));
+ OK(len);
+ }
+
+ case RH_GET_CONFIGURATION:
+ *(__u8 *) data_buf = 0x01;
+ OK(1);
+
+ case RH_SET_CONFIGURATION:
+ WR_RH_STAT(0x10000);
+ OK(0);
+
+ default:
+ dbg("unsupported root hub command");
+ stat = USB_ST_STALLED;
+ }
+
+#ifdef DEBUG
+ ohci_dump_roothub(&gohci, 1);
+#else
+ mdelay(1);
+#endif
+
+ len = min_t(int, len, leni);
+ if (data != data_buf)
+ memcpy(data, data_buf, len);
+ dev->act_len = len;
+ dev->status = stat;
+
+#ifdef DEBUG
+ if (transfer_len)
+ urb_priv.actual_length = transfer_len;
+ pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)",
+ 0 /*usb_pipein(pipe) */);
+#else
+ mdelay(1);
+#endif
+
+ return stat;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* common code for handling submit messages - used for all but root hub */
+/* accesses. */
+int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup, int interval)
+{
+ int stat = 0;
+ int maxsize = usb_maxpacket(dev, pipe);
+ int timeout;
+
+ /* device pulled? Shortcut the action. */
+ if (devgone == dev) {
+ dev->status = USB_ST_CRC_ERR;
+ return 0;
+ }
+#ifdef DEBUG
+ urb_priv.actual_length = 0;
+ pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB",
+ usb_pipein(pipe));
+#else
+ mdelay(1);
+#endif
+ if (!maxsize) {
+ err("submit_common_message: pipesize for pipe %lx is zero",
+ pipe);
+ return -1;
+ }
+
+ if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) <
+ 0) {
+ err("sohci_submit_job failed");
+ return -1;
+ }
+
+ mdelay(10);
+ /* ohci_dump_status(&gohci); */
+
+ /* allow more time for a BULK device to react - some are slow */
+#define BULK_TO 5000 /* timeout in milliseconds */
+ if (usb_pipebulk(pipe))
+ timeout = BULK_TO;
+ else
+ timeout = 100;
+
+ /* wait for it to complete */
+ for (;;) {
+ /* check whether the controller is done */
+ stat = hc_interrupt();
+
+ if (stat < 0) {
+ stat = USB_ST_CRC_ERR;
+ break;
+ }
+
+ /* NOTE: since we are not interrupt driven in U-Boot and always
+ * handle only one URB at a time, we cannot assume the
+ * transaction finished on the first successful return from
+ * hc_interrupt().. unless the flag for current URB is set,
+ * meaning that all TD's to/from device got actually
+ * transferred and processed. If the current URB is not
+ * finished we need to re-iterate this loop so as
+ * hc_interrupt() gets called again as there needs to be some
+ * more TD's to process still */
+ if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
+ /* 0xff is returned for an SF-interrupt */
+ break;
+ }
+
+ if (--timeout) {
+ mdelay(1);
+ if (!urb_finished)
+ dbg("\%");
+
+ } else {
+ err("CTL:TIMEOUT ");
+ dbg("submit_common_msg: TO status %x\n", stat);
+ stat = USB_ST_CRC_ERR;
+ urb_finished = 1;
+ break;
+ }
+ }
+
+#if 0
+ /* we got an Root Hub Status Change interrupt */
+ if (got_rhsc) {
+#ifdef DEBUG
+ ohci_dump_roothub(&gohci, 1);
+#endif
+ got_rhsc = 0;
+ /* abuse timeout */
+ timeout = rh_check_port_status(&gohci);
+ if (timeout >= 0) {
+#if 0 /* this does nothing useful, but leave it here
+ in case that changes */
+ /* the called routine adds 1 to the passed value */
+ usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
+#endif
+ /*
+ * XXX
+ * This is potentially dangerous because it assumes
+ * that only one device is ever plugged in!
+ */
+ devgone = dev;
+ }
+ }
+#endif
+
+ dev->status = stat;
+ dev->act_len = transfer_len;
+
+#ifdef DEBUG
+ pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)",
+ usb_pipein(pipe));
+#else
+ mdelay(1);
+#endif
+
+ /* free TDs in urb_priv */
+ urb_free_priv(&urb_priv);
+ return 0;
+}
+
+/* submit routines called from usb.c */
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len)
+{
+ info("submit_bulk_msg");
+ return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
+}
+
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup)
+{
+ int maxsize = usb_maxpacket(dev, pipe);
+
+ info("submit_control_msg");
+#ifdef DEBUG
+ urb_priv.actual_length = 0;
+ pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB",
+ usb_pipein(pipe));
+#else
+ mdelay(1);
+#endif
+ if (!maxsize) {
+ err("submit_control_message: pipesize for pipe %lx is zero",
+ pipe);
+ return -1;
+ }
+ if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
+ gohci.rh.dev = dev;
+ /* root hub - redirect */
+ return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
+ setup);
+ }
+
+ return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
+}
+
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, int interval)
+{
+ info("submit_int_msg");
+ return -1;
+}
+
+/*-------------------------------------------------------------------------*
+ * HC functions
+ *-------------------------------------------------------------------------*/
+
+/* reset the HC and BUS */
+
+static int hc_reset(struct ohci *ohci)
+{
+ int timeout = 30;
+ int smm_timeout = 50; /* 0,5 sec */
+
+ if (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
+ /* SMM owns the HC - request ownership */
+ writel(OHCI_OCR, &ohci->regs->cmdstatus);
+ info("USB HC TakeOver from SMM");
+ while (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
+ mdelay(10);
+ if (--smm_timeout == 0) {
+ err("USB HC TakeOver failed!");
+ return -1;
+ }
+ }
+ }
+
+ /* Disable HC interrupts */
+ writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
+
+ dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
+ ohci->slot_name, readl(&ohci->regs->control));
+
+ /* Reset USB (needed by some controllers) */
+ writel(0, &ohci->regs->control);
+
+ /* HC Reset requires max 10 us delay */
+ writel(OHCI_HCR, &ohci->regs->cmdstatus);
+ while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
+ if (--timeout == 0) {
+ err("USB HC reset timed out!");
+ return -1;
+ }
+ udelay(1);
+ }
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* Start an OHCI controller, set the BUS operational
+ * enable interrupts
+ * connect the virtual root hub */
+
+static int hc_start(struct ohci *ohci)
+{
+ __u32 mask;
+ unsigned int fminterval;
+
+ ohci->disabled = 1;
+
+ /* Tell the controller where the control and bulk lists are
+ * The lists are empty now. */
+
+ writel(0, &ohci->regs->ed_controlhead);
+ writel(0, &ohci->regs->ed_bulkhead);
+
+ /* a reset clears this */
+ writel((__u32) ohci->hcca, &ohci->regs->hcca);
+
+ fminterval = 0x2edf;
+ writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
+ fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
+ writel(fminterval, &ohci->regs->fminterval);
+ writel(0x628, &ohci->regs->lsthresh);
+
+ /* start controller operations */
+ ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
+ ohci->disabled = 0;
+ writel(ohci->hc_control, &ohci->regs->control);
+
+ /* disable all interrupts */
+ mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
+ OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
+ OHCI_INTR_OC | OHCI_INTR_MIE);
+ writel(mask, &ohci->regs->intrdisable);
+ /* clear all interrupts */
+ mask &= ~OHCI_INTR_MIE;
+ writel(mask, &ohci->regs->intrstatus);
+ /* Choose the interrupts we care about now - but w/o MIE */
+ mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
+ writel(mask, &ohci->regs->intrenable);
+
+#ifdef OHCI_USE_NPS
+ /* required for AMD-756 and some Mac platforms */
+ writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
+ &ohci->regs->roothub.a);
+ writel(RH_HS_LPSC, &ohci->regs->roothub.status);
+#endif /* OHCI_USE_NPS */
+
+ /* POTPGT delay is bits 24-31, in 2 ms units. */
+ mdelay((roothub_a(ohci) >> 23) & 0x1fe);
+
+ /* connect the virtual root hub */
+ ohci->rh.devnum = 0;
+
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* an interrupt happens */
+
+static int hc_interrupt(void)
+{
+ struct ohci *ohci = &gohci;
+ struct ohci_regs *regs = ohci->regs;
+ int ints;
+ int stat = -1;
+
+ if ((ohci->hcca->done_head != 0) &&
+ !(m32_swap(ohci->hcca->done_head) & 0x01)) {
+
+ ints = OHCI_INTR_WDH;
+
+ } else {
+ ints = readl(&regs->intrstatus);
+ if (ints == ~(u32) 0) {
+ ohci->disabled++;
+ err("%s device removed!", ohci->slot_name);
+ return -1;
+ }
+ ints &= readl(&regs->intrenable);
+ if (ints == 0) {
+ dbg("hc_interrupt: returning..\n");
+ return 0xff;
+ }
+ }
+
+ /* dbg("Interrupt: %x frame: %x", ints,
+ le16_to_cpu(ohci->hcca->frame_no)); */
+
+ if (ints & OHCI_INTR_RHSC) {
+ got_rhsc = 1;
+ stat = 0xff;
+ }
+
+ if (ints & OHCI_INTR_UE) {
+ ohci->disabled++;
+ err("OHCI Unrecoverable Error, controller usb-%s disabled",
+ ohci->slot_name);
+ /* e.g. due to PCI Master/Target Abort */
+
+#ifdef DEBUG
+ ohci_dump(ohci, 1);
+#else
+ mdelay(1);
+#endif
+ /* FIXME: be optimistic, hope that bug won't repeat often. */
+ /* Make some non-interrupt context restart the controller. */
+ /* Count and limit the retries though; either hardware or */
+ /* software errors can go forever... */
+ hc_reset(ohci);
+ return -1;
+ }
+
+ if (ints & OHCI_INTR_WDH) {
+ mdelay(1);
+
+ writel(OHCI_INTR_WDH, &regs->intrdisable);
+ stat = dl_done_list(&gohci, dl_reverse_done_list(&gohci));
+ writel(OHCI_INTR_WDH, &regs->intrenable);
+ }
+
+ if (ints & OHCI_INTR_SO) {
+ dbg("USB Schedule overrun\n");
+ writel(OHCI_INTR_SO, &regs->intrenable);
+ stat = -1;
+ }
+
+ /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
+ if (ints & OHCI_INTR_SF) {
+ unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
+ mdelay(1);
+ writel(OHCI_INTR_SF, &regs->intrdisable);
+ if (ohci->ed_rm_list[frame] != NULL)
+ writel(OHCI_INTR_SF, &regs->intrenable);
+ stat = 0xff;
+ }
+
+ writel(ints, &regs->intrstatus);
+ return stat;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*-------------------------------------------------------------------------*/
+
+/* De-allocate all resources.. */
+
+static void hc_release_ohci(struct ohci *ohci)
+{
+ dbg("USB HC release ohci usb-%s", ohci->slot_name);
+
+ if (!ohci->disabled)
+ hc_reset(ohci);
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * low level initalisation routine, called from usb.c
+ */
+static char ohci_inited = 0;
+
+int usb_lowlevel_init(int index, void **controller)
+{
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+ struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
+
+ /*
+ * Set the 48 MHz UPLL clocking. Values are taken from
+ * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
+ */
+ clk_power->upllcon = ((40 << 12) + (1 << 4) + 2);
+ gpio->misccr |= 0x8; /* 1 = use pads related USB for USB host */
+
+ /*
+ * Enable USB host clock.
+ */
+ clk_power->clkcon |= (1 << 4);
+
+ memset(&gohci, 0, sizeof(struct ohci));
+ memset(&urb_priv, 0, sizeof(struct urb_priv));
+
+ /* align the storage */
+ if ((__u32) &ghcca[0] & 0xff) {
+ err("HCCA not aligned!!");
+ return -1;
+ }
+ phcca = &ghcca[0];
+ info("aligned ghcca %p", phcca);
+ memset(&ohci_dev, 0, sizeof(struct ohci_device));
+ if ((__u32) &ohci_dev.ed[0] & 0x7) {
+ err("EDs not aligned!!");
+ return -1;
+ }
+ memset(gtd, 0, sizeof(struct td) * (NUM_TD + 1));
+ if ((__u32) gtd & 0x7) {
+ err("TDs not aligned!!");
+ return -1;
+ }
+ ptd = gtd;
+ gohci.hcca = phcca;
+ memset(phcca, 0, sizeof(struct ohci_hcca));
+
+ gohci.disabled = 1;
+ gohci.sleeping = 0;
+ gohci.irq = -1;
+ gohci.regs = (struct ohci_regs *)S3C24X0_USB_HOST_BASE;
+
+ gohci.flags = 0;
+ gohci.slot_name = "s3c2400";
+
+ if (hc_reset(&gohci) < 0) {
+ hc_release_ohci(&gohci);
+ /* Initialization failed */
+ clk_power->clkcon &= ~(1 << 4);
+ return -1;
+ }
+
+ /* FIXME this is a second HC reset; why?? */
+ gohci.hc_control = OHCI_USB_RESET;
+ writel(gohci.hc_control, &gohci.regs->control);
+ mdelay(10);
+
+ if (hc_start(&gohci) < 0) {
+ err("can't start usb-%s", gohci.slot_name);
+ hc_release_ohci(&gohci);
+ /* Initialization failed */
+ clk_power->clkcon &= ~(1 << 4);
+ return -1;
+ }
+#ifdef DEBUG
+ ohci_dump(&gohci, 1);
+#else
+ mdelay(1);
+#endif
+ ohci_inited = 1;
+ urb_finished = 1;
+
+ return 0;
+}
+
+int usb_lowlevel_stop(int index)
+{
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+
+ /* this gets called really early - before the controller has */
+ /* even been initialized! */
+ if (!ohci_inited)
+ return 0;
+ /* TODO release any interrupts, etc. */
+ /* call hc_release_ohci() here ? */
+ hc_reset(&gohci);
+ /* may not want to do this */
+ clk_power->clkcon &= ~(1 << 4);
+ return 0;
+}
+
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0) */
+
+#if defined(CONFIG_USB_OHCI_NEW) && \
+ defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
+ defined(CONFIG_S3C24X0)
+
+int usb_cpu_init(void)
+{
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+ struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
+
+ /*
+ * Set the 48 MHz UPLL clocking. Values are taken from
+ * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
+ */
+ writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon);
+ /* 1 = use pads related USB for USB host */
+ writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);
+
+ /*
+ * Enable USB host clock.
+ */
+ writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
+
+ return 0;
+}
+
+int usb_cpu_stop(void)
+{
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+ /* may not want to do this */
+ writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
+ return 0;
+}
+
+int usb_cpu_init_fail(void)
+{
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+ writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
+ return 0;
+}
+
+#endif /* defined(CONFIG_USB_OHCI_NEW) && \
+ defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
+ defined(CONFIG_S3C24X0) */
diff --git a/drivers/usb/host/ohci-s3c24xx.h b/drivers/usb/host/ohci-s3c24xx.h
new file mode 100644
index 0000000..f272d78
--- /dev/null
+++ b/drivers/usb/host/ohci-s3c24xx.h
@@ -0,0 +1,409 @@
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB.
+ *
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * usb-ohci.h
+ */
+
+
+static int cc_to_error[16] = {
+
+/* mapping of the OHCI CC status to error codes */
+ /* No Error */ 0,
+ /* CRC Error */ USB_ST_CRC_ERR,
+ /* Bit Stuff */ USB_ST_BIT_ERR,
+ /* Data Togg */ USB_ST_CRC_ERR,
+ /* Stall */ USB_ST_STALLED,
+ /* DevNotResp */ -1,
+ /* PIDCheck */ USB_ST_BIT_ERR,
+ /* UnExpPID */ USB_ST_BIT_ERR,
+ /* DataOver */ USB_ST_BUF_ERR,
+ /* DataUnder */ USB_ST_BUF_ERR,
+ /* reservd */ -1,
+ /* reservd */ -1,
+ /* BufferOver */ USB_ST_BUF_ERR,
+ /* BuffUnder */ USB_ST_BUF_ERR,
+ /* Not Access */ -1,
+ /* Not Access */ -1
+};
+
+/* ED States */
+#define ED_NEW 0x00
+#define ED_UNLINK 0x01
+#define ED_OPER 0x02
+#define ED_DEL 0x04
+#define ED_URB_DEL 0x08
+
+/* usb_ohci_ed */
+struct ed {
+ __u32 hwINFO;
+ __u32 hwTailP;
+ __u32 hwHeadP;
+ __u32 hwNextED;
+
+ struct ed *ed_prev;
+ __u8 int_period;
+ __u8 int_branch;
+ __u8 int_load;
+ __u8 int_interval;
+ __u8 state;
+ __u8 type;
+ __u16 last_iso;
+ struct ed *ed_rm_list;
+
+ struct usb_device *usb_dev;
+ __u32 unused[3];
+} __attribute__ ((aligned(16)));
+
+/* TD info field */
+#define TD_CC 0xf0000000
+#define TD_CC_GET(td_p) (((td_p) >> 28) & 0x0f)
+#define TD_CC_SET(td_p, cc) \
+ {(td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)}
+#define TD_EC 0x0C000000
+#define TD_T 0x03000000
+#define TD_T_DATA0 0x02000000
+#define TD_T_DATA1 0x03000000
+#define TD_T_TOGGLE 0x00000000
+#define TD_R 0x00040000
+#define TD_DI 0x00E00000
+#define TD_DI_SET(X) (((X) & 0x07)<< 21)
+#define TD_DP 0x00180000
+#define TD_DP_SETUP 0x00000000
+#define TD_DP_IN 0x00100000
+#define TD_DP_OUT 0x00080000
+
+#define TD_ISO 0x00010000
+#define TD_DEL 0x00020000
+
+/* CC Codes */
+#define TD_CC_NOERROR 0x00
+#define TD_CC_CRC 0x01
+#define TD_CC_BITSTUFFING 0x02
+#define TD_CC_DATATOGGLEM 0x03
+#define TD_CC_STALL 0x04
+#define TD_DEVNOTRESP 0x05
+#define TD_PIDCHECKFAIL 0x06
+#define TD_UNEXPECTEDPID 0x07
+#define TD_DATAOVERRUN 0x08
+#define TD_DATAUNDERRUN 0x09
+#define TD_BUFFEROVERRUN 0x0C
+#define TD_BUFFERUNDERRUN 0x0D
+#define TD_NOTACCESSED 0x0F
+
+
+#define MAXPSW 1
+
+struct td {
+ __u32 hwINFO;
+ __u32 hwCBP; /* Current Buffer Pointer */
+ __u32 hwNextTD; /* Next TD Pointer */
+ __u32 hwBE; /* Memory Buffer End Pointer */
+
+ __u8 unused;
+ __u8 index;
+ struct ed *ed;
+ struct td *next_dl_td;
+ struct usb_device *usb_dev;
+ int transfer_len;
+ __u32 data;
+
+ __u32 unused2[2];
+} __attribute__ ((aligned(32)));
+
+#define OHCI_ED_SKIP (1 << 14)
+
+/*
+ * The HCCA (Host Controller Communications Area) is a 256 byte
+ * structure defined in the OHCI spec. that the host controller is
+ * told the base address of. It must be 256-byte aligned.
+ */
+
+#define NUM_INTS 32 /* part of the OHCI standard */
+struct ohci_hcca {
+ __u32 int_table[NUM_INTS]; /* Interrupt ED table */
+ __u16 frame_no; /* current frame number */
+ __u16 pad1; /* set to 0 on each frame_no change */
+ __u32 done_head; /* info returned for an interrupt */
+ u8 reserved_for_hc[116];
+} __attribute__ ((aligned(256)));
+
+/*
+ * Maximum number of root hub ports.
+ */
+#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */
+
+/*
+ * This is the structure of the OHCI controller's memory mapped I/O
+ * region. This is Memory Mapped I/O. You must use the readl() and
+ * writel() macros defined in asm/io.h to access these!!
+ */
+struct ohci_regs {
+ /* control and status registers */
+ __u32 revision;
+ __u32 control;
+ __u32 cmdstatus;
+ __u32 intrstatus;
+ __u32 intrenable;
+ __u32 intrdisable;
+ /* memory pointers */
+ __u32 hcca;
+ __u32 ed_periodcurrent;
+ __u32 ed_controlhead;
+ __u32 ed_controlcurrent;
+ __u32 ed_bulkhead;
+ __u32 ed_bulkcurrent;
+ __u32 donehead;
+ /* frame counters */
+ __u32 fminterval;
+ __u32 fmremaining;
+ __u32 fmnumber;
+ __u32 periodicstart;
+ __u32 lsthresh;
+ /* Root hub ports */
+ struct ohci_roothub_regs {
+ __u32 a;
+ __u32 b;
+ __u32 status;
+ __u32 portstatus[MAX_ROOT_PORTS];
+ } roothub;
+} __attribute__ ((aligned(32)));
+
+/* OHCI CONTROL AND STATUS REGISTER MASKS */
+
+/*
+ * HcControl (control) register masks
+ */
+#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
+#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
+#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
+#define OHCI_CTRL_CLE (1 << 4) /* control list enable */
+#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
+#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
+#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
+#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
+#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
+
+/* pre-shifted values for HCFS */
+# define OHCI_USB_RESET (0 << 6)
+# define OHCI_USB_RESUME (1 << 6)
+# define OHCI_USB_OPER (2 << 6)
+# define OHCI_USB_SUSPEND (3 << 6)
+
+/*
+ * HcCommandStatus (cmdstatus) register masks
+ */
+#define OHCI_HCR (1 << 0) /* host controller reset */
+#define OHCI_CLF (1 << 1) /* control list filled */
+#define OHCI_BLF (1 << 2) /* bulk list filled */
+#define OHCI_OCR (1 << 3) /* ownership change request */
+#define OHCI_SOC (3 << 16) /* scheduling overrun count */
+
+/*
+ * masks used with interrupt registers:
+ * HcInterruptStatus (intrstatus)
+ * HcInterruptEnable (intrenable)
+ * HcInterruptDisable (intrdisable)
+ */
+#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
+#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
+#define OHCI_INTR_SF (1 << 2) /* start frame */
+#define OHCI_INTR_RD (1 << 3) /* resume detect */
+#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
+#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
+#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
+#define OHCI_INTR_OC (1 << 30) /* ownership change */
+#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
+
+/* Virtual Root HUB */
+struct virt_root_hub {
+ int devnum; /* Address of Root Hub endpoint */
+ void *dev; /* was urb */
+ void *int_addr;
+ int send;
+ int interval;
+};
+
+/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
+
+/* destination of request */
+#define RH_INTERFACE 0x01
+#define RH_ENDPOINT 0x02
+#define RH_OTHER 0x03
+
+#define RH_CLASS 0x20
+#define RH_VENDOR 0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS 0x0080
+#define RH_CLEAR_FEATURE 0x0100
+#define RH_SET_FEATURE 0x0300
+#define RH_SET_ADDRESS 0x0500
+#define RH_GET_DESCRIPTOR 0x0680
+#define RH_SET_DESCRIPTOR 0x0700
+#define RH_GET_CONFIGURATION 0x0880
+#define RH_SET_CONFIGURATION 0x0900
+#define RH_GET_STATE 0x0280
+#define RH_GET_INTERFACE 0x0A80
+#define RH_SET_INTERFACE 0x0B00
+#define RH_SYNC_FRAME 0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP 0x2000
+
+
+/* Hub port features */
+#define RH_PORT_CONNECTION 0x00
+#define RH_PORT_ENABLE 0x01
+#define RH_PORT_SUSPEND 0x02
+#define RH_PORT_OVER_CURRENT 0x03
+#define RH_PORT_RESET 0x04
+#define RH_PORT_POWER 0x08
+#define RH_PORT_LOW_SPEED 0x09
+
+#define RH_C_PORT_CONNECTION 0x10
+#define RH_C_PORT_ENABLE 0x11
+#define RH_C_PORT_SUSPEND 0x12
+#define RH_C_PORT_OVER_CURRENT 0x13
+#define RH_C_PORT_RESET 0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER 0x00
+#define RH_C_HUB_OVER_CURRENT 0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP 0x00
+#define RH_ENDPOINT_STALL 0x01
+
+#define RH_ACK 0x01
+#define RH_REQ_ERR -1
+#define RH_NACK 0x00
+
+
+/* OHCI ROOT HUB REGISTER MASKS */
+
+/* roothub.portstatus [i] bits */
+#define RH_PS_CCS 0x00000001 /* current connect status */
+#define RH_PS_PES 0x00000002 /* port enable status */
+#define RH_PS_PSS 0x00000004 /* port suspend status */
+#define RH_PS_POCI 0x00000008 /* port over current indicator */
+#define RH_PS_PRS 0x00000010 /* port reset status */
+#define RH_PS_PPS 0x00000100 /* port power status */
+#define RH_PS_LSDA 0x00000200 /* low speed device attached */
+#define RH_PS_CSC 0x00010000 /* connect status change */
+#define RH_PS_PESC 0x00020000 /* port enable status change */
+#define RH_PS_PSSC 0x00040000 /* port suspend status change */
+#define RH_PS_OCIC 0x00080000 /* over current indicator change */
+#define RH_PS_PRSC 0x00100000 /* port reset status change */
+
+/* roothub.status bits */
+#define RH_HS_LPS 0x00000001 /* local power status */
+#define RH_HS_OCI 0x00000002 /* over current indicator */
+#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
+#define RH_HS_LPSC 0x00010000 /* local power status change */
+#define RH_HS_OCIC 0x00020000 /* over current indicator change */
+#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
+
+/* roothub.b masks */
+#define RH_B_DR 0x0000ffff /* device removable flags */
+#define RH_B_PPCM 0xffff0000 /* port power control mask */
+
+/* roothub.a masks */
+#define RH_A_NDP (0xff << 0) /* number of downstream ports */
+#define RH_A_PSM (1 << 8) /* power switching mode */
+#define RH_A_NPS (1 << 9) /* no power switching */
+#define RH_A_DT (1 << 10) /* device type (mbz) */
+#define RH_A_OCPM (1 << 11) /* over current protection mode */
+#define RH_A_NOCP (1 << 12) /* no over current protection */
+#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
+
+/* urb */
+#define N_URB_TD 48
+struct urb_priv {
+ struct ed *ed;
+ __u16 length; /* number of tds associated with this request */
+ __u16 td_cnt; /* number of tds already serviced */
+ int state;
+ unsigned long pipe;
+ int actual_length;
+ struct td *td[N_URB_TD]; /* list pointer to all corresponding TDs
+ associated with this request */
+};
+#define URB_DEL 1
+
+/*
+ * This is the full ohci controller description
+ *
+ * Note how the "proper" USB information is just
+ * a subset of what the full implementation needs. (Linus)
+ */
+
+
+struct ohci {
+ struct ohci_hcca *hcca; /* hcca */
+ /*dma_addr_t hcca_dma; */
+
+ int irq;
+ int disabled; /* e.g. got a UE, we're hung */
+ int sleeping;
+ unsigned long flags; /* for HC bugs */
+
+ struct ohci_regs *regs; /* OHCI controller's memory */
+
+ struct ed *ed_rm_list[2]; /* lists of all endpoints to be removed */
+ struct ed *ed_bulktail; /* last endpoint of bulk list */
+ struct ed *ed_controltail; /* last endpoint of control list */
+ int intrstatus;
+ __u32 hc_control; /* copy of the hc control reg */
+ struct usb_device *dev[32];
+ struct virt_root_hub rh;
+
+ const char *slot_name;
+};
+
+#define NUM_EDS 8 /* num of preallocated endpoint descriptors */
+
+struct ohci_device {
+ struct ed ed[NUM_EDS];
+ int ed_cnt;
+};
+
+/* hcd */
+/* endpoint */
+static int ep_link(struct ohci *ohci, struct ed *ed);
+static int ep_unlink(struct ohci *ohci, struct ed *ed);
+static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe);
+
+/*-------------------------------------------------------------------------*/
+
+/* we need more TDs than EDs */
+#define NUM_TD 64
+
+/* +1 so we can align the storage */
+struct td gtd[NUM_TD + 1];
+
+/* pointers to aligned storage */
+struct td *ptd;
+
+/* TDs ... */
+static inline struct td *td_alloc(struct usb_device *usb_dev)
+{
+ int i;
+ struct td *td;
+
+ td = NULL;
+ for (i = 0; i < NUM_TD; i++) {
+ if (ptd[i].usb_dev == NULL) {
+ td = &ptd[i];
+ td->usb_dev = usb_dev;
+ break;
+ }
+ }
+
+ return td;
+}
+
+static inline void ed_free(struct ed *ed)
+{
+ ed->usb_dev = NULL;
+}
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 5579bf2..923acb9 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -27,6 +27,7 @@ LIB := $(obj)libwatchdog.o
COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
COBJS-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
+COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/watchdog/tnetv107x_wdt.c b/drivers/watchdog/tnetv107x_wdt.c
new file mode 100644
index 0000000..18aadb0
--- /dev/null
+++ b/drivers/watchdog/tnetv107x_wdt.c
@@ -0,0 +1,180 @@
+/*
+ * TNETV107X: Watchdog timer implementation (for reset)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+#define MAX_DIV 0xFFFE0001
+
+struct wdt_regs {
+ u32 kick_lock;
+#define KICK_LOCK_1 0x5555
+#define KICK_LOCK_2 0xaaaa
+ u32 kick;
+
+ u32 change_lock;
+#define CHANGE_LOCK_1 0x6666
+#define CHANGE_LOCK_2 0xbbbb
+ u32 change;
+
+ u32 disable_lock;
+#define DISABLE_LOCK_1 0x7777
+#define DISABLE_LOCK_2 0xcccc
+#define DISABLE_LOCK_3 0xdddd
+ u32 disable;
+
+ u32 prescale_lock;
+#define PRESCALE_LOCK_1 0x5a5a
+#define PRESCALE_LOCK_2 0xa5a5
+ u32 prescale;
+};
+
+static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE;
+
+#define wdt_reg_read(reg) __raw_readl(&regs->reg)
+#define wdt_reg_write(reg, val) __raw_writel((val), &regs->reg)
+
+static int write_prescale_reg(unsigned long prescale_value)
+{
+ wdt_reg_write(prescale_lock, PRESCALE_LOCK_1);
+ if ((wdt_reg_read(prescale_lock) & 0x3) != 0x1)
+ return -1;
+
+ wdt_reg_write(prescale_lock, PRESCALE_LOCK_2);
+ if ((wdt_reg_read(prescale_lock) & 0x3) != 0x3)
+ return -1;
+
+ wdt_reg_write(prescale, prescale_value);
+
+ return 0;
+}
+
+static int write_change_reg(unsigned long initial_timer_value)
+{
+ wdt_reg_write(change_lock, CHANGE_LOCK_1);
+ if ((wdt_reg_read(change_lock) & 0x3) != 0x1)
+ return -1;
+
+ wdt_reg_write(change_lock, CHANGE_LOCK_2);
+ if ((wdt_reg_read(change_lock) & 0x3) != 0x3)
+ return -1;
+
+ wdt_reg_write(change, initial_timer_value);
+
+ return 0;
+}
+
+static int wdt_control(unsigned long disable_value)
+{
+ wdt_reg_write(disable_lock, DISABLE_LOCK_1);
+ if ((wdt_reg_read(disable_lock) & 0x3) != 0x1)
+ return -1;
+
+ wdt_reg_write(disable_lock, DISABLE_LOCK_2);
+ if ((wdt_reg_read(disable_lock) & 0x3) != 0x2)
+ return -1;
+
+ wdt_reg_write(disable_lock, DISABLE_LOCK_3);
+ if ((wdt_reg_read(disable_lock) & 0x3) != 0x3)
+ return -1;
+
+ wdt_reg_write(disable, disable_value);
+ return 0;
+}
+
+static int wdt_set_period(unsigned long msec)
+{
+ unsigned long change_value, count_value;
+ unsigned long prescale_value = 1;
+ unsigned long refclk_khz, maxdiv;
+ int ret;
+
+ refclk_khz = clk_get_rate(TNETV107X_LPSC_WDT_ARM);
+ maxdiv = (MAX_DIV / refclk_khz);
+
+ if ((!msec) || (msec > maxdiv))
+ return -1;
+
+ count_value = refclk_khz * msec;
+ if (count_value > 0xffff) {
+ change_value = count_value / 0xffff + 1;
+ prescale_value = count_value / change_value;
+ } else {
+ change_value = count_value;
+ }
+
+ ret = write_prescale_reg(prescale_value - 1);
+ if (ret)
+ return ret;
+
+ ret = write_change_reg(change_value);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+unsigned long last_wdt = -1;
+
+int wdt_start(unsigned long msecs)
+{
+ int ret;
+ ret = wdt_control(0);
+ if (ret)
+ return ret;
+ ret = wdt_set_period(msecs);
+ if (ret)
+ return ret;
+ ret = wdt_control(1);
+ if (ret)
+ return ret;
+ ret = wdt_kick();
+ last_wdt = msecs;
+ return ret;
+}
+
+int wdt_stop(void)
+{
+ last_wdt = -1;
+ return wdt_control(0);
+}
+
+int wdt_kick(void)
+{
+ wdt_reg_write(kick_lock, KICK_LOCK_1);
+ if ((wdt_reg_read(kick_lock) & 0x3) != 0x1)
+ return -1;
+
+ wdt_reg_write(kick_lock, KICK_LOCK_2);
+ if ((wdt_reg_read(kick_lock) & 0x3) != 0x3)
+ return -1;
+
+ wdt_reg_write(kick, 1);
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ clk_enable(TNETV107X_LPSC_WDT_ARM);
+ wdt_start(1);
+ wdt_kick();
+}
generated by cgit v1.1 at 2024-12-28 14:13:42 +0000