diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/dma/Makefile | 1 | ||||
| -rw-r--r-- | drivers/dma/fsl_dma.c | 178 | ||||
| -rw-r--r-- | drivers/i2c/bfin-twi_i2c.c | 4 | ||||
| -rw-r--r-- | drivers/mtd/spi/macronix.c | 49 | ||||
| -rw-r--r-- | drivers/mtd/spi/sst.c | 24 | ||||
| -rw-r--r-- | drivers/mtd/ubi/build.c | 2 | ||||
| -rw-r--r-- | drivers/spi/Makefile | 1 | ||||
| -rw-r--r-- | drivers/spi/mpc52xx_spi.c | 109 |
8 files changed, 349 insertions, 19 deletions
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index cf29efa..36d99f9 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libdma.a COBJS-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o +COBJS-$(CONFIG_FSL_DMA) += fsl_dma.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c new file mode 100644 index 0000000..df33e7a --- /dev/null +++ b/drivers/dma/fsl_dma.c @@ -0,0 +1,178 @@ +/* + * Copyright 2004,2007,2008 Freescale Semiconductor, Inc. + * (C) Copyright 2002, 2003 Motorola Inc. + * Xianghua Xiao (X.Xiao@motorola.com) + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/fsl_dma.h> + +/* Controller can only transfer 2^26 - 1 bytes at a time */ +#define FSL_DMA_MAX_SIZE (0x3ffffff) + +#if defined(CONFIG_MPC83xx) +#define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_CTM_DIRECT | FSL_DMA_MR_DMSEN) +#else +#define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT) +#endif + + +#if defined(CONFIG_MPC83xx) +dma83xx_t *dma_base = (void *)(CONFIG_SYS_MPC83xx_DMA_ADDR); +#elif defined(CONFIG_MPC85xx) +ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); +#elif defined(CONFIG_MPC86xx) +ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR); +#else +#error "Freescale DMA engine not supported on your processor" +#endif + +static void dma_sync(void) +{ +#if defined(CONFIG_MPC85xx) + asm("sync; isync; msync"); +#elif defined(CONFIG_MPC86xx) + asm("sync; isync"); +#endif +} + +static void out_dma32(volatile unsigned *addr, int val) +{ +#if defined(CONFIG_MPC83xx) + out_le32(addr, val); +#else + out_be32(addr, val); +#endif +} + +static uint in_dma32(volatile unsigned *addr) +{ +#if defined(CONFIG_MPC83xx) + return in_le32(addr); +#else + return in_be32(addr); +#endif +} + +static uint dma_check(void) { + volatile fsl_dma_t *dma = &dma_base->dma[0]; + uint status; + + /* While the channel is busy, spin */ + do { + status = in_dma32(&dma->sr); + } while (status & FSL_DMA_SR_CB); + + /* clear MR[CS] channel start bit */ + out_dma32(&dma->mr, in_dma32(&dma->mr) & ~FSL_DMA_MR_CS); + dma_sync(); + + if (status != 0) + printf ("DMA Error: status = %x\n", status); + + return status; +} + +#if !defined(CONFIG_MPC83xx) +void dma_init(void) { + volatile fsl_dma_t *dma = &dma_base->dma[0]; + + out_dma32(&dma->satr, FSL_DMA_SATR_SREAD_SNOOP); + out_dma32(&dma->datr, FSL_DMA_DATR_DWRITE_SNOOP); + out_dma32(&dma->sr, 0xffffffff); /* clear any errors */ + dma_sync(); +} +#endif + +int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) { + volatile fsl_dma_t *dma = &dma_base->dma[0]; + uint xfer_size; + + while (count) { + xfer_size = MIN(FSL_DMA_MAX_SIZE, count); + + out_dma32(&dma->dar, (uint) dest); + out_dma32(&dma->sar, (uint) src); + out_dma32(&dma->bcr, xfer_size); + dma_sync(); + + /* Prepare mode register */ + out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT); + dma_sync(); + + /* Start the transfer */ + out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT | FSL_DMA_MR_CS); + + count -= xfer_size; + src += xfer_size; + dest += xfer_size; + + dma_sync(); + + if (dma_check()) + return -1; + } + + return 0; +} + +/* + * 85xx/86xx use dma to initialize SDRAM when !CONFIG_ECC_INIT_VIA_DDRCONTROLLER + * while 83xx uses dma to initialize SDRAM when CONFIG_DDR_ECC_INIT_VIA_DMA + */ +#if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \ + !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) || \ + (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA))) +void dma_meminit(uint val, uint size) +{ + uint *p = 0; + uint i = 0; + + for (*p = 0; p < (uint *)(8 * 1024); p++) { + if (((uint)p & 0x1f) == 0) + ppcDcbz((ulong)p); + + *p = (uint)CONFIG_MEM_INIT_VALUE; + + if (((uint)p & 0x1c) == 0x1c) + ppcDcbf((ulong)p); + } + + dmacpy(0x002000, 0, 0x002000); /* 8K */ + dmacpy(0x004000, 0, 0x004000); /* 16K */ + dmacpy(0x008000, 0, 0x008000); /* 32K */ + dmacpy(0x010000, 0, 0x010000); /* 64K */ + dmacpy(0x020000, 0, 0x020000); /* 128K */ + dmacpy(0x040000, 0, 0x040000); /* 256K */ + dmacpy(0x080000, 0, 0x080000); /* 512K */ + dmacpy(0x100000, 0, 0x100000); /* 1M */ + dmacpy(0x200000, 0, 0x200000); /* 2M */ + dmacpy(0x400000, 0, 0x400000); /* 4M */ + + for (i = 1; i < size / 0x800000; i++) + dmacpy((0x800000 * i), 0, 0x800000); +} +#endif diff --git a/drivers/i2c/bfin-twi_i2c.c b/drivers/i2c/bfin-twi_i2c.c index cfe55cd..e790634 100644 --- a/drivers/i2c/bfin-twi_i2c.c +++ b/drivers/i2c/bfin-twi_i2c.c @@ -164,7 +164,7 @@ static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, /* prime the pump */ if (msg.alen) { - len = msg.alen; + len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len; debugi("first byte=0x%02x", *msg.abuf); bfin_write_TWI_XMT_DATA8(*(msg.abuf++)); --msg.alen; @@ -275,7 +275,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) * @chip: i2c chip addr * @addr: memory (register) address in the chip * @alen: byte size of address - * @buffer: buffer to store data read from chip + * @buffer: buffer holding data to write to chip * @len: how many bytes to write * @return: 0 on success, non-0 on failure */ diff --git a/drivers/mtd/spi/macronix.c b/drivers/mtd/spi/macronix.c index 9464c84..fe1310b 100644 --- a/drivers/mtd/spi/macronix.c +++ b/drivers/mtd/spi/macronix.c @@ -49,18 +49,10 @@ #define CMD_MX25XX_DP 0xb9 /* Deep Power-down */ #define CMD_MX25XX_RES 0xab /* Release from DP, and Read Signature */ -#define MXIC_ID_MX2516 0x15 -#define MXIC_ID_MX2520 0x12 -#define MXIC_ID_MX2532 0x16 -#define MXIC_ID_MX2540 0x13 -#define MXIC_ID_MX2564 0x17 -#define MXIC_ID_MX2580 0x14 -#define MXIC_ID_MX25128 0x18 - #define MACRONIX_SR_WIP (1 << 0) /* Write-in-Progress */ struct macronix_spi_flash_params { - u8 idcode1; + u16 idcode; u16 page_size; u16 pages_per_sector; u16 sectors_per_block; @@ -81,13 +73,45 @@ static inline struct macronix_spi_flash *to_macronix_spi_flash(struct spi_flash static const struct macronix_spi_flash_params macronix_spi_flash_table[] = { { - .idcode1 = MXIC_ID_MX25128, + .idcode = 0x2015, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "MX25L1605D", + }, + { + .idcode = 0x2016, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 64, + .name = "MX25L3205D", + }, + { + .idcode = 0x2017, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 128, + .name = "MX25L6405D", + }, + { + .idcode = 0x2018, .page_size = 256, .pages_per_sector = 16, .sectors_per_block = 16, .nr_blocks = 256, .name = "MX25L12805D", }, + { + .idcode = 0x2618, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 256, + .name = "MX25L12855E", + }, }; static int macronix_wait_ready(struct spi_flash *flash, unsigned long timeout) @@ -277,15 +301,16 @@ struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode) const struct macronix_spi_flash_params *params; struct macronix_spi_flash *mcx; unsigned int i; + u16 id = idcode[2] | idcode[1] << 8; for (i = 0; i < ARRAY_SIZE(macronix_spi_flash_table); i++) { params = ¯onix_spi_flash_table[i]; - if (params->idcode1 == idcode[2]) + if (params->idcode == id) break; } if (i == ARRAY_SIZE(macronix_spi_flash_table)) { - debug("SF: Unsupported Macronix ID %02x\n", idcode[1]); + debug("SF: Unsupported Macronix ID %04x\n", id); return NULL; } diff --git a/drivers/mtd/spi/sst.c b/drivers/mtd/spi/sst.c index 62236d4..50e9299 100644 --- a/drivers/mtd/spi/sst.c +++ b/drivers/mtd/spi/sst.c @@ -55,20 +55,36 @@ static inline struct sst_spi_flash *to_sst_spi_flash(struct spi_flash *flash) #define SST_SECTOR_SIZE (4 * 1024) static const struct sst_spi_flash_params sst_spi_flash_table[] = { { - .idcode1 = 0x01, + .idcode1 = 0x8d, .nr_sectors = 128, + .name = "SST25VF040B", + },{ + .idcode1 = 0x8e, + .nr_sectors = 256, + .name = "SST25VF080B", + },{ + .idcode1 = 0x41, + .nr_sectors = 512, + .name = "SST25VF016B", + },{ + .idcode1 = 0x4a, + .nr_sectors = 1024, + .name = "SST25VF032B", + },{ + .idcode1 = 0x01, + .nr_sectors = 16, .name = "SST25WF512", },{ .idcode1 = 0x02, - .nr_sectors = 256, + .nr_sectors = 32, .name = "SST25WF010", },{ .idcode1 = 0x03, - .nr_sectors = 512, + .nr_sectors = 64, .name = "SST25WF020", },{ .idcode1 = 0x04, - .nr_sectors = 1024, + .nr_sectors = 128, .name = "SST25WF040", }, }; diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index 4f50b2d..354e80b 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -536,7 +536,7 @@ static int io_init(struct ubi_device *ubi) */ ubi->peb_size = ubi->mtd->erasesize; - ubi->peb_count = ubi->mtd->size / ubi->mtd->erasesize; + ubi->peb_count = mtd_div_by_eb(ubi->mtd->size, ubi->mtd); ubi->flash_size = ubi->mtd->size; if (ubi->mtd->block_isbad && ubi->mtd->block_markbad) diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 7ffa47d..a9f67a0 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -29,6 +29,7 @@ COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o +COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o diff --git a/drivers/spi/mpc52xx_spi.c b/drivers/spi/mpc52xx_spi.c new file mode 100644 index 0000000..3e96b3f --- /dev/null +++ b/drivers/spi/mpc52xx_spi.c @@ -0,0 +1,109 @@ +/* + * (C) Copyright 2009 + * Frank Bodammer <frank.bodammer@gcd-solutions.de> + * (C) Copyright 2009 Semihalf, Grzegorz Bernacki + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <spi.h> +#include <mpc5xxx.h> + +void spi_init(void) +{ + struct mpc5xxx_spi *spi = (struct mpc5xxx_spi *)MPC5XXX_SPI; + /* + * Its important to use the correct order when initializing the + * registers + */ + out_8(&spi->ddr, 0x0F); /* set all SPI pins as output */ + out_8(&spi->pdr, 0x00); /* set SS low */ + /* SPI is master, SS is general purpose output */ + out_8(&spi->cr1, SPI_CR_MSTR | SPI_CR_SPE); + out_8(&spi->cr2, 0x00); /* normal operation */ + out_8(&spi->brr, 0x77); /* baud rate: IPB clock / 2048 */ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct spi_slave *slave; + + slave = malloc(sizeof(struct spi_slave)); + if (!slave) + return NULL; + + slave->bus = bus; + slave->cs = cs; + + return slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + free(slave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + return; +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct mpc5xxx_spi *spi = (struct mpc5xxx_spi *)MPC5XXX_SPI; + int i, iter = bitlen >> 3; + const uchar *txp = dout; + uchar *rxp = din; + + debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n", + slave->bus, slave->cs, *(uint *) dout, *(uint *) din, bitlen); + + if (flags & SPI_XFER_BEGIN) + setbits_8(&spi->pdr, SPI_PDR_SS); + + for (i = 0; i < iter; i++) { + udelay(1000); + debug("spi_xfer: sending %x\n", txp[i]); + out_8(&spi->dr, txp[i]); + while (!(in_8(&spi->sr) & SPI_SR_SPIF)) { + udelay(1000); + if (in_8(&spi->sr) & SPI_SR_WCOL) { + rxp[i] = in_8(&spi->dr); + puts("spi_xfer: write collision\n"); + return -1; + } + } + rxp[i] = in_8(&spi->dr); + debug("spi_xfer: received %x\n", rxp[i]); + } + if (flags & SPI_XFER_END) + clrbits_8(&spi->pdr, SPI_PDR_SS); + + return 0; +} |