diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 79 | ||||
| -rw-r--r-- | drivers/mmc/mmc.c | 6 | ||||
| -rw-r--r-- | drivers/mmc/mmc_private.h | 3 | ||||
| -rw-r--r-- | drivers/pci/fsl_pci_init.c | 23 | ||||
| -rw-r--r-- | drivers/usb/host/ehci-fsl.c | 10 |
5 files changed, 119 insertions, 2 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index b9bc165..c4719e6 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -506,11 +506,47 @@ static void set_sysctl(struct mmc *mmc, uint clock) esdhc_setbits32(®s->sysctl, clk); } +#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK +static void esdhc_clock_control(struct mmc *mmc, bool enable) +{ + struct fsl_esdhc_cfg *cfg = mmc->priv; + struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; + u32 value; + u32 time_out; + + value = esdhc_read32(®s->sysctl); + + if (enable) + value |= SYSCTL_CKEN; + else + value &= ~SYSCTL_CKEN; + + esdhc_write32(®s->sysctl, value); + + time_out = 20; + value = PRSSTAT_SDSTB; + while (!(esdhc_read32(®s->prsstat) & value)) { + if (time_out == 0) { + printf("fsl_esdhc: Internal clock never stabilised.\n"); + break; + } + time_out--; + mdelay(1); + } +} +#endif + static void esdhc_set_ios(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = mmc->priv; struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; +#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK + /* Select to use peripheral clock */ + esdhc_clock_control(mmc, false); + esdhc_setbits32(®s->scr, ESDHCCTL_PCS); + esdhc_clock_control(mmc, true); +#endif /* Set the clock speed */ set_sysctl(mmc, mmc->clock); @@ -694,6 +730,39 @@ int fsl_esdhc_mmc_init(bd_t *bis) return fsl_esdhc_initialize(bis, cfg); } +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT +void mmc_adapter_card_type_ident(void) +{ + u8 card_id; + u8 value; + + card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; + gd->arch.sdhc_adapter = card_id; + + switch (card_id) { + case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: + break; + case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: + break; + case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: + value = QIXIS_READ(brdcfg[5]); + value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); + QIXIS_WRITE(brdcfg[5], value); + break; + case QIXIS_ESDHC_ADAPTER_TYPE_RSV: + break; + case QIXIS_ESDHC_ADAPTER_TYPE_MMC: + break; + case QIXIS_ESDHC_ADAPTER_TYPE_SD: + break; + case QIXIS_ESDHC_NO_ADAPTER: + break; + default: + break; + } +} +#endif + #ifdef CONFIG_OF_LIBFDT void fdt_fixup_esdhc(void *blob, bd_t *bd) { @@ -707,9 +776,17 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd) } #endif +#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK + do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", + gd->arch.sdhc_clk, 1); +#else do_fixup_by_compat_u32(blob, compat, "clock-frequency", gd->arch.sdhc_clk, 1); - +#endif +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT + do_fixup_by_compat_u32(blob, compat, "adapter-type", + (u32)(gd->arch.sdhc_adapter), 1); +#endif do_fixup_by_compat(blob, compat, "status", "okay", 4 + 1, 1); } diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 3909e14..79e6fee 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1593,6 +1593,9 @@ int mmc_start_init(struct mmc *mmc) if (mmc->has_init) return 0; +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT + mmc_adapter_card_type_ident(); +#endif board_mmc_power_init(); /* made sure it's not NULL earlier */ @@ -1744,6 +1747,9 @@ static void do_preinit(void) list_for_each(entry, &mmc_devices) { m = list_entry(entry, struct mmc, link); +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT + mmc_set_preinit(m, 1); +#endif if (m->preinit) mmc_start_init(m); } diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h index 16dcf9f..447a700 100644 --- a/drivers/mmc/mmc_private.h +++ b/drivers/mmc/mmc_private.h @@ -16,6 +16,9 @@ extern int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data); extern int mmc_send_status(struct mmc *mmc, int timeout); extern int mmc_set_blocklen(struct mmc *mmc, int len); +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT +void mmc_adapter_card_type_ident(void); +#endif #ifndef CONFIG_SPL_BUILD diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 231b075..52792dc 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -444,6 +444,21 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) ltssm = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT; enabled = (ltssm == 0x11) ? 1 : 0; +#ifdef CONFIG_FSL_PCIE_RESET + int i; + /* assert PCIe reset */ + setbits_be32(&pci->pdb_stat, 0x08000000); + (void) in_be32(&pci->pdb_stat); + udelay(1000); + /* clear PCIe reset */ + clrbits_be32(&pci->pdb_stat, 0x08000000); + asm("sync;isync"); + for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) { + pci_hose_read_config_word(hose, dev, PCI_LTSSM, + <ssm); + udelay(1000); + } +#endif } else { /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); */ /* enabled = ltssm >= PCI_LTSSM_L0; */ @@ -682,8 +697,14 @@ void fsl_pci_config_unlock(struct pci_controller *hose) pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); if (pcie_cap != 0x0) { + ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr; + u32 block_rev = in_be32(&pci->block_rev1); /* PCIe - set CFG_READY bit of Configuration Ready Register */ - pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1); + if (block_rev >= PEX_IP_BLK_REV_3_0) + setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY); + else + pci_hose_write_config_byte(hose, dev, + FSL_PCIE_CFG_RDY, 0x1); } else { /* PCI - clear ACL bit of PBFR */ pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr); diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 2dca524..5fd618d 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -138,6 +138,16 @@ int ehci_hcd_init(int index, enum usb_init_type init, if (has_erratum_a007798()) set_txfifothresh(ehci, TXFIFOTHRESH); + if (has_erratum_a004477()) { + /* + * When reset is issued while any ULPI transaction is ongoing + * then it may result to corruption of ULPI Function Control + * Register which eventually causes phy clock to enter low + * power mode which stops the clock. Thus delay is required + * before reset to let ongoing ULPI transaction complete. + */ + udelay(1); + } return 0; } |