diff options
Diffstat (limited to 'drivers')
37 files changed, 594 insertions, 307 deletions
diff --git a/drivers/Makefile b/drivers/Makefile index 00da40b..6294048 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -51,6 +51,7 @@ obj-y += hwmon/ obj-y += misc/ obj-y += pcmcia/ obj-y += dfu/ +obj-$(CONFIG_X86) += pch/ obj-y += rtc/ obj-y += sound/ obj-y += timer/ diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c index dec6230..7717246 100644 --- a/drivers/bios_emulator/atibios.c +++ b/drivers/bios_emulator/atibios.c @@ -226,11 +226,19 @@ This function executes the BIOS POST code on the controller. We assume that at this stage the controller has its I/O and memory space enabled and that all other controllers are in a disabled state. ****************************************************************************/ +#ifdef CONFIG_DM_PCI +static void PCI_doBIOSPOST(struct udevice *pcidev, BE_VGAInfo *vga_info, + int vesa_mode, struct vbe_mode_info *mode_info) +#else static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo *vga_info, int vesa_mode, struct vbe_mode_info *mode_info) +#endif { RMREGS regs; RMSREGS sregs; +#ifdef CONFIG_DM_PCI + pci_dev_t bdf; +#endif /* Determine the value to store in AX for BIOS POST. Per the PCI specs, AH must contain the bus and AL must contain the devfn, encoded as @@ -238,9 +246,14 @@ static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo *vga_info, */ memset(®s, 0, sizeof(regs)); memset(&sregs, 0, sizeof(sregs)); +#ifdef CONFIG_DM_PCI + bdf = dm_pci_get_bdf(pcidev); + regs.x.ax = (int)PCI_BUS(bdf) << 8 | + (int)PCI_DEV(bdf) << 3 | (int)PCI_FUNC(bdf); +#else regs.x.ax = ((int)PCI_BUS(pcidev) << 8) | ((int)PCI_DEV(pcidev) << 3) | (int)PCI_FUNC(pcidev); - +#endif /*Setup the X86 emulator for the VGA BIOS*/ BE_setVGA(vga_info); @@ -281,15 +294,28 @@ NOTE: This function leaves the original memory aperture disabled by leaving it programmed to all 1's. It must be restored to the correct value later. ****************************************************************************/ +#ifdef CONFIG_DM_PCI +static u32 PCI_findBIOSAddr(struct udevice *pcidev, int *bar) +#else static u32 PCI_findBIOSAddr(pci_dev_t pcidev, int *bar) +#endif { u32 base, size; for (*bar = 0x10; *bar <= 0x14; (*bar) += 4) { +#ifdef CONFIG_DM_PCI + dm_pci_read_config32(pcidev, *bar, &base); +#else pci_read_config_dword(pcidev, *bar, &base); +#endif if (!(base & 0x1)) { +#ifdef CONFIG_DM_PCI + dm_pci_write_config32(pcidev, *bar, 0xFFFFFFFF); + dm_pci_read_config32(pcidev, *bar, &size); +#else pci_write_config_dword(pcidev, *bar, 0xFFFFFFFF); pci_read_config_dword(pcidev, *bar, &size); +#endif size = ~(size & ~0xFF) + 1; if (size >= MAX_BIOSLEN) return base & ~0xFF; @@ -312,11 +338,19 @@ necessary). Anyway to fix this we change all I/O mapped base registers and chop off the top bits. ****************************************************************************/ +#ifdef CONFIG_DM_PCI +static void PCI_fixupIObase(struct udevice *pcidev, int reg, u32 *base) +#else static void PCI_fixupIObase(pci_dev_t pcidev, int reg, u32 * base) +#endif { if ((*base & 0x1) && (*base > 0xFFFE)) { *base &= 0xFFFF; +#ifdef CONFIG_DM_PCI + dm_pci_write_config32(pcidev, reg, *base); +#else pci_write_config_dword(pcidev, reg, *base); +#endif } } @@ -331,18 +365,30 @@ Pointers to the mapped BIOS image REMARKS: Maps a pointer to the BIOS image on the graphics card on the PCI bus. ****************************************************************************/ +#ifdef CONFIG_DM_PCI +void *PCI_mapBIOSImage(struct udevice *pcidev) +#else void *PCI_mapBIOSImage(pci_dev_t pcidev) +#endif { u32 BIOSImageBus; int BIOSImageBAR; u8 *BIOSImage; /*Save PCI BAR registers that might get changed*/ +#ifdef CONFIG_DM_PCI + dm_pci_read_config32(pcidev, PCI_ROM_ADDRESS, &saveROMBaseAddress); + dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_0, &saveBaseAddress10); + dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_1, &saveBaseAddress14); + dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_2, &saveBaseAddress18); + dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_4, &saveBaseAddress20); +#else pci_read_config_dword(pcidev, PCI_ROM_ADDRESS, &saveROMBaseAddress); pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_0, &saveBaseAddress10); pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_1, &saveBaseAddress14); pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_2, &saveBaseAddress18); pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_4, &saveBaseAddress20); +#endif /*Fix up I/O base registers to less than 64K */ if(saveBaseAddress14 != 0) @@ -361,13 +407,21 @@ void *PCI_mapBIOSImage(pci_dev_t pcidev) return NULL; } +#ifdef CONFIG_DM_PCI + BIOSImage = dm_pci_bus_to_virt(pcidev, BIOSImageBus, + PCI_REGION_MEM, 0, MAP_NOCACHE); + + /*Change the PCI BAR registers to map it onto the bus.*/ + dm_pci_write_config32(pcidev, BIOSImageBAR, 0); + dm_pci_write_config32(pcidev, PCI_ROM_ADDRESS, BIOSImageBus | 0x1); +#else BIOSImage = pci_bus_to_virt(pcidev, BIOSImageBus, PCI_REGION_MEM, 0, MAP_NOCACHE); /*Change the PCI BAR registers to map it onto the bus.*/ pci_write_config_dword(pcidev, BIOSImageBAR, 0); pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, BIOSImageBus | 0x1); - +#endif udelay(1); /*Check that the BIOS image is valid. If not fail, or return the @@ -387,6 +441,16 @@ pcidev - PCI device info for the video card on the bus REMARKS: Unmaps the BIOS image for the device and restores framebuffer mappings ****************************************************************************/ +#ifdef CONFIG_DM_PCI +void PCI_unmapBIOSImage(struct udevice *pcidev, void *BIOSImage) +{ + dm_pci_write_config32(pcidev, PCI_ROM_ADDRESS, saveROMBaseAddress); + dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_0, saveBaseAddress10); + dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_1, saveBaseAddress14); + dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_2, saveBaseAddress18); + dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_4, saveBaseAddress20); +} +#else void PCI_unmapBIOSImage(pci_dev_t pcidev, void *BIOSImage) { pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, saveROMBaseAddress); @@ -395,6 +459,7 @@ void PCI_unmapBIOSImage(pci_dev_t pcidev, void *BIOSImage) pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_2, saveBaseAddress18); pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_4, saveBaseAddress20); } +#endif /**************************************************************************** PARAMETERS: @@ -408,13 +473,22 @@ REMARKS: Loads and POST's the display controllers BIOS, directly from the BIOS image we can extract over the PCI bus. ****************************************************************************/ +#ifdef CONFIG_DM_PCI +static int PCI_postController(struct udevice *pcidev, uchar *bios_rom, + int bios_len, BE_VGAInfo *vga_info, + int vesa_mode, struct vbe_mode_info *mode_info) +#else static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len, BE_VGAInfo *vga_info, int vesa_mode, struct vbe_mode_info *mode_info) +#endif { u32 bios_image_len; uchar *mapped_bios; uchar *copy_of_bios; +#ifdef CONFIG_DM_PCI + pci_dev_t bdf; +#endif if (bios_rom) { copy_of_bios = bios_rom; @@ -442,9 +516,16 @@ static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len, } /*Save information in vga_info structure*/ +#ifdef CONFIG_DM_PCI + bdf = dm_pci_get_bdf(pcidev); + vga_info->function = PCI_FUNC(bdf); + vga_info->device = PCI_DEV(bdf); + vga_info->bus = PCI_BUS(bdf); +#else vga_info->function = PCI_FUNC(pcidev); vga_info->device = PCI_DEV(pcidev); vga_info->bus = PCI_BUS(pcidev); +#endif vga_info->pcidev = pcidev; vga_info->BIOSImage = copy_of_bios; vga_info->BIOSImageLen = bios_image_len; @@ -462,13 +543,22 @@ static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len, return true; } +#ifdef CONFIG_DM_PCI +int biosemu_setup(struct udevice *pcidev, BE_VGAInfo **vga_infop) +#else int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **vga_infop) +#endif { BE_VGAInfo *VGAInfo; +#ifdef CONFIG_DM_PCI + pci_dev_t bdf = dm_pci_get_bdf(pcidev); printf("videoboot: Booting PCI video card bus %d, function %d, device %d\n", - PCI_BUS(pcidev), PCI_FUNC(pcidev), PCI_DEV(pcidev)); - + PCI_BUS(bdf), PCI_FUNC(bdf), PCI_DEV(bdf)); +#else + printf("videoboot: Booting PCI video card bus %d, function %d, device %d\n", + PCI_BUS(pcidev), PCI_FUNC(pcidev), PCI_DEV(pcidev)); +#endif /*Initialise the x86 BIOS emulator*/ if ((VGAInfo = malloc(sizeof(*VGAInfo))) == NULL) { printf("videoboot: Out of memory!\n"); @@ -486,9 +576,15 @@ void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void)) X86EMU_setupIntrFunc(intnum, (X86EMU_intrFuncs)int_func); } +#ifdef CONFIG_DM_PCI +int biosemu_run(struct udevice *pcidev, uchar *bios_rom, int bios_len, + BE_VGAInfo *vga_info, int clean_up, int vesa_mode, + struct vbe_mode_info *mode_info) +#else int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len, BE_VGAInfo *vga_info, int clean_up, int vesa_mode, struct vbe_mode_info *mode_info) +#endif { /*Post all the display controller BIOS'es*/ if (!PCI_postController(pcidev, bios_rom, bios_len, vga_info, @@ -522,7 +618,12 @@ REMARKS: Boots the PCI/AGP video card on the bus using the Video ROM BIOS image and the X86 BIOS emulator module. ****************************************************************************/ +#ifdef CONFIG_DM_PCI +int BootVideoCardBIOS(struct udevice *pcidev, BE_VGAInfo **pVGAInfo, + int clean_up) +#else int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int clean_up) +#endif { BE_VGAInfo *VGAInfo; int ret; diff --git a/drivers/bios_emulator/bios.c b/drivers/bios_emulator/bios.c index dd4c0a4..77c7f94 100644 --- a/drivers/bios_emulator/bios.c +++ b/drivers/bios_emulator/bios.c @@ -185,12 +185,21 @@ static void X86API int1A(int unused) case 0xB103: /* Find PCI class code */ M.x86.R_AH = DEVICE_NOT_FOUND; #ifdef __KERNEL__ +#ifdef CONFIG_DM_PCI + dm_pci_read_config8(_BE_env.vgaInfo.pcidev, PCI_CLASS_PROG, + &interface); + dm_pci_read_config8(_BE_env.vgaInfo.pcidev, PCI_CLASS_DEVICE, + &subclass); + dm_pci_read_config8(_BE_env.vgaInfo.pcidev, + PCI_CLASS_DEVICE + 1, &baseclass); +#else pci_read_config_byte(_BE_env.vgaInfo.pcidev, PCI_CLASS_PROG, &interface); pci_read_config_byte(_BE_env.vgaInfo.pcidev, PCI_CLASS_DEVICE, &subclass); pci_read_config_byte(_BE_env.vgaInfo.pcidev, PCI_CLASS_DEVICE + 1, &baseclass); +#endif if (M.x86.R_CL == interface && M.x86.R_CH == subclass && (u8) (M.x86.R_ECX >> 16) == baseclass) { #else @@ -209,8 +218,13 @@ static void X86API int1A(int unused) if (M.x86.R_BX == pciSlot) { M.x86.R_AH = SUCCESSFUL; #ifdef __KERNEL__ +# ifdef CONFIG_DM_PCI + dm_pci_read_config8(_BE_env.vgaInfo.pcidev, M.x86.R_DI, + &M.x86.R_CL); +# else pci_read_config_byte(_BE_env.vgaInfo.pcidev, M.x86.R_DI, &M.x86.R_CL); +# endif #else M.x86.R_CL = (u8) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_BYTE, @@ -224,8 +238,13 @@ static void X86API int1A(int unused) if (M.x86.R_BX == pciSlot) { M.x86.R_AH = SUCCESSFUL; #ifdef __KERNEL__ +# ifdef CONFIG_DM_PCI + dm_pci_read_config16(_BE_env.vgaInfo.pcidev, M.x86.R_DI, + &M.x86.R_CX); +# else pci_read_config_word(_BE_env.vgaInfo.pcidev, M.x86.R_DI, &M.x86.R_CX); +# endif #else M.x86.R_CX = (u16) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_WORD, @@ -239,8 +258,13 @@ static void X86API int1A(int unused) if (M.x86.R_BX == pciSlot) { M.x86.R_AH = SUCCESSFUL; #ifdef __KERNEL__ +# ifdef CONFIG_DM_PCI + dm_pci_read_config32(_BE_env.vgaInfo.pcidev, + M.x86.R_DI, &M.x86.R_ECX); +# else pci_read_config_dword(_BE_env.vgaInfo.pcidev, M.x86.R_DI, &M.x86.R_ECX); +# endif #else M.x86.R_ECX = (u32) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_DWORD, @@ -254,8 +278,13 @@ static void X86API int1A(int unused) if (M.x86.R_BX == pciSlot) { M.x86.R_AH = SUCCESSFUL; #ifdef __KERNEL__ +# ifdef CONFIG_DM_PCI + dm_pci_write_config8(_BE_env.vgaInfo.pcidev, + M.x86.R_DI, M.x86.R_CL); +# else pci_write_config_byte(_BE_env.vgaInfo.pcidev, M.x86.R_DI, M.x86.R_CL); +# endif #else PCI_accessReg(M.x86.R_DI, M.x86.R_CL, PCI_WRITE_BYTE, _BE_env.vgaInfo.pciInfo); @@ -268,8 +297,13 @@ static void X86API int1A(int unused) if (M.x86.R_BX == pciSlot) { M.x86.R_AH = SUCCESSFUL; #ifdef __KERNEL__ +# ifdef CONFIG_DM_PCI + dm_pci_write_config32(_BE_env.vgaInfo.pcidev, + M.x86.R_DI, M.x86.R_CX); +# else pci_write_config_word(_BE_env.vgaInfo.pcidev, M.x86.R_DI, M.x86.R_CX); +# endif #else PCI_accessReg(M.x86.R_DI, M.x86.R_CX, PCI_WRITE_WORD, _BE_env.vgaInfo.pciInfo); @@ -282,8 +316,13 @@ static void X86API int1A(int unused) if (M.x86.R_BX == pciSlot) { M.x86.R_AH = SUCCESSFUL; #ifdef __KERNEL__ +# ifdef CONFIG_DM_PCI + dm_pci_write_config32(_BE_env.vgaInfo.pcidev, + M.x86.R_DI, M.x86.R_ECX); +# else pci_write_config_dword(_BE_env.vgaInfo.pcidev, M.x86.R_DI, M.x86.R_ECX); +# endif #else PCI_accessReg(M.x86.R_DI, M.x86.R_ECX, PCI_WRITE_DWORD, _BE_env.vgaInfo.pciInfo); diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index e69de29..990f768 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -0,0 +1,9 @@ +config DISK + bool "Support disk controllers with driver model" + depends on DM + default y if DM + help + This enables a uclass for disk controllers in U-Boot. Various driver + types can use this, such as AHCI/SATA. It does not provide any standard + operations at present. The block device interface has not been converted + to driver model. diff --git a/drivers/block/Makefile b/drivers/block/Makefile index eb8bda9..5eb87e0 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_DISK) += disk-uclass.o obj-$(CONFIG_SCSI_AHCI) += ahci.o obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o obj-$(CONFIG_FSL_SATA) += fsl_sata.o diff --git a/drivers/block/disk-uclass.c b/drivers/block/disk-uclass.c new file mode 100644 index 0000000..d665b35 --- /dev/null +++ b/drivers/block/disk-uclass.c @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> + +UCLASS_DRIVER(disk) = { + .id = UCLASS_DISK, + .name = "disk", +}; diff --git a/drivers/core/lists.c b/drivers/core/lists.c index a1c9478..c4fc216 100644 --- a/drivers/core/lists.c +++ b/drivers/core/lists.c @@ -172,7 +172,8 @@ int lists_bind_fdt(struct udevice *parent, const void *blob, int offset, dm_dbg(" - found match at '%s'\n", entry->name); ret = device_bind(parent, entry, name, NULL, offset, &dev); if (ret) { - dm_warn("Error binding driver '%s'\n", entry->name); + dm_warn("Error binding driver '%s': %d\n", entry->name, + ret); return ret; } else { dev->driver_data = id->data; diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c index 686c320..a0666d0 100644 --- a/drivers/core/syscon-uclass.c +++ b/drivers/core/syscon-uclass.c @@ -32,7 +32,7 @@ static int syscon_pre_probe(struct udevice *dev) return regmap_init_mem(dev, &priv->regmap); } -struct regmap *syscon_get_regmap_by_driver_data(ulong driver_data) +int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp) { struct udevice *dev; struct uclass *uc; @@ -40,22 +40,29 @@ struct regmap *syscon_get_regmap_by_driver_data(ulong driver_data) ret = uclass_get(UCLASS_SYSCON, &uc); if (ret) - return ERR_PTR(ret); + return ret; uclass_foreach_dev(dev, uc) { if (dev->driver_data == driver_data) { - struct syscon_uc_info *priv; - int ret; - - ret = device_probe(dev); - if (ret) - return ERR_PTR(ret); - priv = dev_get_uclass_priv(dev); - - return priv->regmap; + *devp = dev; + return device_probe(dev); } } - return ERR_PTR(-ENODEV); + return -ENODEV; +} + +struct regmap *syscon_get_regmap_by_driver_data(ulong driver_data) +{ + struct syscon_uc_info *priv; + struct udevice *dev; + int ret; + + ret = syscon_get_by_driver_data(driver_data, &dev); + if (ret) + return ERR_PTR(ret); + priv = dev_get_uclass_priv(dev); + + return priv->regmap; } void *syscon_get_first_range(ulong driver_data) diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c index 22defcd..a6dc935 100644 --- a/drivers/dma/apbh_dma.c +++ b/drivers/dma/apbh_dma.c @@ -215,7 +215,7 @@ static int mxs_dma_reset(int channel) #if defined(CONFIG_MX23) uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set); uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET; -#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6)) +#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7)) uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set); uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET; #endif diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 3ed4d89..d603b55 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -10,6 +10,7 @@ #include <fdtdec.h> #include <malloc.h> #include <asm/gpio.h> +#include <linux/bug.h> #include <linux/ctype.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 14adda2..46b83e7 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -58,6 +58,15 @@ config DM_I2C_GPIO bindings are supported. Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt +config SYS_I2C_INTEL + bool "Intel I2C/SMBUS driver" + depends on DM_I2C + help + Add support for the Intel SMBUS driver. So far this driver is just + a stub which perhaps some basic init. There is no implementation of + the I2C API meaning that any I2C operations will immediately fail + for now. + config SYS_I2C_ROCKCHIP bool "Rockchip I2C driver" depends on DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index bbbc0dc..c75c579 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o +obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o diff --git a/drivers/i2c/intel_i2c.c b/drivers/i2c/intel_i2c.c new file mode 100644 index 0000000..3d777ff --- /dev/null +++ b/drivers/i2c/intel_i2c.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/pch.h> + +int intel_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +{ + return -ENOSYS; +} + +int intel_i2c_probe_chip(struct udevice *bus, uint chip_addr, uint chip_flags) +{ + return -ENOSYS; +} + +int intel_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + return 0; +} + +static int intel_i2c_probe(struct udevice *dev) +{ + /* + * So far this is just setup code for ivybridge SMbus. When we have + * a full I2C driver this may need to be moved, generalised or made + * dependant on a particular compatible string. + * + * Set SMBus I/O base + */ + dm_pci_write_config32(dev, SMB_BASE, + SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + + /* Set SMBus enable. */ + dm_pci_write_config8(dev, HOSTC, HST_EN); + + /* Set SMBus I/O space enable. */ + dm_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); + + /* Disable interrupt generation. */ + outb(0, SMBUS_IO_BASE + SMBHSTCTL); + + /* Clear any lingering errors, so transactions can run. */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + debug("SMBus controller enabled\n"); + + return 0; +} + +static const struct dm_i2c_ops intel_i2c_ops = { + .xfer = intel_i2c_xfer, + .probe_chip = intel_i2c_probe_chip, + .set_bus_speed = intel_i2c_set_bus_speed, +}; + +static const struct udevice_id intel_i2c_ids[] = { + { .compatible = "intel,ich-i2c" }, + { } +}; + +U_BOOT_DRIVER(intel_i2c) = { + .name = "i2c_intel", + .id = UCLASS_I2C, + .of_match = intel_i2c_ids, + .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), + .ops = &intel_i2c_ops, + .probe = intel_i2c_probe, +}; diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c index f15cf36..ba019a0 100644 --- a/drivers/mtd/nand/mxs_nand.c +++ b/drivers/mtd/nand/mxs_nand.c @@ -30,7 +30,7 @@ #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512 -#if defined(CONFIG_MX6) +#if (defined(CONFIG_MX6) || defined(CONFIG_MX7)) #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2 #else #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0 @@ -152,7 +152,7 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size, int max_ecc_strength_supported; /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */ - if (is_cpu_type(MXC_CPU_MX6SX)) + if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7)) max_ecc_strength_supported = 62; else max_ecc_strength_supported = 40; diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index f484e62..baf4e2d 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -30,6 +30,7 @@ #include <linux/slab.h> #include <linux/major.h> #else +#include <linux/bug.h> #include <linux/log2.h> #endif #include <linux/err.h> diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c index f2cd32c..d4a6386 100644 --- a/drivers/net/eepro100.c +++ b/drivers/net/eepro100.c @@ -240,23 +240,23 @@ static void eepro100_halt (struct eth_device *dev); static inline int INW (struct eth_device *dev, u_long addr) { - return le16_to_cpu (*(volatile u16 *) (addr + dev->iobase)); + return le16_to_cpu(*(volatile u16 *)(addr + (u_long)dev->iobase)); } static inline void OUTW (struct eth_device *dev, int command, u_long addr) { - *(volatile u16 *) ((addr + dev->iobase)) = cpu_to_le16 (command); + *(volatile u16 *)((addr + (u_long)dev->iobase)) = cpu_to_le16(command); } static inline void OUTL (struct eth_device *dev, int command, u_long addr) { - *(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command); + *(volatile u32 *)((addr + (u_long)dev->iobase)) = cpu_to_le32(command); } #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) static inline int INL (struct eth_device *dev, u_long addr) { - return le32_to_cpu (*(volatile u32 *) (addr + dev->iobase)); + return le32_to_cpu(*(volatile u32 *)(addr + (u_long)dev->iobase)); } static int get_phyreg (struct eth_device *dev, unsigned char addr, diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index bac4610..4b9b372 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -5,6 +5,7 @@ */ #include <common.h> #include <errno.h> +#include <linux/bug.h> #include <asm/io.h> #include <libfdt.h> #include <fdt_support.h> diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 7059c84..97e30f3 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -19,6 +19,7 @@ #include <asm/io.h> #include <phy.h> #include <miiphy.h> +#include <wait_bit.h> #include <watchdog.h> #include <asm/system.h> #include <asm/arch/hardware.h> @@ -448,38 +449,6 @@ static int zynq_gem_init(struct udevice *dev) return 0; } -static int wait_for_bit(const char *func, u32 *reg, const u32 mask, - bool set, unsigned int timeout) -{ - u32 val; - unsigned long start = get_timer(0); - - while (1) { - val = readl(reg); - - if (!set) - val = ~val; - - if ((val & mask) == mask) - return 0; - - if (get_timer(start) > timeout) - break; - - if (ctrlc()) { - puts("Abort\n"); - return -EINTR; - } - - udelay(1); - } - - debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", - func, reg, mask, set); - - return -ETIMEDOUT; -} - static int zynq_gem_send(struct udevice *dev, void *ptr, int len) { u32 addr, size; @@ -521,7 +490,7 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len) printf("TX buffers exhausted in mid frame\n"); return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE, - true, 20000); + true, 20000, true); } /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile new file mode 100644 index 0000000..dde9e86 --- /dev/null +++ b/drivers/pch/Makefile @@ -0,0 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += pch-uclass.o +obj-y += pch7.o +obj-y += pch9.o diff --git a/drivers/pch/pch-uclass.c b/drivers/pch/pch-uclass.c new file mode 100644 index 0000000..4579ed1 --- /dev/null +++ b/drivers/pch/pch-uclass.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <pch.h> +#include <dm/root.h> + +DECLARE_GLOBAL_DATA_PTR; + +int pch_get_sbase(struct udevice *dev, ulong *sbasep) +{ + struct pch_ops *ops = pch_get_ops(dev); + + *sbasep = 0; + if (!ops->get_sbase) + return -ENOSYS; + + return ops->get_sbase(dev, sbasep); +} + +enum pch_version pch_get_version(struct udevice *dev) +{ + struct pch_ops *ops = pch_get_ops(dev); + + if (!ops->get_version) + return -ENOSYS; + + return ops->get_version(dev); +} + +int pch_set_spi_protect(struct udevice *dev, bool protect) +{ + struct pch_ops *ops = pch_get_ops(dev); + + if (!ops->set_spi_protect) + return -ENOSYS; + + return ops->set_spi_protect(dev, protect); +} + +static int pch_uclass_post_bind(struct udevice *bus) +{ + /* + * Scan the device tree for devices + * + * Before relocation, only bind devices marked for pre-relocation + * use. + */ + return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset, + gd->flags & GD_FLG_RELOC ? false : true); +} + +UCLASS_DRIVER(pch) = { + .id = UCLASS_PCH, + .name = "pch", + .post_bind = pch_uclass_post_bind, +}; diff --git a/drivers/pch/pch7.c b/drivers/pch/pch7.c new file mode 100644 index 0000000..ef72422 --- /dev/null +++ b/drivers/pch/pch7.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <pch.h> + +#define BIOS_CTRL 0xd8 + +static int pch7_get_sbase(struct udevice *dev, ulong *sbasep) +{ + u32 rcba; + + dm_pci_read_config32(dev, PCH_RCBA, &rcba); + /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */ + rcba = rcba & 0xffffc000; + *sbasep = rcba + 0x3020; + + return 0; +} + +static enum pch_version pch7_get_version(struct udevice *dev) +{ + return PCHV_7; +} + +static int pch7_set_spi_protect(struct udevice *dev, bool protect) +{ + uint8_t bios_cntl; + + /* Adjust the BIOS write protect to dis/allow write commands */ + dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl); + if (protect) + bios_cntl &= ~BIOS_CTRL_BIOSWE; + else + bios_cntl |= BIOS_CTRL_BIOSWE; + dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl); + + return 0; +} + +static const struct pch_ops pch7_ops = { + .get_sbase = pch7_get_sbase, + .get_version = pch7_get_version, + .set_spi_protect = pch7_set_spi_protect, +}; + +static const struct udevice_id pch7_ids[] = { + { .compatible = "intel,pch7" }, + { } +}; + +U_BOOT_DRIVER(pch7_drv) = { + .name = "intel-pch7", + .id = UCLASS_PCH, + .of_match = pch7_ids, + .ops = &pch7_ops, +}; diff --git a/drivers/pch/pch9.c b/drivers/pch/pch9.c new file mode 100644 index 0000000..529cb02 --- /dev/null +++ b/drivers/pch/pch9.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <pch.h> + +#define SBASE_ADDR 0x54 + +static int pch9_get_sbase(struct udevice *dev, ulong *sbasep) +{ + uint32_t sbase_addr; + + dm_pci_read_config32(dev, SBASE_ADDR, &sbase_addr); + *sbasep = sbase_addr & 0xfffffe00; + + return 0; +} + +static enum pch_version pch9_get_version(struct udevice *dev) +{ + return PCHV_9; +} + +static const struct pch_ops pch9_ops = { + .get_sbase = pch9_get_sbase, + .get_version = pch9_get_version, +}; + +static const struct udevice_id pch9_ids[] = { + { .compatible = "intel,pch9" }, + { } +}; + +U_BOOT_DRIVER(pch9_drv) = { + .name = "intel-pch9", + .id = UCLASS_PCH, + .of_match = pch9_ids, + .ops = &pch9_ops, +}; diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 685df9d..61292d7 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -22,7 +22,7 @@ DECLARE_GLOBAL_DATA_PTR; -static int pci_get_bus(int busnum, struct udevice **busp) +int pci_get_bus(int busnum, struct udevice **busp) { int ret; @@ -41,20 +41,6 @@ static int pci_get_bus(int busnum, struct udevice **busp) return ret; } -struct pci_controller *pci_bus_to_hose(int busnum) -{ - struct udevice *bus; - int ret; - - ret = pci_get_bus(busnum, &bus); - if (ret) { - debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret); - return NULL; - } - - return dev_get_uclass_priv(bus); -} - struct udevice *pci_get_controller(struct udevice *dev) { while (device_is_on_pci_bus(dev)) @@ -1067,6 +1053,14 @@ u32 dm_pci_read_bar32(struct udevice *dev, int barnum) return addr & PCI_BASE_ADDRESS_MEM_MASK; } +void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr) +{ + int bar; + + bar = PCI_BASE_ADDRESS_0 + barnum * 4; + dm_pci_write_config32(dev, bar, addr); +} + static int _dm_pci_bus_to_phys(struct udevice *ctlr, pci_addr_t bus_addr, unsigned long flags, unsigned long skip_mask, phys_addr_t *pa) diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 5cfa135..88bc416 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <dm.h> #include <errno.h> #include <pci.h> @@ -167,8 +168,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) struct pci_region *pci_prefetch; struct pci_region *pci_io; u16 cmdstat, prefechable_64; - /* The root controller has the region information */ - struct pci_controller *ctlr_hose = pci_bus_to_hose(0); + struct udevice *ctlr = pci_get_controller(dev); + struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); pci_mem = ctlr_hose->pci_mem; pci_prefetch = ctlr_hose->pci_prefetch; @@ -248,9 +249,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) struct pci_region *pci_mem; struct pci_region *pci_prefetch; struct pci_region *pci_io; - - /* The root controller has the region information */ - struct pci_controller *ctlr_hose = pci_bus_to_hose(0); + struct udevice *ctlr = pci_get_controller(dev); + struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); pci_mem = ctlr_hose->pci_mem; pci_prefetch = ctlr_hose->pci_prefetch; @@ -311,13 +311,13 @@ int dm_pciauto_config_device(struct udevice *dev) unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev)); unsigned short class; bool enum_only = false; + struct udevice *ctlr = pci_get_controller(dev); + struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); int n; #ifdef CONFIG_PCI_ENUM_ONLY enum_only = true; #endif - /* The root controller has the region information */ - struct pci_controller *ctlr_hose = pci_bus_to_hose(0); pci_mem = ctlr_hose->pci_mem; pci_prefetch = ctlr_hose->pci_prefetch; diff --git a/drivers/pci/pci_compat.c b/drivers/pci/pci_compat.c index dd15eb1..ddaf358 100644 --- a/drivers/pci/pci_compat.c +++ b/drivers/pci/pci_compat.c @@ -12,6 +12,7 @@ #include <pci.h> #include <dm/device-internal.h> #include <dm/lists.h> +#include "pci_internal.h" #define PCI_HOSE_OP(rw, name, size, type) \ int pci_hose_##rw##_config_##name(struct pci_controller *hose, \ @@ -36,3 +37,17 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) return -1; return dm_pci_get_bdf(dev); } + +struct pci_controller *pci_bus_to_hose(int busnum) +{ + struct udevice *bus; + int ret; + + ret = pci_get_bus(busnum, &bus); + if (ret) { + debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret); + return NULL; + } + + return dev_get_uclass_priv(bus); +} diff --git a/drivers/pci/pci_internal.h b/drivers/pci/pci_internal.h index 0867575..616b9c1 100644 --- a/drivers/pci/pci_internal.h +++ b/drivers/pci/pci_internal.h @@ -47,4 +47,16 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus); */ int dm_pciauto_config_device(struct udevice *dev); +/** + * pci_get_bus() - Get a pointer to a bus, given its number + * + * This looks up a PCI bus based on its bus number. The bus is probed if + * necessary. + * + * @busnum: PCI bus number to look up + * @busp: Returns PCI bus on success + * @return 0 on success, or -ve error + */ +int pci_get_bus(int busnum, struct udevice **busp); + #endif diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index ed2f61d..d5bf6f4 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -328,12 +328,12 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), #ifdef CONFIG_BIOSEMU BE_VGAInfo *info; - ret = biosemu_setup(dm_pci_get_bdf(dev), &info); + ret = biosemu_setup(dev, &info); if (ret) goto err; biosemu_set_interrupt_handler(0x15, int15_handler); - ret = biosemu_run(dm_pci_get_bdf(dev), (uchar *)ram, 1 << 16, - info, true, vesa_mode, &mode_info); + ret = biosemu_run(dev, (uchar *)ram, 1 << 16, info, + true, vesa_mode, &mode_info); if (ret) goto err; #endif diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h index 7eaec6a..6bdebf2 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h @@ -7,9 +7,7 @@ #ifndef __PINCTRL_UNIPHIER_H__ #define __PINCTRL_UNIPHIER_H__ -/* TODO: move this to include/linux/bug.h */ -#define BUILD_BUG_ON_ZERO(e) (sizeof(struct { int:-!!(e); })) - +#include <linux/bug.h> #include <linux/kernel.h> #include <linux/types.h> diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 021b211..93dad33 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -423,11 +423,15 @@ const struct dm_serial_ops ns16550_serial_ops = { }; #if CONFIG_IS_ENABLED(OF_CONTROL) +/* + * Please consider existing compatible strings before adding a new + * one to keep this table compact. Or you may add a generic "ns16550" + * compatible string to your dts. + */ static const struct udevice_id ns16550_serial_ids[] = { { .compatible = "ns16550" }, { .compatible = "ns16550a" }, { .compatible = "nvidia,tegra20-uart" }, - { .compatible = "rockchip,rk3036-uart" }, { .compatible = "snps,dw-apb-uart" }, { .compatible = "ti,omap2-uart" }, { .compatible = "ti,omap3-uart" }, diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c index 799ef6a..fcb1e95 100644 --- a/drivers/serial/serial_ns16550.c +++ b/drivers/serial/serial_ns16550.c @@ -127,11 +127,6 @@ static void _serial_putc(const char c, const int port) NS16550_putc(PORT, c); } -static void _serial_putc_raw(const char c, const int port) -{ - NS16550_putc(PORT, c); -} - static void _serial_puts(const char *s, const int port) { while (*s) { @@ -165,12 +160,6 @@ serial_putc_dev(unsigned int dev_index,const char c) } static inline void -serial_putc_raw_dev(unsigned int dev_index,const char c) -{ - _serial_putc_raw(c,dev_index); -} - -static inline void serial_puts_dev(unsigned int dev_index,const char *s) { _serial_puts(s,dev_index); diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 59eaaea..e543b8f 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -5,14 +5,14 @@ * * This file is derived from the flashrom project. */ - #include <common.h> #include <dm.h> #include <errno.h> #include <malloc.h> -#include <spi.h> +#include <pch.h> #include <pci.h> #include <pci_ids.h> +#include <spi.h> #include <asm/io.h> #include "ich.h" @@ -20,10 +20,14 @@ #define SPI_OPCODE_WREN 0x06 #define SPI_OPCODE_FAST_READ 0x0b +#ifdef DEBUG_TRACE +#define debug_trace(fmt, args...) debug(fmt, ##args) +#else +#define debug_trace(x, args...) +#endif + struct ich_spi_platdata { - pci_dev_t dev; /* PCI device number */ - int ich_version; /* Controller version, 7 or 9 */ - bool use_sbase; /* Use SBASE instead of RCB */ + enum pch_version ich_version; /* Controller version, 7 or 9 */ }; struct ich_spi_priv { @@ -52,7 +56,7 @@ static u8 ich_readb(struct ich_spi_priv *priv, int reg) { u8 value = readb(priv->base + reg); - debug("read %2.2x from %4.4x\n", value, reg); + debug_trace("read %2.2x from %4.4x\n", value, reg); return value; } @@ -61,7 +65,7 @@ static u16 ich_readw(struct ich_spi_priv *priv, int reg) { u16 value = readw(priv->base + reg); - debug("read %4.4x from %4.4x\n", value, reg); + debug_trace("read %4.4x from %4.4x\n", value, reg); return value; } @@ -70,7 +74,7 @@ static u32 ich_readl(struct ich_spi_priv *priv, int reg) { u32 value = readl(priv->base + reg); - debug("read %8.8x from %4.4x\n", value, reg); + debug_trace("read %8.8x from %4.4x\n", value, reg); return value; } @@ -78,19 +82,19 @@ static u32 ich_readl(struct ich_spi_priv *priv, int reg) static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg) { writeb(value, priv->base + reg); - debug("wrote %2.2x to %4.4x\n", value, reg); + debug_trace("wrote %2.2x to %4.4x\n", value, reg); } static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg) { writew(value, priv->base + reg); - debug("wrote %4.4x to %4.4x\n", value, reg); + debug_trace("wrote %4.4x to %4.4x\n", value, reg); } static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg) { writel(value, priv->base + reg); - debug("wrote %8.8x to %4.4x\n", value, reg); + debug_trace("wrote %8.8x to %4.4x\n", value, reg); } static void write_reg(struct ich_spi_priv *priv, const void *value, @@ -116,40 +120,16 @@ static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr) ich_writel(ctlr, ichspi_bbar, ctlr->bbar); } -/* - * Check if this device ID matches one of supported Intel PCH devices. - * - * Return the ICH version if there is a match, or zero otherwise. - */ -static int get_ich_version(uint16_t device_id) -{ - if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC || - device_id == PCI_DEVICE_ID_INTEL_ITC_LPC || - device_id == PCI_DEVICE_ID_INTEL_QRK_ILB) - return 7; - - if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && - device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || - (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && - device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) || - device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC || - device_id == PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC || - device_id == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LPC) - return 9; - - return 0; -} - /* @return 1 if the SPI flash supports the 33MHz speed */ -static int ich9_can_do_33mhz(pci_dev_t dev) +static int ich9_can_do_33mhz(struct udevice *dev) { u32 fdod, speed; /* Observe SPI Descriptor Component Section 0 */ - pci_write_config_dword(dev, 0xb0, 0x1000); + dm_pci_write_config32(dev->parent, 0xb0, 0x1000); /* Extract the Write/Erase SPI Frequency from descriptor */ - pci_read_config_dword(dev, 0xb4, &fdod); + dm_pci_read_config32(dev->parent, 0xb4, &fdod); /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */ speed = (fdod >> 21) & 7; @@ -157,59 +137,22 @@ static int ich9_can_do_33mhz(pci_dev_t dev) return speed == 1; } -static int ich_find_spi_controller(struct ich_spi_platdata *ich) -{ - int last_bus = pci_last_busno(); - int bus; - - if (last_bus == -1) { - debug("No PCI busses?\n"); - return -ENODEV; - } - - for (bus = 0; bus <= last_bus; bus++) { - uint16_t vendor_id, device_id; - uint32_t ids; - pci_dev_t dev; - - dev = PCI_BDF(bus, 31, 0); - pci_read_config_dword(dev, 0, &ids); - vendor_id = ids; - device_id = ids >> 16; - - if (vendor_id == PCI_VENDOR_ID_INTEL) { - ich->dev = dev; - ich->ich_version = get_ich_version(device_id); - if (device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC) - ich->use_sbase = true; - return ich->ich_version == 0 ? -ENODEV : 0; - } - } - - debug("ICH SPI: No ICH found.\n"); - return -ENODEV; -} - -static int ich_init_controller(struct ich_spi_platdata *plat, +static int ich_init_controller(struct udevice *dev, + struct ich_spi_platdata *plat, struct ich_spi_priv *ctlr) { - uint8_t *rcrb; /* Root Complex Register Block */ - uint32_t rcba; /* Root Complex Base Address */ - uint32_t sbase_addr; - uint8_t *sbase; - - pci_read_config_dword(plat->dev, 0xf0, &rcba); - /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ - rcrb = (uint8_t *)(rcba & 0xffffc000); + ulong sbase_addr; + void *sbase; /* SBASE is similar */ - pci_read_config_dword(plat->dev, 0x54, &sbase_addr); - sbase = (uint8_t *)(sbase_addr & 0xfffffe00); + pch_get_sbase(dev->parent, &sbase_addr); + sbase = (void *)sbase_addr; + debug("%s: sbase=%p\n", __func__, sbase); - if (plat->ich_version == 7) { - struct ich7_spi_regs *ich7_spi; + if (plat->ich_version == PCHV_7) { + struct ich7_spi_regs *ich7_spi = sbase; - ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020); + ich7_spi = (struct ich7_spi_regs *)sbase; ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK; ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu); ctlr->menubytes = sizeof(ich7_spi->opmenu); @@ -222,13 +165,9 @@ static int ich_init_controller(struct ich_spi_platdata *plat, ctlr->bbar = offsetof(struct ich7_spi_regs, bbar); ctlr->preop = offsetof(struct ich7_spi_regs, preop); ctlr->base = ich7_spi; - } else if (plat->ich_version == 9) { - struct ich9_spi_regs *ich9_spi; + } else if (plat->ich_version == PCHV_9) { + struct ich9_spi_regs *ich9_spi = sbase; - if (plat->use_sbase) - ich9_spi = (struct ich9_spi_regs *)sbase; - else - ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800); ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu); ctlr->menubytes = sizeof(ich9_spi->opmenu); @@ -252,9 +191,9 @@ static int ich_init_controller(struct ich_spi_platdata *plat, /* Work out the maximum speed we can support */ ctlr->max_speed = 20000000; - if (plat->ich_version == 9 && ich9_can_do_33mhz(plat->dev)) + if (plat->ich_version == PCHV_9 && ich9_can_do_33mhz(dev)) ctlr->max_speed = 33000000; - debug("ICH SPI: Version %d detected at %p, speed %ld\n", + debug("ICH SPI: Version ID %d detected at %p, speed %ld\n", plat->ich_version, ctlr->base, ctlr->max_speed); ich_set_bbar(ctlr, 0); @@ -447,7 +386,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, } memcpy(trans->cmd, dout, bytes); trans->cmd_len = bytes; - debug("ICH SPI: Saved %d bytes\n", bytes); + debug_trace("ICH SPI: Saved %d bytes\n", bytes); return 0; } @@ -462,7 +401,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, trans->out = trans->cmd; trans->bytesout = trans->cmd_len; using_cmd = 1; - debug("ICH SPI: Using %d bytes\n", trans->cmd_len); + debug_trace("ICH SPI: Using %d bytes\n", trans->cmd_len); } else { trans->out = dout; trans->bytesout = dout ? bytes : 0; @@ -481,7 +420,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, if (ret < 0) return ret; - if (plat->ich_version == 7) + if (plat->ich_version == PCHV_7) ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); else ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); @@ -520,7 +459,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, if (using_cmd && dout && bytes) { trans->out = dout; trans->bytesout = bytes; - debug("ICH SPI: Moving to data, %d bytes\n", bytes); + debug_trace("ICH SPI: Moving to data, %d bytes\n", bytes); } /* Preset control fields */ @@ -676,30 +615,30 @@ int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit, return 0; } -static int ich_spi_probe(struct udevice *bus) +static int ich_spi_probe(struct udevice *dev) { - struct ich_spi_platdata *plat = dev_get_platdata(bus); - struct ich_spi_priv *priv = dev_get_priv(bus); + struct ich_spi_platdata *plat = dev_get_platdata(dev); + struct ich_spi_priv *priv = dev_get_priv(dev); uint8_t bios_cntl; int ret; - ret = ich_init_controller(plat, priv); + /* Check the ICH version */ + plat->ich_version = pch_get_version(dev->parent); + + ret = ich_init_controller(dev, plat, priv); if (ret) return ret; - /* - * Disable the BIOS write protect so write commands are allowed. On - * v9, deassert SMM BIOS Write Protect Disable. - */ - if (plat->use_sbase) { + /* Disable the BIOS write protect so write commands are allowed */ + ret = pch_set_spi_protect(dev->parent, false); + if (ret == -ENOSYS) { bios_cntl = ich_readb(priv, priv->bcr); bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */ bios_cntl |= 1; /* Write Protect Disable (WPD) */ ich_writeb(priv, bios_cntl, priv->bcr); - } else { - pci_read_config_byte(plat->dev, 0xdc, &bios_cntl); - if (plat->ich_version == 9) - bios_cntl &= ~BIT(5); - pci_write_config_byte(plat->dev, 0xdc, bios_cntl | 0x1); + } else if (ret) { + debug("%s: Failed to disable write-protect: err=%d\n", + __func__, ret); + return ret; } priv->cur_speed = priv->max_speed; @@ -707,18 +646,6 @@ static int ich_spi_probe(struct udevice *bus) return 0; } -static int ich_spi_ofdata_to_platdata(struct udevice *bus) -{ - struct ich_spi_platdata *plat = dev_get_platdata(bus); - int ret; - - ret = ich_find_spi_controller(plat); - if (ret) - return ret; - - return 0; -} - static int ich_spi_set_speed(struct udevice *bus, uint speed) { struct ich_spi_priv *priv = dev_get_priv(bus); @@ -751,7 +678,7 @@ static int ich_spi_child_pre_probe(struct udevice *dev) * ICH 7 SPI controller only supports array read command * and byte program command for SST flash */ - if (plat->ich_version == 7) { + if (plat->ich_version == PCHV_7) { slave->mode_rx = SPI_RX_SLOW; slave->mode = SPI_TX_BYTE; } @@ -779,7 +706,6 @@ U_BOOT_DRIVER(ich_spi) = { .id = UCLASS_SPI, .of_match = ich_spi_ids, .ops = &ich_spi_ops, - .ofdata_to_platdata = ich_spi_ofdata_to_platdata, .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata), .priv_auto_alloc_size = sizeof(struct ich_spi_priv), .child_pre_probe = ich_spi_child_pre_probe, diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 8ff949d..25ccc01 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -18,6 +18,7 @@ #include <malloc.h> #include <asm/dma-mapping.h> #include <usb/lin_gadget_compat.h> +#include <linux/bug.h> #include <linux/list.h> #include <linux/usb/ch9.h> diff --git a/drivers/usb/dwc3/linux-compat.h b/drivers/usb/dwc3/linux-compat.h index 6c9c279..9e944a3 100644 --- a/drivers/usb/dwc3/linux-compat.h +++ b/drivers/usb/dwc3/linux-compat.h @@ -17,8 +17,6 @@ #define dev_WARN(dev, format, arg...) debug(format, ##arg) #define WARN_ON_ONCE(val) debug("Error %d\n", val) -#define BUILD_BUG_ON_NOT_POWER_OF_2(n) - static inline size_t strlcat(char *dest, const char *src, size_t n) { strcat(dest, src); diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index b272c57..c6727c3 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -13,6 +13,7 @@ #include <memalign.h> #include <phys2bus.h> #include <usbroothubdes.h> +#include <wait_bit.h> #include <asm/io.h> #include "dwc2.h" @@ -53,27 +54,6 @@ static struct dwc2_priv local; /* * DWC2 IP interface */ -static int wait_for_bit(void *reg, const uint32_t mask, bool set) -{ - unsigned int timeout = 1000000; - uint32_t val; - - while (--timeout) { - val = readl(reg); - if (!set) - val = ~val; - - if ((val & mask) == mask) - return 0; - - udelay(1); - } - - debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", - __func__, reg, mask, set); - - return -ETIMEDOUT; -} /* * Initializes the FSLSPClkSel field of the HCFG register @@ -118,7 +98,8 @@ static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num) writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET), ®s->grstctl); - ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_TXFFLSH, 0); + ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_TXFFLSH, + false, 1000, false); if (ret) printf("%s: Timeout!\n", __func__); @@ -136,7 +117,8 @@ static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs) int ret; writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl); - ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_RXFFLSH, 0); + ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_RXFFLSH, + false, 1000, false); if (ret) printf("%s: Timeout!\n", __func__); @@ -153,13 +135,15 @@ static void dwc_otg_core_reset(struct dwc2_core_regs *regs) int ret; /* Wait for AHB master IDLE state. */ - ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_AHBIDLE, 1); + ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_AHBIDLE, + true, 1000, false); if (ret) printf("%s: Timeout!\n", __func__); /* Core Soft Reset */ writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl); - ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_CSFTRST, 0); + ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_CSFTRST, + false, 1000, false); if (ret) printf("%s: Timeout!\n", __func__); @@ -244,8 +228,8 @@ static void dwc_otg_core_host_init(struct dwc2_core_regs *regs) clrsetbits_le32(®s->hc_regs[i].hcchar, DWC2_HCCHAR_EPDIR, DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS); - ret = wait_for_bit(®s->hc_regs[i].hcchar, - DWC2_HCCHAR_CHEN, 0); + ret = wait_for_bit(__func__, ®s->hc_regs[i].hcchar, + DWC2_HCCHAR_CHEN, false, 1000, false); if (ret) printf("%s: Timeout!\n", __func__); } @@ -745,7 +729,8 @@ int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle) int ret; uint32_t hcint, hctsiz; - ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true); + ret = wait_for_bit(__func__, &hc_regs->hcint, DWC2_HCINT_CHHLTD, true, + 1000, false); if (ret) return ret; diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 2666351..e1c67f7 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -8,6 +8,7 @@ #include <common.h> #include <usb.h> #include <errno.h> +#include <wait_bit.h> #include <linux/compiler.h> #include <usb/ehci-fsl.h> #include <asm/io.h> @@ -117,32 +118,6 @@ static void usb_power_config(int index) pll_480_ctrl_set); } -static int wait_for_bit(u32 *reg, const u32 mask, bool set) -{ - u32 val; - const unsigned int timeout = 10000; - unsigned long start = get_timer(0); - - while(1) { - val = readl(reg); - if (!set) - val = ~val; - - if ((val & mask) == mask) - return 0; - - if (get_timer(start) > timeout) - break; - - udelay(1); - } - - debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", - __func__, reg, mask, set); - - return -ETIMEDOUT; -} - /* Return 0 : host node, <>0 : device mode */ static int usb_phy_enable(int index, struct usb_ehci *ehci) { @@ -160,12 +135,13 @@ static int usb_phy_enable(int index, struct usb_ehci *ehci) /* Stop then Reset */ clrbits_le32(usb_cmd, UCMD_RUN_STOP); - ret = wait_for_bit(usb_cmd, UCMD_RUN_STOP, 0); + ret = wait_for_bit(__func__, usb_cmd, UCMD_RUN_STOP, false, 10000, + false); if (ret) return ret; setbits_le32(usb_cmd, UCMD_RESET); - ret = wait_for_bit(usb_cmd, UCMD_RESET, 0); + ret = wait_for_bit(__func__, usb_cmd, UCMD_RESET, false, 10000, false); if (ret) return ret; diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index cda1c6d..f21a1fa 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -137,11 +137,17 @@ static int ehci_pci_remove(struct udevice *dev) return 0; } +static const struct udevice_id ehci_pci_ids[] = { + { .compatible = "ehci-pci" }, + { } +}; + U_BOOT_DRIVER(ehci_pci) = { .name = "ehci_pci", .id = UCLASS_USB, .probe = ehci_pci_probe, .remove = ehci_pci_remove, + .of_match = ehci_pci_ids, .ops = &ehci_usb_ops, .platdata_auto_alloc_size = sizeof(struct usb_platdata), .priv_auto_alloc_size = sizeof(struct ehci_pci_priv), diff --git a/drivers/usb/host/ohci-lpc32xx.c b/drivers/usb/host/ohci-lpc32xx.c index 48d338e..9245126 100644 --- a/drivers/usb/host/ohci-lpc32xx.c +++ b/drivers/usb/host/ohci-lpc32xx.c @@ -10,6 +10,7 @@ #include <common.h> #include <errno.h> +#include <wait_bit.h> #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/clk.h> @@ -80,30 +81,6 @@ struct otg_regs { static struct otg_regs *otg = (struct otg_regs *)USB_BASE; static struct clk_pm_regs *clk_pwr = (struct clk_pm_regs *)CLK_PM_BASE; -static int wait_for_bit(void *reg, const u32 mask, bool set) -{ - u32 val; - unsigned long start = get_timer(0); - - while (1) { - val = readl(reg); - if (!set) - val = ~val; - - if ((val & mask) == mask) - return 0; - - if (get_timer(start) > CONFIG_SYS_HZ) - break; - - udelay(1); - } - - error("Timeout (reg=%p mask=%08x wait_set=%i)\n", reg, mask, set); - - return -ETIMEDOUT; -} - static int isp1301_set_value(int reg, u8 value) { return i2c_write(ISP1301_I2C_ADDR, reg, 1, &value, 1); @@ -158,7 +135,8 @@ static int usbpll_setup(void) setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_POSTDIV_2POW(0x01)); setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_PWRUP); - ret = wait_for_bit(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_STS, 1); + ret = wait_for_bit(__func__, &clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_STS, + true, CONFIG_SYS_HZ, false); if (ret) return ret; @@ -183,7 +161,8 @@ int usb_cpu_init(void) /* enable I2C clock */ writel(OTG_CLK_I2C_EN, &otg->otg_clk_ctrl); - ret = wait_for_bit(&otg->otg_clk_sts, OTG_CLK_I2C_EN, 1); + ret = wait_for_bit(__func__, &otg->otg_clk_sts, OTG_CLK_I2C_EN, true, + CONFIG_SYS_HZ, false); if (ret) return ret; @@ -203,7 +182,8 @@ int usb_cpu_init(void) OTG_CLK_I2C_EN | OTG_CLK_HOST_EN; writel(mask, &otg->otg_clk_ctrl); - ret = wait_for_bit(&otg->otg_clk_sts, mask, 1); + ret = wait_for_bit(__func__, &otg->otg_clk_sts, mask, true, + CONFIG_SYS_HZ, false); if (ret) return ret; |