diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpio/Kconfig | 7 | ||||
| -rw-r--r-- | drivers/gpio/pca953x.c | 4 | ||||
| -rw-r--r-- | drivers/gpio/zynq_gpio.c | 338 | ||||
| -rw-r--r-- | drivers/i2c/Kconfig | 7 | ||||
| -rw-r--r-- | drivers/i2c/Makefile | 1 | ||||
| -rw-r--r-- | drivers/i2c/i2c-cdns.c | 335 |
6 files changed, 596 insertions, 96 deletions
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index f56a606..2b4624d 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -136,4 +136,11 @@ config MVEBU_GPIO help Say yes here to support Marvell MVEBU (Armada XP/38x) GPIOs. +config ZYNQ_GPIO + bool "Zynq GPIO driver" + depends on DM_GPIO && (ARCH_ZYNQ || ARCH_ZYNQMP) + default y + help + Supports GPIO access on Zynq SoC. + endmenu diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c index 932dfe9..238e028 100644 --- a/drivers/gpio/pca953x.c +++ b/drivers/gpio/pca953x.c @@ -217,7 +217,7 @@ int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* All commands but "device" require 'maxargs' arguments */ if (!c || !((argc == (c->maxargs)) || - (((int)c->cmd == PCA953X_CMD_DEVICE) && + (((long)c->cmd == PCA953X_CMD_DEVICE) && (argc == (c->maxargs - 1))))) { return CMD_RET_USAGE; } @@ -230,7 +230,7 @@ int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (argc > 3) ul_arg3 = simple_strtoul(argv[3], NULL, 16) & 0x1; - switch ((int)c->cmd) { + switch ((long)c->cmd) { #ifdef CONFIG_CMD_PCA953X_INFO case PCA953X_CMD_INFO: ret = pca953x_info(chip); diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c index 83a2c46..3a995f6 100644 --- a/drivers/gpio/zynq_gpio.c +++ b/drivers/gpio/zynq_gpio.c @@ -13,6 +13,141 @@ #include <asm/gpio.h> #include <asm/io.h> #include <asm/errno.h> +#include <dm.h> +#include <fdtdec.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Maximum banks */ +#define ZYNQ_GPIO_MAX_BANK 4 + +#define ZYNQ_GPIO_BANK0_NGPIO 32 +#define ZYNQ_GPIO_BANK1_NGPIO 22 +#define ZYNQ_GPIO_BANK2_NGPIO 32 +#define ZYNQ_GPIO_BANK3_NGPIO 32 + +#define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \ + ZYNQ_GPIO_BANK1_NGPIO + \ + ZYNQ_GPIO_BANK2_NGPIO + \ + ZYNQ_GPIO_BANK3_NGPIO) + +#define ZYNQMP_GPIO_MAX_BANK 6 + +#define ZYNQMP_GPIO_BANK0_NGPIO 26 +#define ZYNQMP_GPIO_BANK1_NGPIO 26 +#define ZYNQMP_GPIO_BANK2_NGPIO 26 +#define ZYNQMP_GPIO_BANK3_NGPIO 32 +#define ZYNQMP_GPIO_BANK4_NGPIO 32 +#define ZYNQMP_GPIO_BANK5_NGPIO 32 + +#define ZYNQMP_GPIO_NR_GPIOS 174 + +#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0 +#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \ + ZYNQ##str##_GPIO_BANK0_NGPIO - 1) +#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1) +#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \ + ZYNQ##str##_GPIO_BANK1_NGPIO - 1) +#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1) +#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \ + ZYNQ##str##_GPIO_BANK2_NGPIO - 1) +#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1) +#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \ + ZYNQ##str##_GPIO_BANK3_NGPIO - 1) +#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1) +#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \ + ZYNQ##str##_GPIO_BANK4_NGPIO - 1) +#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1) +#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \ + ZYNQ##str##_GPIO_BANK5_NGPIO - 1) + +/* Register offsets for the GPIO device */ +/* LSW Mask & Data -WO */ +#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK)) +/* MSW Mask & Data -WO */ +#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK)) +/* Data Register-RW */ +#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK)) +/* Direction mode reg-RW */ +#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) +/* Output enable reg-RW */ +#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK)) +/* Interrupt mask reg-RO */ +#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK)) +/* Interrupt enable reg-WO */ +#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK)) +/* Interrupt disable reg-WO */ +#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK)) +/* Interrupt status reg-RO */ +#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK)) +/* Interrupt type reg-RW */ +#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK)) +/* Interrupt polarity reg-RW */ +#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK)) +/* Interrupt on any, reg-RW */ +#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK)) + +/* Disable all interrupts mask */ +#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF + +/* Mid pin number of a bank */ +#define ZYNQ_GPIO_MID_PIN_NUM 16 + +/* GPIO upper 16 bit mask */ +#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000 + +struct zynq_gpio_privdata { + phys_addr_t base; + const struct zynq_platform_data *p_data; +}; + +/** + * struct zynq_platform_data - zynq gpio platform data structure + * @label: string to store in gpio->label + * @ngpio: max number of gpio pins + * @max_bank: maximum number of gpio banks + * @bank_min: this array represents bank's min pin + * @bank_max: this array represents bank's max pin + */ +struct zynq_platform_data { + const char *label; + u16 ngpio; + int max_bank; + int bank_min[ZYNQMP_GPIO_MAX_BANK]; + int bank_max[ZYNQMP_GPIO_MAX_BANK]; +}; + +static const struct zynq_platform_data zynqmp_gpio_def = { + .label = "zynqmp_gpio", + .ngpio = ZYNQMP_GPIO_NR_GPIOS, + .max_bank = ZYNQMP_GPIO_MAX_BANK, + .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP), + .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP), + .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP), + .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP), + .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP), + .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP), + .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP), + .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP), + .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP), + .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP), + .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP), + .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP), +}; + +static const struct zynq_platform_data zynq_gpio_def = { + .label = "zynq_gpio", + .ngpio = ZYNQ_GPIO_NR_GPIOS, + .max_bank = ZYNQ_GPIO_MAX_BANK, + .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(), + .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(), + .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(), + .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(), + .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(), + .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(), + .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(), + .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(), +}; /** * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank @@ -27,88 +162,71 @@ */ static inline void zynq_gpio_get_bank_pin(unsigned int pin_num, unsigned int *bank_num, - unsigned int *bank_pin_num) + unsigned int *bank_pin_num, + struct udevice *dev) { - switch (pin_num) { - case ZYNQ_GPIO_BANK0_PIN_MIN ... ZYNQ_GPIO_BANK0_PIN_MAX: - *bank_num = 0; - *bank_pin_num = pin_num; - break; - case ZYNQ_GPIO_BANK1_PIN_MIN ... ZYNQ_GPIO_BANK1_PIN_MAX: - *bank_num = 1; - *bank_pin_num = pin_num - ZYNQ_GPIO_BANK1_PIN_MIN; - break; - case ZYNQ_GPIO_BANK2_PIN_MIN ... ZYNQ_GPIO_BANK2_PIN_MAX: - *bank_num = 2; - *bank_pin_num = pin_num - ZYNQ_GPIO_BANK2_PIN_MIN; - break; - case ZYNQ_GPIO_BANK3_PIN_MIN ... ZYNQ_GPIO_BANK3_PIN_MAX: - *bank_num = 3; - *bank_pin_num = pin_num - ZYNQ_GPIO_BANK3_PIN_MIN; - break; - default: - printf("invalid GPIO pin number: %u\n", pin_num); + struct zynq_gpio_privdata *priv = dev_get_priv(dev); + int bank; + + for (bank = 0; bank < priv->p_data->max_bank; bank++) { + if ((pin_num >= priv->p_data->bank_min[bank]) && + (pin_num <= priv->p_data->bank_max[bank])) { + *bank_num = bank; + *bank_pin_num = pin_num - + priv->p_data->bank_min[bank]; + return; + } + } + + if (bank >= priv->p_data->max_bank) { + printf("Inavlid bank and pin num\n"); *bank_num = 0; *bank_pin_num = 0; - break; } } -int gpio_is_valid(unsigned gpio) +static int gpio_is_valid(unsigned gpio, struct udevice *dev) { - return (gpio >= 0) && (gpio < ZYNQ_GPIO_NR_GPIOS); + struct zynq_gpio_privdata *priv = dev_get_priv(dev); + + return (gpio >= 0) && (gpio < priv->p_data->ngpio); } -static int check_gpio(unsigned gpio) +static int check_gpio(unsigned gpio, struct udevice *dev) { - if (!gpio_is_valid(gpio)) { + if (!gpio_is_valid(gpio, dev)) { printf("ERROR : check_gpio: invalid GPIO %d\n", gpio); return -1; } return 0; } -/** - * gpio_get_value - Get the state of the specified pin of GPIO device - * @gpio: gpio pin number within the device - * - * This function reads the state of the specified pin of the GPIO device. - * - * Return: 0 if the pin is low, 1 if pin is high. - */ -int gpio_get_value(unsigned gpio) +static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio) { u32 data; unsigned int bank_num, bank_pin_num; + struct zynq_gpio_privdata *priv = dev_get_priv(dev); - if (check_gpio(gpio) < 0) + if (check_gpio(gpio, dev) < 0) return -1; - zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num); + zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); - data = readl(ZYNQ_GPIO_BASE_ADDRESS + + data = readl(priv->base + ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); return (data >> bank_pin_num) & 1; } -/** - * gpio_set_value - Modify the value of the pin with specified value - * @gpio: gpio pin number within the device - * @value: value used to modify the value of the specified pin - * - * This function calculates the register offset (i.e to lower 16 bits or - * upper 16 bits) based on the given pin number and sets the value of a - * gpio pin to the specified value. The value is either 0 or non-zero. - */ -int gpio_set_value(unsigned gpio, int value) +static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value) { unsigned int reg_offset, bank_num, bank_pin_num; + struct zynq_gpio_privdata *priv = dev_get_priv(dev); - if (check_gpio(gpio) < 0) + if (check_gpio(gpio, dev) < 0) return -1; - zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num); + zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) { /* only 16 data bits in bit maskable reg */ @@ -126,95 +244,127 @@ int gpio_set_value(unsigned gpio, int value) value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) & ((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK); - writel(value, ZYNQ_GPIO_BASE_ADDRESS + reg_offset); + writel(value, priv->base + reg_offset); return 0; } -/** - * gpio_direction_input - Set the direction of the specified GPIO pin as input - * @gpio: gpio pin number within the device - * - * This function uses the read-modify-write sequence to set the direction of - * the gpio pin as input. - * - * Return: -1 if invalid gpio specified, 0 if successul - */ -int gpio_direction_input(unsigned gpio) +static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio) { u32 reg; unsigned int bank_num, bank_pin_num; + struct zynq_gpio_privdata *priv = dev_get_priv(dev); - if (check_gpio(gpio) < 0) + if (check_gpio(gpio, dev) < 0) return -1; - zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num); + zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); /* bank 0 pins 7 and 8 are special and cannot be used as inputs */ if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8)) return -1; /* clear the bit in direction mode reg to set the pin as input */ - reg = readl(ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); + reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); reg &= ~BIT(bank_pin_num); - writel(reg, ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); + writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); return 0; } -/** - * gpio_direction_output - Set the direction of the specified GPIO pin as output - * @gpio: gpio pin number within the device - * @value: value to be written to specified pin - * - * This function sets the direction of specified GPIO pin as output, configures - * the Output Enable register for the pin and uses zynq_gpio_set to set - * the value of the pin to the value specified. - * - * Return: 0 always - */ -int gpio_direction_output(unsigned gpio, int value) +static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio, + int value) { u32 reg; unsigned int bank_num, bank_pin_num; + struct zynq_gpio_privdata *priv = dev_get_priv(dev); - if (check_gpio(gpio) < 0) + if (check_gpio(gpio, dev) < 0) return -1; - zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num); + zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); /* set the GPIO pin as output */ - reg = readl(ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); + reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); reg |= BIT(bank_pin_num); - writel(reg, ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); + writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); /* configure the output enable reg for the pin */ - reg = readl(ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); + reg = readl(priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); reg |= BIT(bank_pin_num); - writel(reg, ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); + writel(reg, priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); /* set the state of the pin */ gpio_set_value(gpio, value); return 0; } -/** - * Request a gpio before using it. - * - * NOTE: Argument 'label' is unused. - */ -int gpio_request(unsigned gpio, const char *label) +static const struct dm_gpio_ops gpio_zynq_ops = { + .direction_input = zynq_gpio_direction_input, + .direction_output = zynq_gpio_direction_output, + .get_value = zynq_gpio_get_value, + .set_value = zynq_gpio_set_value, +}; + +static const struct udevice_id zynq_gpio_ids[] = { + { .compatible = "xlnx,zynq-gpio-1.0", + .data = (ulong)&zynq_gpio_def}, + { .compatible = "xlnx,zynqmp-gpio-1.0", + .data = (ulong)&zynqmp_gpio_def}, + { } +}; + +static void zynq_gpio_getplat_data(struct udevice *dev) { - if (check_gpio(gpio) < 0) - return -1; + const struct udevice_id *of_match = zynq_gpio_ids; + int ret; + struct zynq_gpio_privdata *priv = dev_get_priv(dev); + + while (of_match->compatible) { + ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, + of_match->compatible); + if (ret >= 0) { + priv->p_data = + (struct zynq_platform_data *)of_match->data; + break; + } else { + of_match++; + continue; + } + } + + if (!priv->p_data) + printf("No Platform data found\n"); +} + +static int zynq_gpio_probe(struct udevice *dev) +{ + struct zynq_gpio_privdata *priv = dev_get_priv(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + zynq_gpio_getplat_data(dev); + + if (priv->p_data) + uc_priv->gpio_count = priv->p_data->ngpio; return 0; } -/** - * Reset and free the gpio after using it. - */ -int gpio_free(unsigned gpio) +static int zynq_gpio_ofdata_to_platdata(struct udevice *dev) { + struct zynq_gpio_privdata *priv = dev_get_priv(dev); + + priv->base = dev_get_addr(dev); + return 0; } + +U_BOOT_DRIVER(gpio_zynq) = { + .name = "gpio_zynq", + .id = UCLASS_GPIO, + .ops = &gpio_zynq_ops, + .of_match = zynq_gpio_ids, + .ofdata_to_platdata = zynq_gpio_ofdata_to_platdata, + .probe = zynq_gpio_probe, + .priv_auto_alloc_size = sizeof(struct zynq_gpio_privdata), +}; diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 46b83e7..9324c6c 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -58,6 +58,13 @@ config DM_I2C_GPIO bindings are supported. Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt +config SYS_I2C_CADENCE + tristate "Cadence I2C Controller" + depends on DM_I2C && (ARCH_ZYNQ || ARM64) + help + Say yes here to select Cadence I2C Host Controller. This controller is + e.g. used by Xilinx Zynq. + config SYS_I2C_INTEL bool "Intel I2C/SMBUS driver" depends on DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index c75c579..167424d 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SYS_I2C) += i2c_core.o +obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c new file mode 100644 index 0000000..909cea2 --- /dev/null +++ b/drivers/i2c/i2c-cdns.c @@ -0,0 +1,335 @@ +/* + * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com> + * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2) + * + * This file is based on: drivers/i2c/zynq_i2c.c, + * with added driver-model support and code cleanup. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/types.h> +#include <linux/io.h> +#include <asm/errno.h> +#include <dm/device.h> +#include <dm/root.h> +#include <i2c.h> +#include <fdtdec.h> +#include <mapmem.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* i2c register set */ +struct cdns_i2c_regs { + u32 control; + u32 status; + u32 address; + u32 data; + u32 interrupt_status; + u32 transfer_size; + u32 slave_mon_pause; + u32 time_out; + u32 interrupt_mask; + u32 interrupt_enable; + u32 interrupt_disable; +}; + +/* Control register fields */ +#define CDNS_I2C_CONTROL_RW 0x00000001 +#define CDNS_I2C_CONTROL_MS 0x00000002 +#define CDNS_I2C_CONTROL_NEA 0x00000004 +#define CDNS_I2C_CONTROL_ACKEN 0x00000008 +#define CDNS_I2C_CONTROL_HOLD 0x00000010 +#define CDNS_I2C_CONTROL_SLVMON 0x00000020 +#define CDNS_I2C_CONTROL_CLR_FIFO 0x00000040 +#define CDNS_I2C_CONTROL_DIV_B_SHIFT 8 +#define CDNS_I2C_CONTROL_DIV_B_MASK 0x00003F00 +#define CDNS_I2C_CONTROL_DIV_A_SHIFT 14 +#define CDNS_I2C_CONTROL_DIV_A_MASK 0x0000C000 + +/* Status register values */ +#define CDNS_I2C_STATUS_RXDV 0x00000020 +#define CDNS_I2C_STATUS_TXDV 0x00000040 +#define CDNS_I2C_STATUS_RXOVF 0x00000080 +#define CDNS_I2C_STATUS_BA 0x00000100 + +/* Interrupt register fields */ +#define CDNS_I2C_INTERRUPT_COMP 0x00000001 +#define CDNS_I2C_INTERRUPT_DATA 0x00000002 +#define CDNS_I2C_INTERRUPT_NACK 0x00000004 +#define CDNS_I2C_INTERRUPT_TO 0x00000008 +#define CDNS_I2C_INTERRUPT_SLVRDY 0x00000010 +#define CDNS_I2C_INTERRUPT_RXOVF 0x00000020 +#define CDNS_I2C_INTERRUPT_TXOVF 0x00000040 +#define CDNS_I2C_INTERRUPT_RXUNF 0x00000080 +#define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200 + +#define CDNS_I2C_FIFO_DEPTH 16 +#define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */ + +#ifdef DEBUG +static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c) +{ + int int_status; + int status; + int_status = readl(&cdns_i2c->interrupt_status); + + status = readl(&cdns_i2c->status); + if (int_status || status) { + debug("Status: "); + if (int_status & CDNS_I2C_INTERRUPT_COMP) + debug("COMP "); + if (int_status & CDNS_I2C_INTERRUPT_DATA) + debug("DATA "); + if (int_status & CDNS_I2C_INTERRUPT_NACK) + debug("NACK "); + if (int_status & CDNS_I2C_INTERRUPT_TO) + debug("TO "); + if (int_status & CDNS_I2C_INTERRUPT_SLVRDY) + debug("SLVRDY "); + if (int_status & CDNS_I2C_INTERRUPT_RXOVF) + debug("RXOVF "); + if (int_status & CDNS_I2C_INTERRUPT_TXOVF) + debug("TXOVF "); + if (int_status & CDNS_I2C_INTERRUPT_RXUNF) + debug("RXUNF "); + if (int_status & CDNS_I2C_INTERRUPT_ARBLOST) + debug("ARBLOST "); + if (status & CDNS_I2C_STATUS_RXDV) + debug("RXDV "); + if (status & CDNS_I2C_STATUS_TXDV) + debug("TXDV "); + if (status & CDNS_I2C_STATUS_RXOVF) + debug("RXOVF "); + if (status & CDNS_I2C_STATUS_BA) + debug("BA "); + debug("TS%d ", readl(&cdns_i2c->transfer_size)); + debug("\n"); + } +} +#endif + +struct i2c_cdns_bus { + int id; + struct cdns_i2c_regs __iomem *regs; /* register base */ +}; + + +/** cdns_i2c_probe() - Probe method + * @dev: udevice pointer + * + * DM callback called when device is probed + */ +static int cdns_i2c_probe(struct udevice *dev) +{ + struct i2c_cdns_bus *bus = dev_get_priv(dev); + + bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev); + if (!bus->regs) + return -ENOMEM; + + /* TODO: Calculate dividers based on CPU_CLK_1X */ + /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */ + writel((16 << CDNS_I2C_CONTROL_DIV_B_SHIFT) | + (2 << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control); + + /* Enable master mode, ack, and 7-bit addressing */ + setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS | + CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA); + + debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs); + + return 0; +} + +static int cdns_i2c_remove(struct udevice *dev) +{ + struct i2c_cdns_bus *bus = dev_get_priv(dev); + + debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs); + + unmap_sysmem(bus->regs); + + return 0; +} + +/* Wait for an interrupt */ +static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask) +{ + int timeout, int_status; + + for (timeout = 0; timeout < 100; timeout++) { + udelay(100); + int_status = readl(&cdns_i2c->interrupt_status); + if (int_status & mask) + break; + } + + /* Clear interrupt status flags */ + writel(int_status & mask, &cdns_i2c->interrupt_status); + + return int_status & mask; +} + +static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) +{ + if (speed != 100000) { + printf("%s, failed to set clock speed to %u\n", __func__, + speed); + return -EINVAL; + } + + return 0; +} + +/* Probe to see if a chip is present. */ +static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr, + uint chip_flags) +{ + struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus); + struct cdns_i2c_regs *regs = i2c_bus->regs; + + /* Attempt to read a byte */ + setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO | + CDNS_I2C_CONTROL_RW); + clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); + writel(0xFF, ®s->interrupt_status); + writel(chip_addr, ®s->address); + writel(1, ®s->transfer_size); + + return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP | + CDNS_I2C_INTERRUPT_NACK) & + CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT; +} + +static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, + u32 len, bool next_is_read) +{ + u8 *cur_data = data; + + struct cdns_i2c_regs *regs = i2c_bus->regs; + + setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO | + CDNS_I2C_CONTROL_HOLD); + + /* if next is a read, we need to clear HOLD, doesn't work */ + if (next_is_read) + clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); + + clrbits_le32(®s->control, CDNS_I2C_CONTROL_RW); + + writel(0xFF, ®s->interrupt_status); + writel(addr, ®s->address); + + while (len--) { + writel(*(cur_data++), ®s->data); + if (readl(®s->transfer_size) == CDNS_I2C_FIFO_DEPTH) { + if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) { + /* Release the bus */ + clrbits_le32(®s->control, + CDNS_I2C_CONTROL_HOLD); + return -ETIMEDOUT; + } + } + } + + /* All done... release the bus */ + clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); + /* Wait for the address and data to be sent */ + if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) + return -ETIMEDOUT; + return 0; +} + +static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, + u32 len) +{ + u32 status; + u32 i = 0; + u8 *cur_data = data; + + /* TODO: Fix this */ + struct cdns_i2c_regs *regs = i2c_bus->regs; + + /* Check the hardware can handle the requested bytes */ + if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX)) + return -EINVAL; + + setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO | + CDNS_I2C_CONTROL_RW); + + /* Start reading data */ + writel(addr, ®s->address); + writel(len, ®s->transfer_size); + + /* Wait for data */ + do { + status = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP | + CDNS_I2C_INTERRUPT_DATA); + if (!status) { + /* Release the bus */ + clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); + return -ETIMEDOUT; + } + debug("Read %d bytes\n", + len - readl(®s->transfer_size)); + for (; i < len - readl(®s->transfer_size); i++) + *(cur_data++) = readl(®s->data); + } while (readl(®s->transfer_size) != 0); + /* All done... release the bus */ + clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); + +#ifdef DEBUG + cdns_i2c_debug_status(regs); +#endif + return 0; +} + +static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, + int nmsgs) +{ + struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev); + int ret; + + debug("i2c_xfer: %d messages\n", nmsgs); + for (; nmsgs > 0; nmsgs--, msg++) { + bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD); + + debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); + if (msg->flags & I2C_M_RD) { + ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf, + msg->len); + } else { + ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf, + msg->len, next_is_read); + } + if (ret) { + debug("i2c_write: error sending\n"); + return -EREMOTEIO; + } + } + + return 0; +} + +static const struct dm_i2c_ops cdns_i2c_ops = { + .xfer = cdns_i2c_xfer, + .probe_chip = cdns_i2c_probe_chip, + .set_bus_speed = cdns_i2c_set_bus_speed, +}; + +static const struct udevice_id cdns_i2c_of_match[] = { + { .compatible = "cdns,i2c-r1p10" }, + { /* end of table */ } +}; + +U_BOOT_DRIVER(cdns_i2c) = { + .name = "i2c-cdns", + .id = UCLASS_I2C, + .of_match = cdns_i2c_of_match, + .probe = cdns_i2c_probe, + .remove = cdns_i2c_remove, + .priv_auto_alloc_size = sizeof(struct i2c_cdns_bus), + .ops = &cdns_i2c_ops, +}; |