diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/bios_emulator/biosemu.c | 4 | ||||
| -rw-r--r-- | drivers/bios_emulator/include/x86emu.h | 10 | ||||
| -rw-r--r-- | drivers/bios_emulator/x86emu/ops.c | 14 | ||||
| -rw-r--r-- | drivers/bios_emulator/x86emu/ops2.c | 2 | ||||
| -rw-r--r-- | drivers/dma/MCD_tasks.c | 6 | ||||
| -rw-r--r-- | drivers/misc/fsl_law.c | 19 | ||||
| -rw-r--r-- | drivers/mtd/dataflash.c | 38 | ||||
| -rw-r--r-- | drivers/mtd/jedec_flash.c | 4 | ||||
| -rw-r--r-- | drivers/net/cs8900.c | 4 | ||||
| -rw-r--r-- | drivers/net/lan91c96.c | 20 | ||||
| -rw-r--r-- | drivers/net/macb.c | 8 | ||||
| -rw-r--r-- | drivers/net/macb.h | 6 | ||||
| -rw-r--r-- | drivers/net/netarm_eth.c | 4 | ||||
| -rw-r--r-- | drivers/net/rtl8019.c | 7 | ||||
| -rw-r--r-- | drivers/net/rtl8169.c | 2 | ||||
| -rw-r--r-- | drivers/qe/Makefile | 3 | ||||
| -rw-r--r-- | drivers/qe/fdt.c | 90 | ||||
| -rw-r--r-- | drivers/qe/qe.h | 1 | ||||
| -rw-r--r-- | drivers/rtc/Makefile | 2 | ||||
| -rw-r--r-- | drivers/rtc/bf5xx_rtc.c | 143 | ||||
| -rw-r--r-- | drivers/rtc/bfin_rtc.c | 117 | ||||
| -rw-r--r-- | drivers/rtc/rx8025.c | 5 | ||||
| -rw-r--r-- | drivers/spi/mpc8xxx_spi.c | 4 | ||||
| -rw-r--r-- | drivers/video/ati_radeon_fb.c | 322 |
24 files changed, 616 insertions, 219 deletions
diff --git a/drivers/bios_emulator/biosemu.c b/drivers/bios_emulator/biosemu.c index 75ceb45..decdb79 100644 --- a/drivers/bios_emulator/biosemu.c +++ b/drivers/bios_emulator/biosemu.c @@ -53,7 +53,7 @@ #include "biosemui.h" BE_sysEnv _BE_env = {{0}}; -static X86EMU_memFuncs _BE_mem __attribute__((section(".got2"))) = { +static X86EMU_memFuncs _BE_mem __attribute__((section(GOT2_TYPE))) = { BE_rdb, BE_rdw, BE_rdl, @@ -62,7 +62,7 @@ static X86EMU_memFuncs _BE_mem __attribute__((section(".got2"))) = { BE_wrl, }; -static X86EMU_pioFuncs _BE_pio __attribute__((section(".got2"))) = { +static X86EMU_pioFuncs _BE_pio __attribute__((section(GOT2_TYPE))) = { BE_inb, BE_inw, BE_inl, diff --git a/drivers/bios_emulator/include/x86emu.h b/drivers/bios_emulator/include/x86emu.h index 6004beb..a70a768 100644 --- a/drivers/bios_emulator/include/x86emu.h +++ b/drivers/bios_emulator/include/x86emu.h @@ -53,6 +53,16 @@ typedef u16 X86EMU_pioAddr; /*---------------------- Macros and type definitions ----------------------*/ +#if defined (CONFIG_ARM) +#define GAS_LINE_COMMENT "@" +#elif defined(CONFIG_MIPS) || defined(CONFIG_PPC) +#define GAS_LINE_COMMENT "#" +#elif defined (CONFIG_SH) +#define GAS_LINE_COMMENT "!" +#endif + +#define GOT2_TYPE ".got2,\"aw\"\t"GAS_LINE_COMMENT + #pragma pack(1) /**************************************************************************** diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c index a77bd9b..10f2757 100644 --- a/drivers/bios_emulator/x86emu/ops.c +++ b/drivers/bios_emulator/x86emu/ops.c @@ -91,7 +91,7 @@ static char *x86emu_GenOpName[8] = { #endif /* used by several opcodes */ -static u8 (*genop_byte_operation[])(u8 d, u8 s) __attribute__ ((section(".got2"))) = +static u8 (*genop_byte_operation[])(u8 d, u8 s) __attribute__ ((section(GOT2_TYPE))) = { add_byte, /* 00 */ or_byte, /* 01 */ @@ -103,7 +103,7 @@ static u8 (*genop_byte_operation[])(u8 d, u8 s) __attribute__ ((section(".got2") cmp_byte, /* 07 */ }; -static u16 (*genop_word_operation[])(u16 d, u16 s) __attribute__ ((section(".got2"))) = +static u16 (*genop_word_operation[])(u16 d, u16 s) __attribute__ ((section(GOT2_TYPE))) = { add_word, /*00 */ or_word, /*01 */ @@ -115,7 +115,7 @@ static u16 (*genop_word_operation[])(u16 d, u16 s) __attribute__ ((section(".got cmp_word, /*07 */ }; -static u32 (*genop_long_operation[])(u32 d, u32 s) __attribute__ ((section(".got2"))) = +static u32 (*genop_long_operation[])(u32 d, u32 s) __attribute__ ((section(GOT2_TYPE))) = { add_long, /*00 */ or_long, /*01 */ @@ -128,7 +128,7 @@ static u32 (*genop_long_operation[])(u32 d, u32 s) __attribute__ ((section(".got }; /* used by opcodes 80, c0, d0, and d2. */ -static u8(*opcD0_byte_operation[])(u8 d, u8 s) __attribute__ ((section(".got2"))) = +static u8(*opcD0_byte_operation[])(u8 d, u8 s) __attribute__ ((section(GOT2_TYPE))) = { rol_byte, ror_byte, @@ -141,7 +141,7 @@ static u8(*opcD0_byte_operation[])(u8 d, u8 s) __attribute__ ((section(".got2")) }; /* used by opcodes c1, d1, and d3. */ -static u16(*opcD1_word_operation[])(u16 s, u8 d) __attribute__ ((section(".got2"))) = +static u16(*opcD1_word_operation[])(u16 s, u8 d) __attribute__ ((section(GOT2_TYPE))) = { rol_word, ror_word, @@ -154,7 +154,7 @@ static u16(*opcD1_word_operation[])(u16 s, u8 d) __attribute__ ((section(".got2" }; /* used by opcodes c1, d1, and d3. */ -static u32 (*opcD1_long_operation[])(u32 s, u8 d) __attribute__ ((section(".got2"))) = +static u32 (*opcD1_long_operation[])(u32 s, u8 d) __attribute__ ((section(GOT2_TYPE))) = { rol_long, ror_long, @@ -5147,7 +5147,7 @@ void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) /*************************************************************************** * Single byte operation code table: **************************************************************************/ -void (*x86emu_optab[256])(u8) __attribute__ ((section(".got2"))) = +void (*x86emu_optab[256])(u8) __attribute__ ((section(GOT2_TYPE))) = { /* 0x00 */ x86emuOp_genop_byte_RM_R, /* 0x01 */ x86emuOp_genop_word_RM_R, diff --git a/drivers/bios_emulator/x86emu/ops2.c b/drivers/bios_emulator/x86emu/ops2.c index d6a210c..d90d366 100644 --- a/drivers/bios_emulator/x86emu/ops2.c +++ b/drivers/bios_emulator/x86emu/ops2.c @@ -1498,7 +1498,7 @@ void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2)) /*************************************************************************** * Double byte operation code table: **************************************************************************/ -void (*x86emu_optab2[256])(u8) __attribute__((section(".got2"))) = +void (*x86emu_optab2[256])(u8) __attribute__((section(GOT2_TYPE))) = { /* 0x00 */ x86emuOp2_illegal_op, /* Group F (ring 0 PM) */ /* 0x01 */ x86emuOp2_illegal_op, /* Group G (ring 0 PM) */ diff --git a/drivers/dma/MCD_tasks.c b/drivers/dma/MCD_tasks.c index 694e780..06a2d53 100644 --- a/drivers/dma/MCD_tasks.c +++ b/drivers/dma/MCD_tasks.c @@ -22,6 +22,10 @@ /* Contains task code and structures for Multi-channel DMA */ +#include <common.h> + +#ifdef CONFIG_FSLDMAFEC + #include <MCD_dma.h> u32 MCD_varTab0[]; @@ -2426,3 +2430,5 @@ u32 MCD_ENetXmit_TDT[] = { #ifdef MCD_INCLUDE_EU MCD_bufDesc MCD_singleBufDescs[NCHANNELS]; #endif + +#endif /* CONFIG_FSLDMAFEC */ diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 8bdf5a7..dca6a4d 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -28,6 +28,7 @@ #include <asm/io.h> #define LAWAR_EN 0x80000000 +#define FSL_HW_NUM_LAWS 10 /* number of LAWs in the hw implementation */ void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { @@ -53,6 +54,24 @@ void disable_law(u8 idx) return; } +void print_laws(void) +{ + volatile u32 *base = (volatile u32 *)(CFG_IMMR + 0xc08); + volatile u32 *lawbar = base; + volatile u32 *lawar = base + 2; + int i; + + printf("\nLocal Access Window Configuration\n"); + for(i = 0; i < FSL_HW_NUM_LAWS; i++) { + printf("\tLAWBAR%d : 0x%08x, LAWAR%d : 0x%08x\n", + i, in_be32(lawbar), i, in_be32(lawar)); + lawbar += 8; + lawar += 8; + } + + return; +} + void init_laws(void) { int i; diff --git a/drivers/mtd/dataflash.c b/drivers/mtd/dataflash.c index 91903c8..36c99a0 100644 --- a/drivers/mtd/dataflash.c +++ b/drivers/mtd/dataflash.c @@ -26,24 +26,30 @@ AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; static AT91S_DataFlash DataFlashInst; +struct dataflash_addr { + unsigned long addr; + int cs; +}; + #ifdef CONFIG_AT91SAM9260EK -int cs[][CFG_MAX_DATAFLASH_BANKS] = { +struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = { {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ {CFG_DATAFLASH_LOGIC_ADDR_CS1, 1} }; -#elif defined(CONFIG_AT91SAM9263EK) -int cs[][CFG_MAX_DATAFLASH_BANKS] = { - {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0} /* Logical adress, CS */ +#elif defined(CONFIG_AT91SAM9263EK) || defined(CONFIG_AT91CAP9ADK) +struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = { + {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ }; #else -int cs[][CFG_MAX_DATAFLASH_BANKS] = { +struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = { {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ {CFG_DATAFLASH_LOGIC_ADDR_CS3, 3} }; #endif /*define the area offsets*/ -#if defined(CONFIG_AT91SAM9261EK) || defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AT91SAM9263EK) +#if defined(CONFIG_AT91SAM9261EK) || defined(CONFIG_AT91SAM9260EK) || \ + defined(CONFIG_AT91SAM9263EK) || defined(CONFIG_AT91CAP9ADK) #if defined(CONFIG_NEW_PARTITION) dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { {0x00000000, 0x00003FFF, FLAG_PROTECT_SET, 0, "Bootstrap"}, /* ROM code */ @@ -114,7 +120,7 @@ int AT91F_DataflashInit (void) dataflash_info[i].Desc.state = IDLE; dataflash_info[i].id = 0; dataflash_info[i].Device.pages_number = 0; - dfcode = AT91F_DataflashProbe (cs[i][1], + dfcode = AT91F_DataflashProbe (cs[i].cs, &dataflash_info[i].Desc); switch (dfcode) { @@ -123,9 +129,9 @@ int AT91F_DataflashInit (void) dataflash_info[i].Device.pages_size = 528; dataflash_info[i].Device.page_offset = 10; dataflash_info[i].Device.byte_mask = 0x300; - dataflash_info[i].Device.cs = cs[i][1]; + dataflash_info[i].Device.cs = cs[i].cs; dataflash_info[i].Desc.DataFlash_state = IDLE; - dataflash_info[i].logical_address = cs[i][0]; + dataflash_info[i].logical_address = cs[i].addr; dataflash_info[i].id = dfcode; found[i] += dfcode;; break; @@ -135,9 +141,9 @@ int AT91F_DataflashInit (void) dataflash_info[i].Device.pages_size = 528; dataflash_info[i].Device.page_offset = 10; dataflash_info[i].Device.byte_mask = 0x300; - dataflash_info[i].Device.cs = cs[i][1]; + dataflash_info[i].Device.cs = cs[i].cs; dataflash_info[i].Desc.DataFlash_state = IDLE; - dataflash_info[i].logical_address = cs[i][0]; + dataflash_info[i].logical_address = cs[i].addr; dataflash_info[i].id = dfcode; found[i] += dfcode;; break; @@ -147,9 +153,9 @@ int AT91F_DataflashInit (void) dataflash_info[i].Device.pages_size = 1056; dataflash_info[i].Device.page_offset = 11; dataflash_info[i].Device.byte_mask = 0x700; - dataflash_info[i].Device.cs = cs[i][1]; + dataflash_info[i].Device.cs = cs[i].cs; dataflash_info[i].Desc.DataFlash_state = IDLE; - dataflash_info[i].logical_address = cs[i][0]; + dataflash_info[i].logical_address = cs[i].addr; dataflash_info[i].id = dfcode; found[i] += dfcode;; break; @@ -159,9 +165,9 @@ int AT91F_DataflashInit (void) dataflash_info[i].Device.pages_size = 1056; dataflash_info[i].Device.page_offset = 11; dataflash_info[i].Device.byte_mask = 0x700; - dataflash_info[i].Device.cs = cs[i][1]; + dataflash_info[i].Device.cs = cs[i].cs; dataflash_info[i].Desc.DataFlash_state = IDLE; - dataflash_info[i].logical_address = cs[i][0]; + dataflash_info[i].logical_address = cs[i].addr; dataflash_info[i].id = dfcode; found[i] += dfcode;; break; @@ -304,7 +310,7 @@ AT91PS_DataFlash AT91F_DataflashSelect (AT91PS_DataFlash pFlash, for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) if ( dataflash_info[i].id - && ((((int) addr) & 0xFF000000) == + && ((((int) *addr) & 0xFF000000) == dataflash_info[i].logical_address)) { addr_valid = 1; break; diff --git a/drivers/mtd/jedec_flash.c b/drivers/mtd/jedec_flash.c index 94e87cb..41aad3b 100644 --- a/drivers/mtd/jedec_flash.c +++ b/drivers/mtd/jedec_flash.c @@ -218,10 +218,6 @@ static const struct amd_flash_info jedec_table[] = { #endif }; - -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - - static inline void fill_info(flash_info_t *info, const struct amd_flash_info *jedec_entry, ulong base) { int i,j; diff --git a/drivers/net/cs8900.c b/drivers/net/cs8900.c index 80c4ba2..55ef346 100644 --- a/drivers/net/cs8900.c +++ b/drivers/net/cs8900.c @@ -165,7 +165,7 @@ void cs8900_get_enetaddr (uchar * addr) addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]) ; - debug ("### Set environment from HW MAC addr = \"%s\"\n", ethaddr); + debug ("### Set environment from HW MAC addr = \"%s\"\n", ethaddr); setenv ("ethaddr", ethaddr); } @@ -317,6 +317,6 @@ int cs8900_e2prom_write(unsigned char addr, unsigned short value) return 0; } -#endif /* COMMANDS & CFG_NET */ +#endif /* CONFIG_CMD_NET */ #endif /* CONFIG_DRIVER_CS8900 */ diff --git a/drivers/net/lan91c96.c b/drivers/net/lan91c96.c index ecdcbd9..51cfb7e 100644 --- a/drivers/net/lan91c96.c +++ b/drivers/net/lan91c96.c @@ -36,12 +36,12 @@ * AUI/TP selection ( mine has 10Base2/10BaseT select ) * * Arguments: - * io = for the base address + * io = for the base address * irq = for the IRQ * * author: - * Erik Stahlman ( erik@vt.edu ) - * Daris A Nevil ( dnevil@snmc.com ) + * Erik Stahlman ( erik@vt.edu ) + * Daris A Nevil ( dnevil@snmc.com ) * * * Hardware multicast code from Peter Cammaert ( pc@denkart.be ) @@ -53,7 +53,7 @@ * o lan91c96.c (Intel Diagnostic Manager driver) * * History: - * 04/30/03 Mathijs Haarman Modified smc91111.c (u-boot version) + * 04/30/03 Mathijs Haarman Modified smc91111.c (u-boot version) * for lan91c96 *--------------------------------------------------------------------------- */ @@ -296,8 +296,8 @@ static int poll4int (byte mask, int timeout) /* * Function: smc_reset( void ) * Purpose: - * This sets the SMC91111 chip to its normal state, hopefully from whatever - * mess that any other DOS driver has put it in. + * This sets the SMC91111 chip to its normal state, hopefully from whatever + * mess that any other DOS driver has put it in. * * Maybe I should reset more registers to defaults in here? SOFTRST should * do that for me. @@ -397,7 +397,7 @@ static void smc_shutdown () * This sends the actual packet to the SMC9xxx chip. * * Algorithm: - * First, see if a saved_skb is available. + * First, see if a saved_skb is available. * ( this should NOT be called if there is no 'saved_skb' * Now, find the packet number that the chip allocated * Point the data pointers at it in memory @@ -405,9 +405,9 @@ static void smc_shutdown () * Dump the packet to chip memory * Check if a last byte is needed ( odd length packet ) * if so, set the control flag right - * Tell the card to send it + * Tell the card to send it * Enable the transmit interrupt, so I know if it failed - * Free the kernel data if I actually sent it. + * Free the kernel data if I actually sent it. */ static int smc_send_packet (volatile void *packet, int packet_length) { @@ -865,7 +865,7 @@ static int smc_hw_init () } #endif /* 0 */ -#endif /* COMMANDS & CFG_NET */ +#endif /* CONFIG_CMD_NET */ /* smc_get_ethaddr (bd_t * bd) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 6657d22..9c98338 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -417,10 +417,18 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) /* choose RMII or MII mode. This depends on the board */ #ifdef CONFIG_RMII +#ifdef CONFIG_AT91CAP9ADK + macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); +#else macb_writel(macb, USRIO, 0); +#endif +#else +#ifdef CONFIG_AT91CAP9ADK + macb_writel(macb, USRIO, MACB_BIT(CLKEN)); #else macb_writel(macb, USRIO, MACB_BIT(MII)); #endif +#endif /* CONFIG_RMII */ if (!macb_phy_init(macb)) return -1; diff --git a/drivers/net/macb.h b/drivers/net/macb.h index c778e4e..f92a20c 100644 --- a/drivers/net/macb.h +++ b/drivers/net/macb.h @@ -222,6 +222,12 @@ #define MACB_TX_PAUSE_ZERO_OFFSET 3 #define MACB_TX_PAUSE_ZERO_SIZE 1 +/* Bitfields in USRIO (AT91) */ +#define MACB_RMII_OFFSET 0 +#define MACB_RMII_SIZE 1 +#define MACB_CLKEN_OFFSET 1 +#define MACB_CLKEN_SIZE 1 + /* Bitfields in WOL */ #define MACB_IP_OFFSET 0 #define MACB_IP_SIZE 16 diff --git a/drivers/net/netarm_eth.c b/drivers/net/netarm_eth.c index a99ee5d..ecf45dc 100644 --- a/drivers/net/netarm_eth.c +++ b/drivers/net/netarm_eth.c @@ -29,7 +29,6 @@ #include "netarm_eth.h" #include <asm/arch/netarm_registers.h> - #if defined(CONFIG_CMD_NET) static int na_mii_poll_busy (void); @@ -56,7 +55,6 @@ static void na_get_mac_addr (void) setenv ("ethaddr", ethaddr); } - static void na_mii_write (int reg, int value) { int mii_addr; @@ -355,6 +353,6 @@ extern int eth_send (volatile void *packet, int length) return 1; } -#endif /* COMMANDS & CFG_NET */ +#endif /* CONFIG_CMD_NET */ #endif /* CONFIG_DRIVER_NETARMETH */ diff --git a/drivers/net/rtl8019.c b/drivers/net/rtl8019.c index 409a69f..9d62cab 100644 --- a/drivers/net/rtl8019.c +++ b/drivers/net/rtl8019.c @@ -36,16 +36,13 @@ #if defined(CONFIG_CMD_NET) - /* packet page register access functions */ - static unsigned char get_reg (unsigned int regno) { return (*(unsigned char *) regno); } - static void put_reg (unsigned int regno, unsigned char val) { *(volatile unsigned char *) regno = val; @@ -91,7 +88,6 @@ void rtl8019_get_enetaddr (uchar * addr) put_reg (RTL8019_COMMAND, RTL8019_PAGE0); } - void eth_halt (void) { put_reg (RTL8019_COMMAND, 0x01); @@ -134,7 +130,6 @@ int eth_init (bd_t * bd) return 0; } - static unsigned char nic_to_pc (void) { unsigned char rec_head_status; @@ -277,6 +272,6 @@ extern int eth_send (volatile void *packet, int length) return 0; } -#endif /* COMMANDS & CFG_NET */ +#endif /* CONFIG_CMD_NET */ #endif /* CONFIG_DRIVER_RTL8019 */ diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 57ccbd9..d71323f 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -352,8 +352,6 @@ int mdio_read(int RegAddr) return value; } -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - static int rtl8169_init_board(struct eth_device *dev) { int i; diff --git a/drivers/qe/Makefile b/drivers/qe/Makefile index 4844181..ec5aa73 100644 --- a/drivers/qe/Makefile +++ b/drivers/qe/Makefile @@ -24,7 +24,8 @@ include $(TOPDIR)/config.mk LIB := $(obj)qe.a -COBJS := qe.o uccf.o uec.o uec_phy.o +COBJS-$(CONFIG_OF_LIBFDT) += fdt.o +COBJS := qe.o uccf.o uec.o uec_phy.o $(COBJS-y) SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/qe/fdt.c b/drivers/qe/fdt.c new file mode 100644 index 0000000..5307488 --- /dev/null +++ b/drivers/qe/fdt.c @@ -0,0 +1,90 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <libfdt.h> +#include <fdt_support.h> +#include "qe.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * If a QE firmware has been uploaded, then add the 'firmware' node under + * the 'qe' node. + */ +void fdt_fixup_qe_firmware(void *blob) +{ + struct qe_firmware_info *qe_fw_info; + int node, ret; + + qe_fw_info = qe_get_firmware_info(); + if (!qe_fw_info) + return; + + node = fdt_path_offset(blob, "/qe"); + if (node < 0) + return; + + /* We assume the node doesn't exist yet */ + node = fdt_add_subnode(blob, node, "firmware"); + if (node < 0) + return; + + ret = fdt_setprop(blob, node, "extended-modes", + &qe_fw_info->extended_modes, sizeof(u64)); + if (ret < 0) + goto error; + + ret = fdt_setprop_string(blob, node, "id", qe_fw_info->id); + if (ret < 0) + goto error; + + ret = fdt_setprop(blob, node, "virtual-traps", qe_fw_info->vtraps, + sizeof(qe_fw_info->vtraps)); + if (ret < 0) + goto error; + + return; + +error: + fdt_del_node(blob, node); +} + +void ft_qe_setup(void *blob) +{ +#ifdef CONFIG_QE + do_fixup_by_prop_u32(blob, "device_type", "qe", 4, + "bus-frequency", gd->qe_clk, 1); + do_fixup_by_prop_u32(blob, "device_type", "qe", 4, + "brg-frequency", gd->brg_clk, 1); + do_fixup_by_compat_u32(blob, "fsl,qe", + "clock-frequency", gd->qe_clk, 1); + do_fixup_by_compat_u32(blob, "fsl,qe", + "bus-frequency", gd->qe_clk, 1); + do_fixup_by_compat_u32(blob, "fsl,qe", + "brg-frequency", gd->brg_clk, 1); + fdt_fixup_qe_firmware(blob); +#endif +} diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h index 4c96c67..741ed7f 100644 --- a/drivers/qe/qe.h +++ b/drivers/qe/qe.h @@ -289,5 +289,6 @@ int qe_set_brg(uint brg, uint rate); int qe_set_mii_clk_src(int ucc_num); int qe_upload_firmware(const struct qe_firmware *firmware); struct qe_firmware_info *qe_get_firmware_info(void); +void ft_qe_setup(void *blob); #endif /* __QE_H__ */ diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 8c7f148..2af2bf4 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)librtc.a COBJS-y += date.o -COBJS-y += bf5xx_rtc.o +COBJS-y += bfin_rtc.o COBJS-y += ds12887.o COBJS-y += ds1302.o COBJS-y += ds1306.o diff --git a/drivers/rtc/bf5xx_rtc.c b/drivers/rtc/bf5xx_rtc.c deleted file mode 100644 index 8856bb9..0000000 --- a/drivers/rtc/bf5xx_rtc.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * Real Time Clock interface of ADI21535 (Blackfin) for uCLinux - * - * Copyright (C) 2003 Motorola Corporation. All rights reserved. - * Richard Xiao (A2590C@email.mot.com) - * - * Copyright (C) 1996 Paul Gortmaker - * - * - * Based on other minimal char device drivers, like Alan's - * watchdog, Ted's random, etc. etc. - * - * 1.07 Paul Gortmaker. - * 1.08 Miquel van Smoorenburg: disallow certain things on the - * DEC Alpha as the CMOS clock is also used for other things. - * 1.09 Nikita Schmidt: epoch support and some Alpha cleanup. - * 1.09a Pete Zaitcev: Sun SPARC - * 1.09b Jeff Garzik: Modularize, init cleanup - * 1.09c Jeff Garzik: SMP cleanup - * 1.10 Paul Barton-Davis: add support for async I/O - * 1.10a Andrea Arcangeli: Alpha updates - * 1.10b Andrew Morton: SMP lock fix - * 1.10c Cesar Barros: SMP locking fixes and cleanup - * 1.10d Paul Gortmaker: delete paranoia check in rtc_exit - * 1.10e LG Soft India: Register access is different in BF533. - */ - -#include <common.h> -#include <command.h> -#include <rtc.h> - -#if defined(CONFIG_RTC_BFIN) && defined(CONFIG_CMD_DATE) - -#include <asm/blackfin.h> -#include <asm/arch/bf5xx_rtc.h> - -void rtc_reset(void) -{ - return; /* nothing to do */ -} - -/* Wait for pending writes to complete */ -void wait_for_complete(void) -{ - while (!(*(volatile unsigned short *)RTC_ISTAT & 0x8000)) { - printf(""); - } - *(volatile unsigned short *)RTC_ISTAT = 0x8000; -} - -/* Enable the RTC prescaler enable register */ -void rtc_init() -{ - *(volatile unsigned short *)RTC_PREN = 0x1; - wait_for_complete(); -} - -/* Set the time. Get the time_in_secs which is the number of seconds since Jan 1970 and set the RTC registers - * based on this value. - */ -void rtc_set(struct rtc_time *tmp) -{ - unsigned long n_days_1970 = 0; - unsigned long n_secs_rem = 0; - unsigned long n_hrs = 0; - unsigned long n_mins = 0; - unsigned long n_secs = 0; - unsigned long time_in_secs; - - if (tmp == NULL) { - printf("Error setting the date/time \n"); - return; - } - - time_in_secs = - mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_hour, - tmp->tm_min, tmp->tm_sec); - - /* Compute no. of days since 1970 */ - n_days_1970 = (unsigned long)(time_in_secs / (NUM_SECS_IN_DAY)); - - /* From the remining secs, compute the hrs(0-23), mins(0-59) and secs(0-59) */ - n_secs_rem = (unsigned long)(time_in_secs % (NUM_SECS_IN_DAY)); - n_hrs = n_secs_rem / (NUM_SECS_IN_HOUR); - n_secs_rem = n_secs_rem % (NUM_SECS_IN_HOUR); - n_mins = n_secs_rem / (NUM_SECS_IN_MIN); - n_secs = n_secs_rem % (NUM_SECS_IN_MIN); - - /* Store the new time in the RTC_STAT register */ - *(volatile unsigned long *)RTC_STAT = - ((n_days_1970 << DAY_BITS_OFF) | (n_hrs << HOUR_BITS_OFF) | - (n_mins << MIN_BITS_OFF) | (n_secs << SEC_BITS_OFF)); - - wait_for_complete(); -} - -/* Read the time from the RTC_STAT. time_in_seconds is seconds since Jan 1970 */ -void rtc_get(struct rtc_time *tmp) -{ - unsigned long cur_rtc_stat = 0; - unsigned long time_in_sec; - unsigned long tm_sec = 0, tm_min = 0, tm_hour = 0, tm_day = 0; - - if (tmp == NULL) { - printf("Error getting the date/time \n"); - return; - } - - /* Read the RTC_STAT register */ - cur_rtc_stat = *(volatile unsigned long *)RTC_STAT; - - /* Get the secs (0-59), mins (0-59), hrs (0-23) and the days since Jan 1970 */ - tm_sec = (cur_rtc_stat >> SEC_BITS_OFF) & 0x3f; - tm_min = (cur_rtc_stat >> MIN_BITS_OFF) & 0x3f; - tm_hour = (cur_rtc_stat >> HOUR_BITS_OFF) & 0x1f; - tm_day = (cur_rtc_stat >> DAY_BITS_OFF) & 0x7fff; - - /* Calculate the total number of seconds since Jan 1970 */ - time_in_sec = (tm_sec) + - MIN_TO_SECS(tm_min) + HRS_TO_SECS(tm_hour) + DAYS_TO_SECS(tm_day); - to_tm(time_in_sec, tmp); -} -#endif diff --git a/drivers/rtc/bfin_rtc.c b/drivers/rtc/bfin_rtc.c new file mode 100644 index 0000000..5755a20 --- /dev/null +++ b/drivers/rtc/bfin_rtc.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2004-2008 Analog Devices Inc. + * + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <command.h> +#include <rtc.h> + +#if defined(CONFIG_RTC_BFIN) && defined(CONFIG_CMD_DATE) + +#include <asm/blackfin.h> +#include <asm/mach-common/bits/rtc.h> + +#define pr_stamp() debug("%s:%s:%i: here i am\n", __FILE__, __func__, __LINE__) + +#define MIN_TO_SECS(x) (60 * (x)) +#define HRS_TO_SECS(x) (60 * MIN_TO_SECS(x)) +#define DAYS_TO_SECS(x) (24 * HRS_TO_SECS(x)) + +#define NUM_SECS_IN_MIN MIN_TO_SECS(1) +#define NUM_SECS_IN_HR HRS_TO_SECS(1) +#define NUM_SECS_IN_DAY DAYS_TO_SECS(1) + +/* Our on-chip RTC has no notion of "reset" */ +void rtc_reset(void) +{ + return; +} + +/* Wait for pending writes to complete */ +static void wait_for_complete(void) +{ + pr_stamp(); + while (!(bfin_read_RTC_ISTAT() & WRITE_COMPLETE)) + if (!(bfin_read_RTC_ISTAT() & WRITE_PENDING)) + break; + bfin_write_RTC_ISTAT(WRITE_COMPLETE); +} + +/* Enable the RTC prescaler enable register */ +int rtc_init(void) +{ + pr_stamp(); + bfin_write_RTC_PREN(0x1); + return 0; +} + +/* Set the time. Get the time_in_secs which is the number of seconds since Jan 1970 and set the RTC registers + * based on this value. + */ +void rtc_set(struct rtc_time *tmp) +{ + unsigned long remain, days, hrs, mins, secs; + + pr_stamp(); + + if (tmp == NULL) { + puts("Error setting the date/time\n"); + return; + } + + wait_for_complete(); + + /* Calculate number of seconds this incoming time represents */ + remain = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + /* Figure out how many days since epoch */ + days = remain / NUM_SECS_IN_DAY; + + /* From the remaining secs, compute the hrs(0-23), mins(0-59) and secs(0-59) */ + remain = remain % NUM_SECS_IN_DAY; + hrs = remain / NUM_SECS_IN_HR; + remain = remain % NUM_SECS_IN_HR; + mins = remain / NUM_SECS_IN_MIN; + secs = remain % NUM_SECS_IN_MIN; + + /* Encode these time values into our RTC_STAT register */ + bfin_write_RTC_STAT(SET_ALARM(days, hrs, mins, secs)); +} + +/* Read the time from the RTC_STAT. time_in_seconds is seconds since Jan 1970 */ +void rtc_get(struct rtc_time *tmp) +{ + uint32_t cur_rtc_stat; + int time_in_sec; + int tm_sec, tm_min, tm_hr, tm_day; + + pr_stamp(); + + if (tmp == NULL) { + puts("Error getting the date/time\n"); + return; + } + + wait_for_complete(); + + /* Read the RTC_STAT register */ + cur_rtc_stat = bfin_read_RTC_STAT(); + + /* Convert our encoded format into actual time values */ + tm_sec = (cur_rtc_stat & RTC_SEC) >> RTC_SEC_P; + tm_min = (cur_rtc_stat & RTC_MIN) >> RTC_MIN_P; + tm_hr = (cur_rtc_stat & RTC_HR ) >> RTC_HR_P; + tm_day = (cur_rtc_stat & RTC_DAY) >> RTC_DAY_P; + + /* Calculate the total number of seconds since epoch */ + time_in_sec = (tm_sec) + MIN_TO_SECS(tm_min) + HRS_TO_SECS(tm_hr) + DAYS_TO_SECS(tm_day); + to_tm(time_in_sec, tmp); +} + +#endif diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c index 6c94ae1..9122f12 100644 --- a/drivers/rtc/rx8025.c +++ b/drivers/rtc/rx8025.c @@ -142,7 +142,6 @@ void rtc_get (struct rtc_time *tmp) tmp->tm_hour, tmp->tm_min, tmp->tm_sec); } - /* * Set the RTC */ @@ -166,7 +165,6 @@ void rtc_set (struct rtc_time *tmp) rtc_write (RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412); } - /* * Reset the RTC. We setting the date back to 1970-01-01. */ @@ -200,7 +198,6 @@ void rtc_reset (void) return; } - /* * Helper functions */ @@ -224,4 +221,4 @@ static unsigned char bin2bcd (unsigned int n) return (((n / 10) << 4) | (n % 10)); } -#endif /* CONFIG_RTC_RX8025 && (CFG_COMMANDS & CFG_CMD_DATE) */ +#endif /* CONFIG_RTC_RX8025 && CONFIG_CMD_DATE */ diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c index a3d1c95..2fe838c 100644 --- a/drivers/spi/mpc8xxx_spi.c +++ b/drivers/spi/mpc8xxx_spi.c @@ -22,11 +22,11 @@ */ #include <common.h> +#if defined(CONFIG_MPC8XXX_SPI) && defined(CONFIG_HARD_SPI) + #include <spi.h> #include <asm/mpc8xxx_spi.h> -#ifdef CONFIG_HARD_SPI - #define SPI_EV_NE (0x80000000 >> 22) /* Receiver Not Empty */ #define SPI_EV_NF (0x80000000 >> 23) /* Transmitter Not Full */ diff --git a/drivers/video/ati_radeon_fb.c b/drivers/video/ati_radeon_fb.c index 0bdaa1c..a1e7bae 100644 --- a/drivers/video/ati_radeon_fb.c +++ b/drivers/video/ati_radeon_fb.c @@ -44,6 +44,7 @@ #include <asm/io.h> #include <malloc.h> #include <video_fb.h> +#include "videomodes.h" #include <radeon.h> #include "ati_ids.h" @@ -65,11 +66,27 @@ #define MAX_MAPPED_VRAM (2048*2048*4) #define MIN_MAPPED_VRAM (1024*768*1) +#define RADEON_BUFFER_ALIGN 0x00000fff +#define SURF_UPPER_BOUND(x,y,bpp) (((((x) * (((y) + 15) & ~15) * (bpp)/8) + RADEON_BUFFER_ALIGN) \ + & ~RADEON_BUFFER_ALIGN) - 1) +#define RADEON_CRT_PITCH(width, bpp) ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) | \ + ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) << 16)) + +#define CRTC_H_TOTAL_DISP_VAL(htotal, hdisp) \ + (((((htotal) / 8) - 1) & 0x3ff) | (((((hdisp) / 8) - 1) & 0x1ff) << 16)) +#define CRTC_HSYNC_STRT_WID_VAL(hsync_srtr, hsync_wid) \ + (((hsync_srtr) & 0x1fff) | (((hsync_wid) & 0x3f) << 16)) +#define CRTC_V_TOTAL_DISP_VAL(vtotal, vdisp) \ + ((((vtotal) - 1) & 0xffff) | (((vdisp) - 1) << 16)) +#define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ + ((((vsync_srtr) - 1) & 0xfff) | (((vsync_wid) & 0x1f) << 16)) + /*#define PCI_VENDOR_ID_ATI*/ #define PCI_CHIP_RV280_5960 0x5960 #define PCI_CHIP_RV280_5961 0x5961 #define PCI_CHIP_RV280_5962 0x5962 #define PCI_CHIP_RV280_5964 0x5964 +#define PCI_CHIP_RV280_5C63 0x5C63 #define PCI_CHIP_RV370_5B60 0x5B60 #define PCI_CHIP_RV380_5657 0x5657 #define PCI_CHIP_R420_554d 0x554d @@ -79,6 +96,7 @@ static struct pci_device_id ati_radeon_pci_ids[] = { {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5961}, {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5962}, {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5964}, + {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5C63}, {PCI_VENDOR_ID_ATI, PCI_CHIP_RV370_5B60}, {PCI_VENDOR_ID_ATI, PCI_CHIP_RV380_5657}, {PCI_VENDOR_ID_ATI, PCI_CHIP_R420_554d}, @@ -90,6 +108,7 @@ static u16 ati_radeon_id_family_table[][2] = { {PCI_CHIP_RV280_5961, CHIP_FAMILY_RV280}, {PCI_CHIP_RV280_5962, CHIP_FAMILY_RV280}, {PCI_CHIP_RV280_5964, CHIP_FAMILY_RV280}, + {PCI_CHIP_RV280_5C63, CHIP_FAMILY_RV280}, {PCI_CHIP_RV370_5B60, CHIP_FAMILY_RV380}, {PCI_CHIP_RV380_5657, CHIP_FAMILY_RV380}, {PCI_CHIP_R420_554d, CHIP_FAMILY_R420}, @@ -350,6 +369,204 @@ void radeon_setmode(void) radeon_write_pll_regs(rinfo, mode); } +static void set_pal(void) +{ + int idx, val = 0; + + for (idx = 0; idx < 256; idx++) { + OUTREG8(PALETTE_INDEX, idx); + OUTREG(PALETTE_DATA, val); + val += 0x00010101; + } +} + +void radeon_setmode_9200(int vesa_idx, int bpp) +{ + struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); + + mode->crtc_gen_cntl = CRTC_EN | CRTC_EXT_DISP_EN; + mode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON; + mode->dac_cntl = DAC_MASK_ALL | DAC_VGA_ADR_EN | DAC_8BIT_EN; + mode->crtc_offset_cntl = CRTC_OFFSET_CNTL__CRTC_TILE_EN; + + switch (bpp) { + case 24: + mode->crtc_gen_cntl |= 0x6 << 8; /* x888 */ +#if defined(__BIG_ENDIAN) + mode->surface_cntl = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; + mode->surf_info[0] = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; +#endif + break; + case 16: + mode->crtc_gen_cntl |= 0x4 << 8; /* 565 */ +#if defined(__BIG_ENDIAN) + mode->surface_cntl = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; + mode->surf_info[0] = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; +#endif + break; + default: + mode->crtc_gen_cntl |= 0x2 << 8; /* palette */ + mode->surface_cntl = 0x00000000; + break; + } + + switch (vesa_idx) { + case RES_MODE_1280x1024: + mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1688,1280); + mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(1066,1024); + mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); +#if defined(CONFIG_RADEON_VREFRESH_75HZ) + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1288,18); + mode->ppll_div_3 = 0x00010078; +#else /* default @ 60 Hz */ + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1320,14); + mode->ppll_div_3 = 0x00010060; +#endif + /* + * for this mode pitch expands to the same value for 32, 16 and 8 bpp, + * so we set it here once only. + */ + mode->crtc_pitch = RADEON_CRT_PITCH(1280,32); + switch (bpp) { + case 24: + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 4 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,32); + break; + case 16: + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 2 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,16); + break; + default: /* 8 bpp */ + mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1280 * 1 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,8); + break; + } + break; + case RES_MODE_1024x768: +#if defined(CONFIG_RADEON_VREFRESH_75HZ) + mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1312,1024); + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1032,12); + mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(800,768); + mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); + mode->ppll_div_3 = 0x0002008c; +#else /* @ 60 Hz */ + mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1344,1024); + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1040,17) | CRTC_H_SYNC_POL; + mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(806,768); + mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) | CRTC_V_SYNC_POL; + mode->ppll_div_3 = 0x00020074; +#endif + /* also same pitch value for 32, 16 and 8 bpp */ + mode->crtc_pitch = RADEON_CRT_PITCH(1024,32); + switch (bpp) { + case 24: + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 4 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,32); + break; + case 16: + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 2 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,16); + break; + default: /* 8 bpp */ + mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,8); + break; + } + break; + case RES_MODE_800x600: + mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1056,800); +#if defined(CONFIG_RADEON_VREFRESH_75HZ) + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(808,10); + mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(625,600); + mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); + mode->ppll_div_3 = 0x000300b0; +#else /* @ 60 Hz */ + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(832,16); + mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(628,600); + mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); + mode->ppll_div_3 = 0x0003008e; +#endif + switch (bpp) { + case 24: + mode->crtc_pitch = RADEON_CRT_PITCH(832,32); + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (832 * 4 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(832,600,32); + break; + case 16: + mode->crtc_pitch = RADEON_CRT_PITCH(896,16); + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (896 * 2 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(896,600,16); + break; + default: /* 8 bpp */ + mode->crtc_pitch = RADEON_CRT_PITCH(1024,8); + mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,600,8); + break; + } + break; + default: /* RES_MODE_640x480 */ +#if defined(CONFIG_RADEON_VREFRESH_75HZ) + mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(840,640); + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(648,8) | CRTC_H_SYNC_POL; + mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(500,480); + mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) | CRTC_V_SYNC_POL; + mode->ppll_div_3 = 0x00030070; +#else /* @ 60 Hz */ + mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(800,640); + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(674,12) | CRTC_H_SYNC_POL; + mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(525,480); + mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) | CRTC_V_SYNC_POL; + mode->ppll_div_3 = 0x00030059; +#endif + /* also same pitch value for 32, 16 and 8 bpp */ + mode->crtc_pitch = RADEON_CRT_PITCH(640,32); + switch (bpp) { + case 24: + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 4 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,32); + break; + case 16: + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 2 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,16); + break; + default: /* 8 bpp */ + mode->crtc_offset_cntl = 0x00000000; + break; + } + break; + } + + OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl | CRTC_DISP_REQ_EN_B); + OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, + (CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); + OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); + OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); + OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); + OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); + OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); + OUTREG(CRTC_OFFSET, 0); + OUTREG(CRTC_OFFSET_CNTL, mode->crtc_offset_cntl); + OUTREG(CRTC_PITCH, mode->crtc_pitch); + OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); + + mode->clk_cntl_index = 0x300; + mode->ppll_ref_div = 0xc; + + radeon_write_pll_regs(rinfo, mode); + + OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, + ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); + OUTREG(SURFACE0_INFO, mode->surf_info[0]); + OUTREG(SURFACE0_LOWER_BOUND, 0); + OUTREG(SURFACE0_UPPER_BOUND, mode->surf_upper_bound[0]); + OUTREG(SURFACE_CNTL, mode->surface_cntl); + + if (bpp > 8) + set_pal(); + + free(mode); +} + #include "../bios_emulator/include/biosemu.h" extern int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp); @@ -421,29 +638,101 @@ GraphicDevice ctfb; void *video_hw_init(void) { GraphicDevice *pGD = (GraphicDevice *) & ctfb; - int i; u32 *vm; + char *penv; + unsigned long t1, hsynch, vsynch; + int bits_per_pixel, i, tmp, vesa_idx = 0, videomode; + struct ctfb_res_modes *res_mode; + struct ctfb_res_modes var_mode; rinfo = malloc(sizeof(struct radeonfb_info)); + printf("Video: "); if(radeon_probe(rinfo)) { printf("No radeon video card found!\n"); return NULL; } - /* fill in Graphic device struct */ - sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", 640, - 480, 16, (1000 / 1000), - (2000 / 1000)); - printf ("%s\n", pGD->modeIdent); + tmp = 0; - pGD->winSizeX = 640; - pGD->winSizeY = 480; - pGD->plnSizeX = 640; - pGD->plnSizeY = 480; + videomode = CFG_DEFAULT_VIDEO_MODE; + /* get video mode via environment */ + if ((penv = getenv ("videomode")) != NULL) { + /* deceide if it is a string */ + if (penv[0] <= '9') { + videomode = (int) simple_strtoul (penv, NULL, 16); + tmp = 1; + } + } else { + tmp = 1; + } + if (tmp) { + /* parameter are vesa modes */ + /* search params */ + for (i = 0; i < VESA_MODES_COUNT; i++) { + if (vesa_modes[i].vesanr == videomode) + break; + } + if (i == VESA_MODES_COUNT) { + printf ("no VESA Mode found, switching to mode 0x%x ", CFG_DEFAULT_VIDEO_MODE); + i = 0; + } + res_mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex]; + bits_per_pixel = vesa_modes[i].bits_per_pixel; + vesa_idx = vesa_modes[i].resindex; + } else { + res_mode = (struct ctfb_res_modes *) &var_mode; + bits_per_pixel = video_get_params (res_mode, penv); + } - pGD->gdfBytesPP = 1; - pGD->gdfIndex = GDF__8BIT_INDEX; + /* calculate hsynch and vsynch freq (info only) */ + t1 = (res_mode->left_margin + res_mode->xres + + res_mode->right_margin + res_mode->hsync_len) / 8; + t1 *= 8; + t1 *= res_mode->pixclock; + t1 /= 1000; + hsynch = 1000000000L / t1; + t1 *= (res_mode->upper_margin + res_mode->yres + + res_mode->lower_margin + res_mode->vsync_len); + t1 /= 1000; + vsynch = 1000000000L / t1; + + /* fill in Graphic device struct */ + sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, + res_mode->yres, bits_per_pixel, (hsynch / 1000), + (vsynch / 1000)); + printf ("%s\n", pGD->modeIdent); + pGD->winSizeX = res_mode->xres; + pGD->winSizeY = res_mode->yres; + pGD->plnSizeX = res_mode->xres; + pGD->plnSizeY = res_mode->yres; + + switch (bits_per_pixel) { + case 24: + pGD->gdfBytesPP = 4; + pGD->gdfIndex = GDF_32BIT_X888RGB; + if (res_mode->xres == 800) { + pGD->winSizeX = 832; + pGD->plnSizeX = 832; + } + break; + case 16: + pGD->gdfBytesPP = 2; + pGD->gdfIndex = GDF_16BIT_565RGB; + if (res_mode->xres == 800) { + pGD->winSizeX = 896; + pGD->plnSizeX = 896; + } + break; + default: + if (res_mode->xres == 800) { + pGD->winSizeX = 1024; + pGD->plnSizeX = 1024; + } + pGD->gdfBytesPP = 1; + pGD->gdfIndex = GDF__8BIT_INDEX; + break; + } pGD->isaBase = CFG_ISA_IO_BASE_ADDRESS; pGD->pciBase = rinfo->fb_base_phys; @@ -464,14 +753,17 @@ void *video_hw_init(void) pGD->cprBase = rinfo->fb_base_phys; /* Dummy */ /* set up Hardware */ - /* Clear video memory */ - i = pGD->memSize / 4; + /* Clear video memory (only visible screen area) */ + i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4; vm = (unsigned int *) pGD->pciBase; while (i--) *vm++ = 0; /*SetDrawingEngine (bits_per_pixel);*/ - radeon_setmode(); + if (rinfo->family == CHIP_FAMILY_RV280) + radeon_setmode_9200(vesa_idx, bits_per_pixel); + else + radeon_setmode(); return ((void *) pGD); } |