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-rw-r--r--drivers/core/Makefile1
-rw-r--r--drivers/core/device.c36
-rw-r--r--drivers/core/lists.c9
-rw-r--r--drivers/core/simple-bus.c33
-rw-r--r--drivers/core/uclass.c4
-rw-r--r--drivers/dfu/dfu_sf.c1
-rw-r--r--drivers/gpio/bcm2835_gpio.c180
-rw-r--r--drivers/gpio/mxc_gpio.c304
-rw-r--r--drivers/gpio/s5p_gpio.c446
-rw-r--r--drivers/misc/cros_ec.c122
-rw-r--r--drivers/misc/cros_ec_sandbox.c99
-rw-r--r--drivers/misc/cros_ec_spi.c87
-rw-r--r--drivers/mmc/s5p_sdhci.c7
-rw-r--r--drivers/mtd/spi/Makefile7
-rw-r--r--drivers/mtd/spi/ramtron.c1
-rw-r--r--drivers/mtd/spi/sandbox.c338
-rw-r--r--drivers/mtd/spi/sf-uclass.c63
-rw-r--r--drivers/mtd/spi/sf_internal.h67
-rw-r--r--drivers/mtd/spi/sf_params.c1
-rw-r--r--drivers/mtd/spi/sf_probe.c154
-rw-r--r--drivers/mtd/spi/spi_spl_load.c1
-rw-r--r--drivers/serial/Makefile5
-rw-r--r--drivers/serial/serial-uclass.c32
-rw-r--r--drivers/serial/serial_mxc.c170
-rw-r--r--drivers/serial/serial_pl01x.c373
-rw-r--r--drivers/serial/serial_pl01x_internal.h (renamed from drivers/serial/serial_pl01x.h)0
-rw-r--r--drivers/serial/serial_s5p.c255
-rw-r--r--drivers/spi/Makefile9
-rw-r--r--drivers/spi/exynos_spi.c513
-rw-r--r--drivers/spi/fdt_spi.c186
-rw-r--r--drivers/spi/sandbox_spi.c200
-rw-r--r--drivers/spi/soft_spi.c227
-rw-r--r--drivers/spi/soft_spi_legacy.c176
-rw-r--r--drivers/spi/spi-emul-uclass.c15
-rw-r--r--drivers/spi/spi-uclass.c390
-rw-r--r--drivers/spi/tegra114_spi.c254
-rw-r--r--drivers/spi/tegra20_sflash.c238
-rw-r--r--drivers/spi/tegra20_slink.c235
-rw-r--r--drivers/spi/tegra_spi.h12
39 files changed, 3514 insertions, 1737 deletions
diff --git a/drivers/core/Makefile b/drivers/core/Makefile
index c7905b1..151c239 100644
--- a/drivers/core/Makefile
+++ b/drivers/core/Makefile
@@ -5,3 +5,4 @@
#
obj-y := device.o lists.o root.o uclass.o util.o
+obj-$(CONFIG_OF_CONTROL) += simple-bus.o
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 32e80e8..49faa29 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -232,7 +232,7 @@ static void device_free(struct udevice *dev)
}
}
-int device_probe(struct udevice *dev)
+int device_probe_child(struct udevice *dev, void *parent_priv)
{
struct driver *drv;
int size = 0;
@@ -282,6 +282,8 @@ int device_probe(struct udevice *dev)
ret = -ENOMEM;
goto fail;
}
+ if (parent_priv)
+ memcpy(dev->parent_priv, parent_priv, size);
}
ret = device_probe(dev->parent);
@@ -335,6 +337,11 @@ fail:
return ret;
}
+int device_probe(struct udevice *dev)
+{
+ return device_probe_child(dev, NULL);
+}
+
int device_remove(struct udevice *dev)
{
struct driver *drv;
@@ -514,3 +521,30 @@ int device_get_child_by_of_offset(struct udevice *parent, int seq,
ret = device_find_child_by_of_offset(parent, seq, &dev);
return device_get_device_tail(dev, ret, devp);
}
+
+int device_find_first_child(struct udevice *parent, struct udevice **devp)
+{
+ if (list_empty(&parent->child_head)) {
+ *devp = NULL;
+ } else {
+ *devp = list_first_entry(&parent->child_head, struct udevice,
+ sibling_node);
+ }
+
+ return 0;
+}
+
+int device_find_next_child(struct udevice **devp)
+{
+ struct udevice *dev = *devp;
+ struct udevice *parent = dev->parent;
+
+ if (list_is_last(&dev->sibling_node, &parent->child_head)) {
+ *devp = NULL;
+ } else {
+ *devp = list_entry(dev->sibling_node.next, struct udevice,
+ sibling_node);
+ }
+
+ return 0;
+}
diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index 699f94b..3a1ea85 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -24,19 +24,12 @@ struct driver *lists_driver_lookup_name(const char *name)
ll_entry_start(struct driver, driver);
const int n_ents = ll_entry_count(struct driver, driver);
struct driver *entry;
- int len;
if (!drv || !n_ents)
return NULL;
- len = strlen(name);
-
for (entry = drv; entry != drv + n_ents; entry++) {
- if (strncmp(name, entry->name, len))
- continue;
-
- /* Full match */
- if (len == strlen(entry->name))
+ if (!strcmp(name, entry->name))
return entry;
}
diff --git a/drivers/core/simple-bus.c b/drivers/core/simple-bus.c
new file mode 100644
index 0000000..3ea4d82
--- /dev/null
+++ b/drivers/core/simple-bus.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/root.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int simple_bus_post_bind(struct udevice *dev)
+{
+ return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+}
+
+UCLASS_DRIVER(simple_bus) = {
+ .id = UCLASS_SIMPLE_BUS,
+ .name = "simple_bus",
+ .post_bind = simple_bus_post_bind,
+};
+
+static const struct udevice_id generic_simple_bus_ids[] = {
+ { .compatible = "simple-bus" },
+ { }
+};
+
+U_BOOT_DRIVER(simple_bus_drv) = {
+ .name = "generic_simple_bus",
+ .id = UCLASS_SIMPLE_BUS,
+ .of_match = generic_simple_bus_ids,
+};
diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index 61ca17e..901b06e 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -60,10 +60,6 @@ static int uclass_add(enum uclass_id id, struct uclass **ucp)
id);
return -ENOENT;
}
- if (uc_drv->ops) {
- dm_warn("No ops for uclass id %d\n", id);
- return -EINVAL;
- }
uc = calloc(1, sizeof(*uc));
if (!uc)
return -ENOMEM;
diff --git a/drivers/dfu/dfu_sf.c b/drivers/dfu/dfu_sf.c
index 91f6df2..c3d3c3b 100644
--- a/drivers/dfu/dfu_sf.c
+++ b/drivers/dfu/dfu_sf.c
@@ -9,6 +9,7 @@
#include <errno.h>
#include <div64.h>
#include <dfu.h>
+#include <spi.h>
#include <spi_flash.h>
static long dfu_get_medium_size_sf(struct dfu_entity *dfu)
diff --git a/drivers/gpio/bcm2835_gpio.c b/drivers/gpio/bcm2835_gpio.c
index 97b5137..332cfc2 100644
--- a/drivers/gpio/bcm2835_gpio.c
+++ b/drivers/gpio/bcm2835_gpio.c
@@ -6,73 +6,207 @@
*/
#include <common.h>
+#include <dm.h>
+#include <errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
-inline int gpio_is_valid(unsigned gpio)
+#define GPIO_NAME_SIZE 20
+
+struct bcm2835_gpios {
+ char label[BCM2835_GPIO_COUNT][GPIO_NAME_SIZE];
+ struct bcm2835_gpio_regs *reg;
+};
+
+/**
+ * gpio_is_requested() - check if a GPIO has been requested
+ *
+ * @bank: Bank to check
+ * @offset: GPIO offset within bank to check
+ * @return true if marked as requested, false if not
+ */
+static inline bool gpio_is_requested(struct bcm2835_gpios *gpios, int offset)
{
- return (gpio < BCM2835_GPIO_COUNT);
+ return *gpios->label[offset] != '\0';
}
-int gpio_request(unsigned gpio, const char *label)
+static int check_requested(struct udevice *dev, unsigned offset,
+ const char *func)
{
- return !gpio_is_valid(gpio);
+ struct bcm2835_gpios *gpios = dev_get_priv(dev);
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+
+ if (!gpio_is_requested(gpios, offset)) {
+ printf("omap_gpio: %s: error: gpio %s%d not requested\n",
+ func, uc_priv->bank_name, offset);
+ return -EPERM;
+ }
+
+ return 0;
}
-int gpio_free(unsigned gpio)
+static int bcm2835_gpio_request(struct udevice *dev, unsigned offset,
+ const char *label)
{
+ struct bcm2835_gpios *gpios = dev_get_priv(dev);
+
+ if (gpio_is_requested(gpios, offset))
+ return -EBUSY;
+
+ strncpy(gpios->label[offset], label, GPIO_NAME_SIZE);
+ gpios->label[offset][GPIO_NAME_SIZE - 1] = '\0';
+
return 0;
}
-int gpio_direction_input(unsigned gpio)
+static int bcm2835_gpio_free(struct udevice *dev, unsigned offset)
{
- struct bcm2835_gpio_regs *reg =
- (struct bcm2835_gpio_regs *)BCM2835_GPIO_BASE;
+ struct bcm2835_gpios *gpios = dev_get_priv(dev);
+ int ret;
+
+ ret = check_requested(dev, offset, __func__);
+ if (ret)
+ return ret;
+ gpios->label[offset][0] = '\0';
+
+ return 0;
+}
+
+static int bcm2835_gpio_direction_input(struct udevice *dev, unsigned gpio)
+{
+ struct bcm2835_gpios *gpios = dev_get_priv(dev);
unsigned val;
- val = readl(&reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
+ val = readl(&gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
val &= ~(BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(gpio));
val |= (BCM2835_GPIO_INPUT << BCM2835_GPIO_FSEL_SHIFT(gpio));
- writel(val, &reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
+ writel(val, &gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
return 0;
}
-int gpio_direction_output(unsigned gpio, int value)
+static int bcm2835_gpio_direction_output(struct udevice *dev, unsigned gpio,
+ int value)
{
- struct bcm2835_gpio_regs *reg =
- (struct bcm2835_gpio_regs *)BCM2835_GPIO_BASE;
+ struct bcm2835_gpios *gpios = dev_get_priv(dev);
unsigned val;
gpio_set_value(gpio, value);
- val = readl(&reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
+ val = readl(&gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
val &= ~(BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(gpio));
val |= (BCM2835_GPIO_OUTPUT << BCM2835_GPIO_FSEL_SHIFT(gpio));
- writel(val, &reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
+ writel(val, &gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
return 0;
}
-int gpio_get_value(unsigned gpio)
+static bool bcm2835_gpio_is_output(const struct bcm2835_gpios *gpios, int gpio)
+{
+ u32 val;
+
+ val = readl(&gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
+ val &= BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(gpio);
+ return val ? true : false;
+}
+
+static int bcm2835_get_value(const struct bcm2835_gpios *gpios, unsigned gpio)
{
- struct bcm2835_gpio_regs *reg =
- (struct bcm2835_gpio_regs *)BCM2835_GPIO_BASE;
unsigned val;
- val = readl(&reg->gplev[BCM2835_GPIO_COMMON_BANK(gpio)]);
+ val = readl(&gpios->reg->gplev[BCM2835_GPIO_COMMON_BANK(gpio)]);
return (val >> BCM2835_GPIO_COMMON_SHIFT(gpio)) & 0x1;
}
-int gpio_set_value(unsigned gpio, int value)
+static int bcm2835_gpio_get_value(struct udevice *dev, unsigned gpio)
{
- struct bcm2835_gpio_regs *reg =
- (struct bcm2835_gpio_regs *)BCM2835_GPIO_BASE;
- u32 *output_reg = value ? reg->gpset : reg->gpclr;
+ const struct bcm2835_gpios *gpios = dev_get_priv(dev);
+
+ return bcm2835_get_value(gpios, gpio);
+}
+
+static int bcm2835_gpio_set_value(struct udevice *dev, unsigned gpio,
+ int value)
+{
+ struct bcm2835_gpios *gpios = dev_get_priv(dev);
+ u32 *output_reg = value ? gpios->reg->gpset : gpios->reg->gpclr;
writel(1 << BCM2835_GPIO_COMMON_SHIFT(gpio),
&output_reg[BCM2835_GPIO_COMMON_BANK(gpio)]);
return 0;
}
+
+static int bcm2835_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+ struct bcm2835_gpios *gpios = dev_get_priv(dev);
+
+ if (!gpio_is_requested(gpios, offset))
+ return GPIOF_UNUSED;
+
+ /* GPIOF_FUNC is not implemented yet */
+ if (bcm2835_gpio_is_output(gpios, offset))
+ return GPIOF_OUTPUT;
+ else
+ return GPIOF_INPUT;
+}
+
+static int bcm2835_gpio_get_state(struct udevice *dev, unsigned int offset,
+ char *buf, int bufsize)
+{
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+ struct bcm2835_gpios *gpios = dev_get_priv(dev);
+ const char *label;
+ bool requested;
+ bool is_output;
+ int size;
+
+ label = gpios->label[offset];
+ is_output = bcm2835_gpio_is_output(gpios, offset);
+ size = snprintf(buf, bufsize, "%s%d: ",
+ uc_priv->bank_name ? uc_priv->bank_name : "", offset);
+ buf += size;
+ bufsize -= size;
+ requested = gpio_is_requested(gpios, offset);
+ snprintf(buf, bufsize, "%s: %d [%c]%s%s",
+ is_output ? "out" : " in",
+ bcm2835_get_value(gpios, offset),
+ requested ? 'x' : ' ',
+ requested ? " " : "",
+ label);
+
+ return 0;
+}
+
+static const struct dm_gpio_ops gpio_bcm2835_ops = {
+ .request = bcm2835_gpio_request,
+ .free = bcm2835_gpio_free,
+ .direction_input = bcm2835_gpio_direction_input,
+ .direction_output = bcm2835_gpio_direction_output,
+ .get_value = bcm2835_gpio_get_value,
+ .set_value = bcm2835_gpio_set_value,
+ .get_function = bcm2835_gpio_get_function,
+ .get_state = bcm2835_gpio_get_state,
+};
+
+static int bcm2835_gpio_probe(struct udevice *dev)
+{
+ struct bcm2835_gpios *gpios = dev_get_priv(dev);
+ struct bcm2835_gpio_platdata *plat = dev_get_platdata(dev);
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+
+ uc_priv->bank_name = "GPIO";
+ uc_priv->gpio_count = BCM2835_GPIO_COUNT;
+ gpios->reg = (struct bcm2835_gpio_regs *)plat->base;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(gpio_bcm2835) = {
+ .name = "gpio_bcm2835",
+ .id = UCLASS_GPIO,
+ .ops = &gpio_bcm2835_ops,
+ .probe = bcm2835_gpio_probe,
+ .priv_auto_alloc_size = sizeof(struct bcm2835_gpios),
+};
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index 6a572d5..3f7b7d2 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -8,16 +8,31 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <errno.h>
+#include <dm.h>
+#include <malloc.h>
#include <asm/arch/imx-regs.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <errno.h>
enum mxc_gpio_direction {
MXC_GPIO_DIRECTION_IN,
MXC_GPIO_DIRECTION_OUT,
};
+#define GPIO_NAME_SIZE 20
+#define GPIO_PER_BANK 32
+
+struct mxc_gpio_plat {
+ struct gpio_regs *regs;
+};
+
+struct mxc_bank_info {
+ char label[GPIO_PER_BANK][GPIO_NAME_SIZE];
+ struct gpio_regs *regs;
+};
+
+#ifndef CONFIG_DM_GPIO
#define GPIO_TO_PORT(n) (n / 32)
/* GPIO port description */
@@ -134,3 +149,290 @@ int gpio_direction_output(unsigned gpio, int value)
return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
}
+#endif
+
+#ifdef CONFIG_DM_GPIO
+/**
+ * gpio_is_requested() - check if a GPIO has been requested
+ *
+ * @bank: Bank to check
+ * @offset: GPIO offset within bank to check
+ * @return true if marked as requested, false if not
+ */
+static inline bool gpio_is_requested(struct mxc_bank_info *bank, int offset)
+{
+ return *bank->label[offset] != '\0';
+}
+
+static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
+{
+ u32 val;
+
+ val = readl(&regs->gpio_dir);
+
+ return val & (1 << offset) ? 1 : 0;
+}
+
+static void mxc_gpio_bank_direction(struct gpio_regs *regs, int offset,
+ enum mxc_gpio_direction direction)
+{
+ u32 l;
+
+ l = readl(&regs->gpio_dir);
+
+ switch (direction) {
+ case MXC_GPIO_DIRECTION_OUT:
+ l |= 1 << offset;
+ break;
+ case MXC_GPIO_DIRECTION_IN:
+ l &= ~(1 << offset);
+ }
+ writel(l, &regs->gpio_dir);
+}
+
+static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset,
+ int value)
+{
+ u32 l;
+
+ l = readl(&regs->gpio_dr);
+ if (value)
+ l |= 1 << offset;
+ else
+ l &= ~(1 << offset);
+ writel(l, &regs->gpio_dr);
+}
+
+static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset)
+{
+ return (readl(&regs->gpio_psr) >> offset) & 0x01;
+}
+
+static int mxc_gpio_bank_get_output_value(struct gpio_regs *regs, int offset)
+{
+ return (readl(&regs->gpio_dr) >> offset) & 0x01;
+}
+
+static int check_requested(struct udevice *dev, unsigned offset,
+ const char *func)
+{
+ struct mxc_bank_info *bank = dev_get_priv(dev);
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+
+ if (!gpio_is_requested(bank, offset)) {
+ printf("mxc_gpio: %s: error: gpio %s%d not requested\n",
+ func, uc_priv->bank_name, offset);
+ return -EPERM;
+ }
+
+ return 0;
+}
+
+/* set GPIO pin 'gpio' as an input */
+static int mxc_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+ struct mxc_bank_info *bank = dev_get_priv(dev);
+ int ret;
+
+ ret = check_requested(dev, offset, __func__);
+ if (ret)
+ return ret;
+
+ /* Configure GPIO direction as input. */
+ mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_IN);
+
+ return 0;
+}
+
+/* set GPIO pin 'gpio' as an output, with polarity 'value' */
+static int mxc_gpio_direction_output(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct mxc_bank_info *bank = dev_get_priv(dev);
+ int ret;
+
+ ret = check_requested(dev, offset, __func__);
+ if (ret)
+ return ret;
+
+ /* Configure GPIO output value. */
+ mxc_gpio_bank_set_value(bank->regs, offset, value);
+
+ /* Configure GPIO direction as output. */
+ mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_OUT);
+
+ return 0;
+}
+
+/* read GPIO IN value of pin 'gpio' */
+static int mxc_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+ struct mxc_bank_info *bank = dev_get_priv(dev);
+ int ret;
+
+ ret = check_requested(dev, offset, __func__);
+ if (ret)
+ return ret;
+
+ return mxc_gpio_bank_get_value(bank->regs, offset);
+}
+
+/* write GPIO OUT value to pin 'gpio' */
+static int mxc_gpio_set_value(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct mxc_bank_info *bank = dev_get_priv(dev);
+ int ret;
+
+ ret = check_requested(dev, offset, __func__);
+ if (ret)
+ return ret;
+
+ mxc_gpio_bank_set_value(bank->regs, offset, value);
+
+ return 0;
+}
+
+static int mxc_gpio_get_state(struct udevice *dev, unsigned int offset,
+ char *buf, int bufsize)
+{
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+ struct mxc_bank_info *bank = dev_get_priv(dev);
+ const char *label;
+ bool requested;
+ bool is_output;
+ int size;
+
+ label = bank->label[offset];
+ is_output = mxc_gpio_is_output(bank->regs, offset);
+ size = snprintf(buf, bufsize, "%s%d: ",
+ uc_priv->bank_name ? uc_priv->bank_name : "", offset);
+ buf += size;
+ bufsize -= size;
+ requested = gpio_is_requested(bank, offset);
+ snprintf(buf, bufsize, "%s: %d [%c]%s%s",
+ is_output ? "out" : " in",
+ is_output ?
+ mxc_gpio_bank_get_output_value(bank->regs, offset) :
+ mxc_gpio_bank_get_value(bank->regs, offset),
+ requested ? 'x' : ' ',
+ requested ? " " : "",
+ label);
+
+ return 0;
+}
+
+static int mxc_gpio_request(struct udevice *dev, unsigned offset,
+ const char *label)
+{
+ struct mxc_bank_info *bank = dev_get_priv(dev);
+
+ if (gpio_is_requested(bank, offset))
+ return -EBUSY;
+
+ strncpy(bank->label[offset], label, GPIO_NAME_SIZE);
+ bank->label[offset][GPIO_NAME_SIZE - 1] = '\0';
+
+ return 0;
+}
+
+static int mxc_gpio_free(struct udevice *dev, unsigned offset)
+{
+ struct mxc_bank_info *bank = dev_get_priv(dev);
+ int ret;
+
+ ret = check_requested(dev, offset, __func__);
+ if (ret)
+ return ret;
+ bank->label[offset][0] = '\0';
+
+ return 0;
+}
+
+static int mxc_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+ struct mxc_bank_info *bank = dev_get_priv(dev);
+
+ if (!gpio_is_requested(bank, offset))
+ return GPIOF_UNUSED;
+
+ /* GPIOF_FUNC is not implemented yet */
+ if (mxc_gpio_is_output(bank->regs, offset))
+ return GPIOF_OUTPUT;
+ else
+ return GPIOF_INPUT;
+}
+
+static const struct dm_gpio_ops gpio_mxc_ops = {
+ .request = mxc_gpio_request,
+ .free = mxc_gpio_free,
+ .direction_input = mxc_gpio_direction_input,
+ .direction_output = mxc_gpio_direction_output,
+ .get_value = mxc_gpio_get_value,
+ .set_value = mxc_gpio_set_value,
+ .get_function = mxc_gpio_get_function,
+ .get_state = mxc_gpio_get_state,
+};
+
+static const struct mxc_gpio_plat mxc_plat[] = {
+ { (struct gpio_regs *)GPIO1_BASE_ADDR },
+ { (struct gpio_regs *)GPIO2_BASE_ADDR },
+ { (struct gpio_regs *)GPIO3_BASE_ADDR },
+#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
+ defined(CONFIG_MX53) || defined(CONFIG_MX6)
+ { (struct gpio_regs *)GPIO4_BASE_ADDR },
+#endif
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
+ { (struct gpio_regs *)GPIO5_BASE_ADDR },
+ { (struct gpio_regs *)GPIO6_BASE_ADDR },
+#endif
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+ { (struct gpio_regs *)GPIO7_BASE_ADDR },
+#endif
+};
+
+static int mxc_gpio_probe(struct udevice *dev)
+{
+ struct mxc_bank_info *bank = dev_get_priv(dev);
+ struct mxc_gpio_plat *plat = dev_get_platdata(dev);
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+ int banknum;
+ char name[18], *str;
+
+ banknum = plat - mxc_plat;
+ sprintf(name, "GPIO%d_", banknum + 1);
+ str = strdup(name);
+ if (!str)
+ return -ENOMEM;
+ uc_priv->bank_name = str;
+ uc_priv->gpio_count = GPIO_PER_BANK;
+ bank->regs = plat->regs;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(gpio_mxc) = {
+ .name = "gpio_mxc",
+ .id = UCLASS_GPIO,
+ .ops = &gpio_mxc_ops,
+ .probe = mxc_gpio_probe,
+ .priv_auto_alloc_size = sizeof(struct mxc_bank_info),
+};
+
+U_BOOT_DEVICES(mxc_gpios) = {
+ { "gpio_mxc", &mxc_plat[0] },
+ { "gpio_mxc", &mxc_plat[1] },
+ { "gpio_mxc", &mxc_plat[2] },
+#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
+ defined(CONFIG_MX53) || defined(CONFIG_MX6)
+ { "gpio_mxc", &mxc_plat[3] },
+#endif
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
+ { "gpio_mxc", &mxc_plat[4] },
+ { "gpio_mxc", &mxc_plat[5] },
+#endif
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+ { "gpio_mxc", &mxc_plat[6] },
+#endif
+};
+#endif
diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index db7b673..13d74eb 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -6,120 +6,72 @@
*/
#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
#include <asm/io.h>
#include <asm/gpio.h>
-#include <asm/arch/gpio.h>
+#include <dm/device-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
#define S5P_GPIO_GET_PIN(x) (x % GPIO_PER_BANK)
-#define CON_MASK(x) (0xf << ((x) << 2))
-#define CON_SFR(x, v) ((v) << ((x) << 2))
+#define CON_MASK(val) (0xf << ((val) << 2))
+#define CON_SFR(gpio, cfg) ((cfg) << ((gpio) << 2))
+#define CON_SFR_UNSHIFT(val, gpio) ((val) >> ((gpio) << 2))
+
+#define DAT_MASK(gpio) (0x1 << (gpio))
+#define DAT_SET(gpio) (0x1 << (gpio))
+
+#define PULL_MASK(gpio) (0x3 << ((gpio) << 1))
+#define PULL_MODE(gpio, pull) ((pull) << ((gpio) << 1))
+
+#define DRV_MASK(gpio) (0x3 << ((gpio) << 1))
+#define DRV_SET(gpio, mode) ((mode) << ((gpio) << 1))
+#define RATE_MASK(gpio) (0x1 << (gpio + 16))
+#define RATE_SET(gpio) (0x1 << (gpio + 16))
-#define DAT_MASK(x) (0x1 << (x))
-#define DAT_SET(x) (0x1 << (x))
+#define GPIO_NAME_SIZE 20
-#define PULL_MASK(x) (0x3 << ((x) << 1))
-#define PULL_MODE(x, v) ((v) << ((x) << 1))
+/* Platform data for each bank */
+struct exynos_gpio_platdata {
+ struct s5p_gpio_bank *bank;
+ const char *bank_name; /* Name of port, e.g. 'gpa0" */
+};
-#define DRV_MASK(x) (0x3 << ((x) << 1))
-#define DRV_SET(x, m) ((m) << ((x) << 1))
-#define RATE_MASK(x) (0x1 << (x + 16))
-#define RATE_SET(x) (0x1 << (x + 16))
+/* Information about each bank at run-time */
+struct exynos_bank_info {
+ char label[GPIO_PER_BANK][GPIO_NAME_SIZE];
+ struct s5p_gpio_bank *bank;
+};
-#define name_to_gpio(n) s5p_name_to_gpio(n)
-static inline int s5p_name_to_gpio(const char *name)
+static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
{
- unsigned num, irregular_set_number, irregular_bank_base;
- const struct gpio_name_num_table *tabp;
- char this_bank, bank_name, irregular_bank_name;
- char *endp;
-
- /*
- * The gpio name starts with either 'g' or 'gp' followed by the bank
- * name character. Skip one or two characters depending on the prefix.
- */
- if (name[0] == 'g' && name[1] == 'p')
- name += 2;
- else if (name[0] == 'g')
- name++;
- else
- return -1; /* Name must start with 'g' */
-
- bank_name = *name++;
- if (!*name)
- return -1; /* At least one digit is required/expected. */
-
- /*
- * On both exynos5 and exynos5420 architectures there is a bank of
- * GPIOs which does not fall into the regular address pattern. Those
- * banks are c4 on Exynos5 and y7 on Exynos5420. The rest of the below
- * assignments help to handle these irregularities.
- */
-#if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5)
- if (cpu_is_exynos5()) {
- if (proid_is_exynos5420()) {
- tabp = exynos5420_gpio_table;
- irregular_bank_name = 'y';
- irregular_set_number = '7';
- irregular_bank_base = EXYNOS5420_GPIO_Y70;
- } else {
- tabp = exynos5_gpio_table;
- irregular_bank_name = 'c';
- irregular_set_number = '4';
- irregular_bank_base = EXYNOS5_GPIO_C40;
- }
- } else {
- if (proid_is_exynos4412())
- tabp = exynos4x12_gpio_table;
- else
- tabp = exynos4_gpio_table;
- irregular_bank_name = 0;
- irregular_set_number = 0;
- irregular_bank_base = 0;
- }
-#else
- if (cpu_is_s5pc110())
- tabp = s5pc110_gpio_table;
- else
- tabp = s5pc100_gpio_table;
- irregular_bank_name = 0;
- irregular_set_number = 0;
- irregular_bank_base = 0;
-#endif
+ const struct gpio_info *data;
+ unsigned int upto;
+ int i, count;
- this_bank = tabp->bank;
- do {
- if (bank_name == this_bank) {
- unsigned pin_index; /* pin number within the bank */
- if ((bank_name == irregular_bank_name) &&
- (name[0] == irregular_set_number)) {
- pin_index = name[1] - '0';
- /* Irregular sets have 8 pins. */
- if (pin_index >= GPIO_PER_BANK)
- return -1;
- num = irregular_bank_base + pin_index;
- } else {
- pin_index = simple_strtoul(name, &endp, 8);
- pin_index -= tabp->bank_offset;
- /*
- * Sanity check: bunk 'z' has no set number,
- * for all other banks there must be exactly
- * two octal digits, and the resulting number
- * should not exceed the number of pins in the
- * bank.
- */
- if (((bank_name != 'z') && !name[1]) ||
- *endp ||
- (pin_index >= tabp->bank_size))
- return -1;
- num = tabp->base + pin_index;
- }
- return num;
+ data = get_gpio_data();
+ count = get_bank_num();
+ upto = 0;
+
+ for (i = 0; i < count; i++) {
+ debug("i=%d, upto=%d\n", i, upto);
+ if (gpio < data->max_gpio) {
+ struct s5p_gpio_bank *bank;
+ bank = (struct s5p_gpio_bank *)data->reg_addr;
+ bank += (gpio - upto) / GPIO_PER_BANK;
+ debug("gpio=%d, bank=%p\n", gpio, bank);
+ return bank;
}
- this_bank = (++tabp)->bank;
- } while (this_bank);
- return -1;
+ upto = data->max_gpio;
+ data++;
+ }
+
+ return NULL;
}
static void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
@@ -143,16 +95,23 @@ static void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en)
writel(value, &bank->dat);
}
-static void s5p_gpio_direction_output(struct s5p_gpio_bank *bank,
- int gpio, int en)
+#ifdef CONFIG_SPL_BUILD
+/* Common GPIO API - SPL does not support driver model yet */
+int gpio_set_value(unsigned gpio, int value)
{
- s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_OUTPUT);
- s5p_gpio_set_value(bank, gpio, en);
-}
+ s5p_gpio_set_value(s5p_gpio_get_bank(gpio),
+ s5p_gpio_get_pin(gpio), value);
-static void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio)
+ return 0;
+}
+#else
+static int s5p_gpio_get_cfg_pin(struct s5p_gpio_bank *bank, int gpio)
{
- s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_INPUT);
+ unsigned int value;
+
+ value = readl(&bank->con);
+ value &= CON_MASK(gpio);
+ return CON_SFR_UNSHIFT(value, gpio);
}
static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio)
@@ -162,6 +121,7 @@ static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio)
value = readl(&bank->dat);
return !!(value & DAT_MASK(gpio));
}
+#endif /* CONFIG_SPL_BUILD */
static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
{
@@ -222,78 +182,156 @@ static void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
writel(value, &bank->drv);
}
-struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
+int s5p_gpio_get_pin(unsigned gpio)
{
- const struct gpio_info *data;
- unsigned int upto;
- int i, count;
+ return S5P_GPIO_GET_PIN(gpio);
+}
- data = get_gpio_data();
- count = get_bank_num();
- upto = 0;
+/* Driver model interface */
+#ifndef CONFIG_SPL_BUILD
+static int exynos_gpio_get_state(struct udevice *dev, unsigned int offset,
+ char *buf, int bufsize)
+{
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+ struct exynos_bank_info *state = dev_get_priv(dev);
+ const char *label;
+ bool is_output;
+ int size;
+ int cfg;
+
+ label = state->label[offset];
+ cfg = s5p_gpio_get_cfg_pin(state->bank, offset);
+ is_output = cfg == S5P_GPIO_OUTPUT;
+ size = snprintf(buf, bufsize, "%s%d: ",
+ uc_priv->bank_name ? uc_priv->bank_name : "", offset);
+ buf += size;
+ bufsize -= size;
+ if (is_output || cfg == S5P_GPIO_INPUT) {
+ snprintf(buf, bufsize, "%s: %d [%c]%s%s",
+ is_output ? "out" : " in",
+ s5p_gpio_get_value(state->bank, offset),
+ *label ? 'x' : ' ',
+ *label ? " " : "",
+ label);
+ } else {
+ snprintf(buf, bufsize, "sfpio");
+ }
- for (i = 0; i < count; i++) {
- debug("i=%d, upto=%d\n", i, upto);
- if (gpio < data->max_gpio) {
- struct s5p_gpio_bank *bank;
- bank = (struct s5p_gpio_bank *)data->reg_addr;
- bank += (gpio - upto) / GPIO_PER_BANK;
- debug("gpio=%d, bank=%p\n", gpio, bank);
- return bank;
- }
+ return 0;
+}
- upto = data->max_gpio;
- data++;
+static int check_reserved(struct udevice *dev, unsigned offset,
+ const char *func)
+{
+ struct exynos_bank_info *state = dev_get_priv(dev);
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+
+ if (!*state->label[offset]) {
+ printf("exynos_gpio: %s: error: gpio %s%d not reserved\n",
+ func, uc_priv->bank_name, offset);
+ return -EPERM;
}
- return NULL;
+ return 0;
}
-int s5p_gpio_get_pin(unsigned gpio)
+/* set GPIO pin 'gpio' as an input */
+static int exynos_gpio_direction_input(struct udevice *dev, unsigned offset)
{
- return S5P_GPIO_GET_PIN(gpio);
-}
+ struct exynos_bank_info *state = dev_get_priv(dev);
+ int ret;
-/* Common GPIO API */
+ ret = check_reserved(dev, offset, __func__);
+ if (ret)
+ return ret;
+
+ /* Configure GPIO direction as input. */
+ s5p_gpio_cfg_pin(state->bank, offset, S5P_GPIO_INPUT);
-int gpio_request(unsigned gpio, const char *label)
-{
return 0;
}
-int gpio_free(unsigned gpio)
+/* set GPIO pin 'gpio' as an output, with polarity 'value' */
+static int exynos_gpio_direction_output(struct udevice *dev, unsigned offset,
+ int value)
{
+ struct exynos_bank_info *state = dev_get_priv(dev);
+ int ret;
+
+ ret = check_reserved(dev, offset, __func__);
+ if (ret)
+ return ret;
+
+ /* Configure GPIO output value. */
+ s5p_gpio_set_value(state->bank, offset, value);
+
+ /* Configure GPIO direction as output. */
+ s5p_gpio_cfg_pin(state->bank, offset, S5P_GPIO_OUTPUT);
+
return 0;
}
-int gpio_direction_input(unsigned gpio)
+/* read GPIO IN value of pin 'gpio' */
+static int exynos_gpio_get_value(struct udevice *dev, unsigned offset)
{
- s5p_gpio_direction_input(s5p_gpio_get_bank(gpio),
- s5p_gpio_get_pin(gpio));
- return 0;
+ struct exynos_bank_info *state = dev_get_priv(dev);
+ int ret;
+
+ ret = check_reserved(dev, offset, __func__);
+ if (ret)
+ return ret;
+
+ return s5p_gpio_get_value(state->bank, offset);
}
-int gpio_direction_output(unsigned gpio, int value)
+/* write GPIO OUT value to pin 'gpio' */
+static int exynos_gpio_set_value(struct udevice *dev, unsigned offset,
+ int value)
{
- s5p_gpio_direction_output(s5p_gpio_get_bank(gpio),
- s5p_gpio_get_pin(gpio), value);
+ struct exynos_bank_info *state = dev_get_priv(dev);
+ int ret;
+
+ ret = check_reserved(dev, offset, __func__);
+ if (ret)
+ return ret;
+
+ s5p_gpio_set_value(state->bank, offset, value);
+
return 0;
}
-int gpio_get_value(unsigned gpio)
+static int exynos_gpio_request(struct udevice *dev, unsigned offset,
+ const char *label)
{
- return (int) s5p_gpio_get_value(s5p_gpio_get_bank(gpio),
- s5p_gpio_get_pin(gpio));
+ struct exynos_bank_info *state = dev_get_priv(dev);
+
+ if (*state->label[offset])
+ return -EBUSY;
+
+ strncpy(state->label[offset], label, GPIO_NAME_SIZE);
+ state->label[offset][GPIO_NAME_SIZE - 1] = '\0';
+
+ return 0;
}
-int gpio_set_value(unsigned gpio, int value)
+static int exynos_gpio_free(struct udevice *dev, unsigned offset)
{
- s5p_gpio_set_value(s5p_gpio_get_bank(gpio),
- s5p_gpio_get_pin(gpio), value);
+ struct exynos_bank_info *state = dev_get_priv(dev);
+ int ret;
+
+ ret = check_reserved(dev, offset, __func__);
+ if (ret)
+ return ret;
+ state->label[offset][0] = '\0';
return 0;
}
+#endif /* nCONFIG_SPL_BUILD */
+/*
+ * There is no common GPIO API for pull, drv, pin, rate (yet). These
+ * functions are kept here to preserve function ordering for review.
+ */
void gpio_set_pull(int gpio, int mode)
{
s5p_gpio_set_pull(s5p_gpio_get_bank(gpio),
@@ -317,3 +355,117 @@ void gpio_set_rate(int gpio, int mode)
s5p_gpio_set_rate(s5p_gpio_get_bank(gpio),
s5p_gpio_get_pin(gpio), mode);
}
+
+#ifndef CONFIG_SPL_BUILD
+static int exynos_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+ struct exynos_bank_info *state = dev_get_priv(dev);
+ int cfg;
+
+ if (!*state->label[offset])
+ return GPIOF_UNUSED;
+ cfg = s5p_gpio_get_cfg_pin(state->bank, offset);
+ if (cfg == S5P_GPIO_OUTPUT)
+ return GPIOF_OUTPUT;
+ else if (cfg == S5P_GPIO_INPUT)
+ return GPIOF_INPUT;
+ else
+ return GPIOF_FUNC;
+}
+
+static const struct dm_gpio_ops gpio_exynos_ops = {
+ .request = exynos_gpio_request,
+ .free = exynos_gpio_free,
+ .direction_input = exynos_gpio_direction_input,
+ .direction_output = exynos_gpio_direction_output,
+ .get_value = exynos_gpio_get_value,
+ .set_value = exynos_gpio_set_value,
+ .get_function = exynos_gpio_get_function,
+ .get_state = exynos_gpio_get_state,
+};
+
+static int gpio_exynos_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+ struct exynos_bank_info *priv = dev->priv;
+ struct exynos_gpio_platdata *plat = dev->platdata;
+
+ /* Only child devices have ports */
+ if (!plat)
+ return 0;
+
+ priv->bank = plat->bank;
+
+ uc_priv->gpio_count = GPIO_PER_BANK;
+ uc_priv->bank_name = plat->bank_name;
+
+ return 0;
+}
+
+/**
+ * We have a top-level GPIO device with no actual GPIOs. It has a child
+ * device for each Exynos GPIO bank.
+ */
+static int gpio_exynos_bind(struct udevice *parent)
+{
+ struct exynos_gpio_platdata *plat = parent->platdata;
+ struct s5p_gpio_bank *bank, *base;
+ const void *blob = gd->fdt_blob;
+ int node;
+
+ /* If this is a child device, there is nothing to do here */
+ if (plat)
+ return 0;
+
+ base = (struct s5p_gpio_bank *)fdtdec_get_addr(gd->fdt_blob,
+ parent->of_offset, "reg");
+ for (node = fdt_first_subnode(blob, parent->of_offset), bank = base;
+ node > 0;
+ node = fdt_next_subnode(blob, node), bank++) {
+ struct exynos_gpio_platdata *plat;
+ struct udevice *dev;
+ fdt_addr_t reg;
+ int ret;
+
+ if (!fdtdec_get_bool(blob, node, "gpio-controller"))
+ continue;
+ plat = calloc(1, sizeof(*plat));
+ if (!plat)
+ return -ENOMEM;
+ reg = fdtdec_get_addr(blob, node, "reg");
+ if (reg != FDT_ADDR_T_NONE)
+ bank = (struct s5p_gpio_bank *)((ulong)base + reg);
+ plat->bank = bank;
+ plat->bank_name = fdt_get_name(blob, node, NULL);
+ debug("dev at %p: %s\n", bank, plat->bank_name);
+
+ ret = device_bind(parent, parent->driver,
+ plat->bank_name, plat, -1, &dev);
+ if (ret)
+ return ret;
+ dev->of_offset = parent->of_offset;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id exynos_gpio_ids[] = {
+ { .compatible = "samsung,s5pc100-pinctrl" },
+ { .compatible = "samsung,s5pc110-pinctrl" },
+ { .compatible = "samsung,exynos4210-pinctrl" },
+ { .compatible = "samsung,exynos4x12-pinctrl" },
+ { .compatible = "samsung,exynos5250-pinctrl" },
+ { .compatible = "samsung,exynos5420-pinctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(gpio_exynos) = {
+ .name = "gpio_exynos",
+ .id = UCLASS_GPIO,
+ .of_match = exynos_gpio_ids,
+ .bind = gpio_exynos_bind,
+ .probe = gpio_exynos_probe,
+ .priv_auto_alloc_size = sizeof(struct exynos_bank_info),
+ .ops = &gpio_exynos_ops,
+};
+#endif
diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index 068373b..521edfd 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -16,6 +16,7 @@
#include <common.h>
#include <command.h>
+#include <dm.h>
#include <i2c.h>
#include <cros_ec.h>
#include <fdtdec.h>
@@ -24,6 +25,8 @@
#include <asm/errno.h>
#include <asm/io.h>
#include <asm-generic/gpio.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
#ifdef DEBUG_TRACE
#define debug_trace(fmt, b...) debug(fmt, #b)
@@ -38,7 +41,9 @@ enum {
CROS_EC_CMD_HASH_TIMEOUT_MS = 2000,
};
+#ifndef CONFIG_DM_CROS_EC
static struct cros_ec_dev static_dev, *last_dev;
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -204,6 +209,9 @@ static int send_command_proto3(struct cros_ec_dev *dev,
const void *dout, int dout_len,
uint8_t **dinp, int din_len)
{
+#ifdef CONFIG_DM_CROS_EC
+ struct dm_cros_ec_ops *ops;
+#endif
int out_bytes, in_bytes;
int rv;
@@ -218,6 +226,10 @@ static int send_command_proto3(struct cros_ec_dev *dev,
if (in_bytes < 0)
return in_bytes;
+#ifdef CONFIG_DM_CROS_EC
+ ops = dm_cros_ec_get_ops(dev->dev);
+ rv = ops->packet(dev->dev, out_bytes, in_bytes);
+#else
switch (dev->interface) {
#ifdef CONFIG_CROS_EC_SPI
case CROS_EC_IF_SPI:
@@ -235,6 +247,7 @@ static int send_command_proto3(struct cros_ec_dev *dev,
debug("%s: Unsupported interface\n", __func__);
rv = -1;
}
+#endif
if (rv < 0)
return rv;
@@ -246,6 +259,9 @@ static int send_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
const void *dout, int dout_len,
uint8_t **dinp, int din_len)
{
+#ifdef CONFIG_DM_CROS_EC
+ struct dm_cros_ec_ops *ops;
+#endif
int ret = -1;
/* Handle protocol version 3 support */
@@ -254,6 +270,11 @@ static int send_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
dout, dout_len, dinp, din_len);
}
+#ifdef CONFIG_DM_CROS_EC
+ ops = dm_cros_ec_get_ops(dev->dev);
+ ret = ops->command(dev->dev, cmd, cmd_version,
+ (const uint8_t *)dout, dout_len, dinp, din_len);
+#else
switch (dev->interface) {
#ifdef CONFIG_CROS_EC_SPI
case CROS_EC_IF_SPI:
@@ -280,6 +301,7 @@ static int send_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
default:
ret = -1;
}
+#endif
return ret;
}
@@ -990,6 +1012,7 @@ int cros_ec_get_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t *state)
return 0;
}
+#ifndef CONFIG_DM_CROS_EC
/**
* Decode EC interface details from the device tree and allocate a suitable
* device.
@@ -1055,11 +1078,61 @@ static int cros_ec_decode_fdt(const void *blob, int node,
return 0;
}
+#endif
-int cros_ec_init(const void *blob, struct cros_ec_dev **cros_ecp)
+#ifdef CONFIG_DM_CROS_EC
+int cros_ec_register(struct udevice *dev)
{
+ struct cros_ec_dev *cdev = dev->uclass_priv;
+ const void *blob = gd->fdt_blob;
+ int node = dev->of_offset;
char id[MSG_BYTES];
+
+ cdev->dev = dev;
+ fdtdec_decode_gpio(blob, node, "ec-interrupt", &cdev->ec_int);
+ cdev->optimise_flash_write = fdtdec_get_bool(blob, node,
+ "optimise-flash-write");
+
+ /* we will poll the EC interrupt line */
+ fdtdec_setup_gpio(&cdev->ec_int);
+ if (fdt_gpio_isvalid(&cdev->ec_int)) {
+ gpio_request(cdev->ec_int.gpio, "cros-ec-irq");
+ gpio_direction_input(cdev->ec_int.gpio);
+ }
+
+ if (cros_ec_check_version(cdev)) {
+ debug("%s: Could not detect CROS-EC version\n", __func__);
+ return -CROS_EC_ERR_CHECK_VERSION;
+ }
+
+ if (cros_ec_read_id(cdev, id, sizeof(id))) {
+ debug("%s: Could not read KBC ID\n", __func__);
+ return -CROS_EC_ERR_READ_ID;
+ }
+
+ /* Remember this device for use by the cros_ec command */
+ debug("Google Chrome EC CROS-EC driver ready, id '%s'\n", id);
+
+ return 0;
+}
+#else
+int cros_ec_init(const void *blob, struct cros_ec_dev **cros_ecp)
+{
struct cros_ec_dev *dev;
+ char id[MSG_BYTES];
+#ifdef CONFIG_DM_CROS_EC
+ struct udevice *udev;
+ int ret;
+
+ ret = uclass_find_device(UCLASS_CROS_EC, 0, &udev);
+ if (!ret)
+ device_remove(udev);
+ ret = uclass_get_device(UCLASS_CROS_EC, 0, &udev);
+ if (ret)
+ return ret;
+ dev = udev->uclass_priv;
+ return 0;
+#else
int node = 0;
*cros_ecp = NULL;
@@ -1108,11 +1181,14 @@ int cros_ec_init(const void *blob, struct cros_ec_dev **cros_ecp)
default:
return 0;
}
+#endif
/* we will poll the EC interrupt line */
fdtdec_setup_gpio(&dev->ec_int);
- if (fdt_gpio_isvalid(&dev->ec_int))
+ if (fdt_gpio_isvalid(&dev->ec_int)) {
+ gpio_request(dev->ec_int.gpio, "cros-ec-irq");
gpio_direction_input(dev->ec_int.gpio);
+ }
if (cros_ec_check_version(dev)) {
debug("%s: Could not detect CROS-EC version\n", __func__);
@@ -1125,11 +1201,15 @@ int cros_ec_init(const void *blob, struct cros_ec_dev **cros_ecp)
}
/* Remember this device for use by the cros_ec command */
- last_dev = *cros_ecp = dev;
+ *cros_ecp = dev;
+#ifndef CONFIG_DM_CROS_EC
+ last_dev = dev;
+#endif
debug("Google Chrome EC CROS-EC driver ready, id '%s'\n", id);
return 0;
}
+#endif
int cros_ec_decode_region(int argc, char * const argv[])
{
@@ -1147,15 +1227,10 @@ int cros_ec_decode_region(int argc, char * const argv[])
return -1;
}
-int cros_ec_decode_ec_flash(const void *blob, struct fdt_cros_ec *config)
+int cros_ec_decode_ec_flash(const void *blob, int node,
+ struct fdt_cros_ec *config)
{
- int flash_node, node;
-
- node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_CROS_EC);
- if (node < 0) {
- debug("Failed to find chrome-ec node'\n");
- return -1;
- }
+ int flash_node;
flash_node = fdt_subnode_offset(blob, node, "flash");
if (flash_node < 0) {
@@ -1516,7 +1591,10 @@ static int cros_ec_i2c_passthrough(struct cros_ec_dev *dev, int flag,
static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- struct cros_ec_dev *dev = last_dev;
+ struct cros_ec_dev *dev;
+#ifdef CONFIG_DM_CROS_EC
+ struct udevice *udev;
+#endif
const char *cmd;
int ret = 0;
@@ -1525,19 +1603,31 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
cmd = argv[1];
if (0 == strcmp("init", cmd)) {
+#ifndef CONFIG_DM_CROS_EC
ret = cros_ec_init(gd->fdt_blob, &dev);
if (ret) {
printf("Could not init cros_ec device (err %d)\n", ret);
return 1;
}
+#endif
return 0;
}
+#ifdef CONFIG_DM_CROS_EC
+ ret = uclass_get_device(UCLASS_CROS_EC, 0, &udev);
+ if (ret) {
+ printf("Cannot get cros-ec device (err=%d)\n", ret);
+ return 1;
+ }
+ dev = udev->uclass_priv;
+#else
/* Just use the last allocated device; there should be only one */
if (!last_dev) {
printf("No CROS-EC device available\n");
return 1;
}
+ dev = last_dev;
+#endif
if (0 == strcmp("id", cmd)) {
char id[MSG_BYTES];
@@ -1794,3 +1884,11 @@ U_BOOT_CMD(
"crosec i2c mw chip address[.0, .1, .2] value [count] - write to I2C passthru (fill)"
);
#endif
+
+#ifdef CONFIG_DM_CROS_EC
+UCLASS_DRIVER(cros_ec) = {
+ .id = UCLASS_CROS_EC,
+ .name = "cros_ec",
+ .per_device_auto_alloc_size = sizeof(struct cros_ec_dev),
+};
+#endif
diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c
index 8a04af5..99cc529 100644
--- a/drivers/misc/cros_ec_sandbox.c
+++ b/drivers/misc/cros_ec_sandbox.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <cros_ec.h>
+#include <dm.h>
#include <ec_commands.h>
#include <errno.h>
#include <hash.h>
@@ -85,7 +86,7 @@ struct ec_state {
struct ec_keymatrix_entry *matrix; /* the key matrix info */
uint8_t keyscan[KEYBOARD_COLS];
bool recovery_req;
-} s_state, *state;
+} s_state, *g_state;
/**
* cros_ec_read_state() - read the sandbox EC state from the state file
@@ -138,7 +139,7 @@ static int cros_ec_read_state(const void *blob, int node)
*/
static int cros_ec_write_state(void *blob, int node)
{
- struct ec_state *ec = &s_state;
+ struct ec_state *ec = g_state;
/* We are guaranteed enough space to write basic properties */
fdt_setprop_u32(blob, node, "current-image", ec->current_image);
@@ -369,7 +370,7 @@ static int process_cmd(struct ec_state *ec,
struct fmap_entry *entry;
int ret, size;
- entry = &state->ec_config.region[EC_FLASH_REGION_RW];
+ entry = &ec->ec_config.region[EC_FLASH_REGION_RW];
switch (req->cmd) {
case EC_VBOOT_HASH_RECALC:
@@ -426,7 +427,7 @@ static int process_cmd(struct ec_state *ec,
case EC_FLASH_REGION_RO:
case EC_FLASH_REGION_RW:
case EC_FLASH_REGION_WP_RO:
- entry = &state->ec_config.region[req->region];
+ entry = &ec->ec_config.region[req->region];
resp->offset = entry->offset;
resp->size = entry->length;
len = sizeof(*resp);
@@ -466,16 +467,24 @@ static int process_cmd(struct ec_state *ec,
return len;
}
+#ifdef CONFIG_DM_CROS_EC
+int cros_ec_sandbox_packet(struct udevice *udev, int out_bytes, int in_bytes)
+{
+ struct cros_ec_dev *dev = udev->uclass_priv;
+ struct ec_state *ec = dev_get_priv(dev->dev);
+#else
int cros_ec_sandbox_packet(struct cros_ec_dev *dev, int out_bytes,
int in_bytes)
{
+ struct ec_state *ec = &s_state;
+#endif
struct ec_host_request *req_hdr = (struct ec_host_request *)dev->dout;
const void *req_data = req_hdr + 1;
struct ec_host_response *resp_hdr = (struct ec_host_response *)dev->din;
void *resp_data = resp_hdr + 1;
int len;
- len = process_cmd(&s_state, req_hdr, req_data, resp_hdr, resp_data);
+ len = process_cmd(ec, req_hdr, req_data, resp_hdr, resp_data);
if (len < 0)
return len;
@@ -498,7 +507,11 @@ int cros_ec_sandbox_decode_fdt(struct cros_ec_dev *dev, const void *blob)
void cros_ec_check_keyboard(struct cros_ec_dev *dev)
{
+#ifdef CONFIG_DM_CROS_EC
+ struct ec_state *ec = dev_get_priv(dev->dev);
+#else
struct ec_state *ec = &s_state;
+#endif
ulong start;
printf("Press keys for EC to detect on reset (ESC=recovery)...");
@@ -512,6 +525,52 @@ void cros_ec_check_keyboard(struct cros_ec_dev *dev)
}
}
+#ifdef CONFIG_DM_CROS_EC
+int cros_ec_probe(struct udevice *dev)
+{
+ struct ec_state *ec = dev->priv;
+ struct cros_ec_dev *cdev = dev->uclass_priv;
+ const void *blob = gd->fdt_blob;
+ int node;
+ int err;
+
+ memcpy(ec, &s_state, sizeof(*ec));
+ err = cros_ec_decode_ec_flash(blob, dev->of_offset, &ec->ec_config);
+ if (err)
+ return err;
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_CROS_EC_KEYB);
+ if (node < 0) {
+ debug("%s: No cros_ec keyboard found\n", __func__);
+ } else if (keyscan_read_fdt_matrix(ec, blob, node)) {
+ debug("%s: Could not read key matrix\n", __func__);
+ return -1;
+ }
+
+ /* If we loaded EC data, check that the length matches */
+ if (ec->flash_data &&
+ ec->flash_data_len != ec->ec_config.flash.length) {
+ printf("EC data length is %x, expected %x, discarding data\n",
+ ec->flash_data_len, ec->ec_config.flash.length);
+ os_free(ec->flash_data);
+ ec->flash_data = NULL;
+ }
+
+ /* Otherwise allocate the memory */
+ if (!ec->flash_data) {
+ ec->flash_data_len = ec->ec_config.flash.length;
+ ec->flash_data = os_malloc(ec->flash_data_len);
+ if (!ec->flash_data)
+ return -ENOMEM;
+ }
+
+ cdev->dev = dev;
+ g_state = ec;
+ return cros_ec_register(dev);
+}
+
+#else
+
/**
* Initialize sandbox EC emulation.
*
@@ -525,8 +584,13 @@ int cros_ec_sandbox_init(struct cros_ec_dev *dev, const void *blob)
int node;
int err;
- state = &s_state;
- err = cros_ec_decode_ec_flash(blob, &ec->ec_config);
+ node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_CROS_EC);
+ if (node < 0) {
+ debug("Failed to find chrome-ec node'\n");
+ return -1;
+ }
+
+ err = cros_ec_decode_ec_flash(blob, node, &ec->ec_config);
if (err)
return err;
@@ -557,3 +621,24 @@ int cros_ec_sandbox_init(struct cros_ec_dev *dev, const void *blob)
return 0;
}
+#endif
+
+#ifdef CONFIG_DM_CROS_EC
+struct dm_cros_ec_ops cros_ec_ops = {
+ .packet = cros_ec_sandbox_packet,
+};
+
+static const struct udevice_id cros_ec_ids[] = {
+ { .compatible = "google,cros-ec" },
+ { }
+};
+
+U_BOOT_DRIVER(cros_ec_sandbox) = {
+ .name = "cros_ec",
+ .id = UCLASS_CROS_EC,
+ .of_match = cros_ec_ids,
+ .probe = cros_ec_probe,
+ .priv_auto_alloc_size = sizeof(struct ec_state),
+ .ops = &cros_ec_ops,
+};
+#endif
diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c
index 015333f..e403664 100644
--- a/drivers/misc/cros_ec_spi.c
+++ b/drivers/misc/cros_ec_spi.c
@@ -15,23 +15,34 @@
#include <common.h>
#include <cros_ec.h>
+#include <dm.h>
+#include <errno.h>
#include <spi.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DM_CROS_EC
+int cros_ec_spi_packet(struct udevice *udev, int out_bytes, int in_bytes)
+{
+ struct cros_ec_dev *dev = udev->uclass_priv;
+#else
int cros_ec_spi_packet(struct cros_ec_dev *dev, int out_bytes, int in_bytes)
{
+#endif
+ struct spi_slave *slave = dev_get_parentdata(dev->dev);
int rv;
/* Do the transfer */
- if (spi_claim_bus(dev->spi)) {
+ if (spi_claim_bus(slave)) {
debug("%s: Cannot claim SPI bus\n", __func__);
return -1;
}
- rv = spi_xfer(dev->spi, max(out_bytes, in_bytes) * 8,
+ rv = spi_xfer(slave, max(out_bytes, in_bytes) * 8,
dev->dout, dev->din,
SPI_XFER_BEGIN | SPI_XFER_END);
- spi_release_bus(dev->spi);
+ spi_release_bus(slave);
if (rv) {
debug("%s: Cannot complete SPI transfer\n", __func__);
@@ -56,10 +67,19 @@ int cros_ec_spi_packet(struct cros_ec_dev *dev, int out_bytes, int in_bytes)
* @param din_len Maximum size of response in bytes
* @return number of bytes in response, or -1 on error
*/
+#ifdef CONFIG_DM_CROS_EC
+int cros_ec_spi_command(struct udevice *udev, uint8_t cmd, int cmd_version,
+ const uint8_t *dout, int dout_len,
+ uint8_t **dinp, int din_len)
+{
+ struct cros_ec_dev *dev = udev->uclass_priv;
+#else
int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
const uint8_t *dout, int dout_len,
uint8_t **dinp, int din_len)
{
+#endif
+ struct spi_slave *slave = dev_get_parentdata(dev->dev);
int in_bytes = din_len + 4; /* status, length, checksum, trailer */
uint8_t *out;
uint8_t *p;
@@ -92,7 +112,7 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
*/
memset(dev->din, '\0', in_bytes);
- if (spi_claim_bus(dev->spi)) {
+ if (spi_claim_bus(slave)) {
debug("%s: Cannot claim SPI bus\n", __func__);
return -1;
}
@@ -113,10 +133,10 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
p = dev->din + sizeof(int64_t) - 2;
len = dout_len + 4;
cros_ec_dump_data("out", cmd, out, len);
- rv = spi_xfer(dev->spi, max(len, in_bytes) * 8, out, p,
+ rv = spi_xfer(slave, max(len, in_bytes) * 8, out, p,
SPI_XFER_BEGIN | SPI_XFER_END);
- spi_release_bus(dev->spi);
+ spi_release_bus(slave);
if (rv) {
debug("%s: Cannot complete SPI transfer\n", __func__);
@@ -146,6 +166,7 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
return len;
}
+#ifndef CONFIG_DM_CROS_EC
int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const void *blob)
{
/* Decode interface-specific FDT params */
@@ -165,11 +186,59 @@ int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const void *blob)
*/
int cros_ec_spi_init(struct cros_ec_dev *dev, const void *blob)
{
- dev->spi = spi_setup_slave_fdt(blob, dev->node, dev->parent_node);
- if (!dev->spi) {
+ int ret;
+
+ ret = spi_setup_slave_fdt(blob, dev->node, dev->parent_node,
+ &slave);
+ if (ret) {
debug("%s: Could not setup SPI slave\n", __func__);
- return -1;
+ return ret;
}
return 0;
}
+#endif
+
+#ifdef CONFIG_DM_CROS_EC
+int cros_ec_probe(struct udevice *dev)
+{
+ struct spi_slave *slave = dev_get_parentdata(dev);
+ int ret;
+
+ /*
+ * TODO(sjg@chromium.org)
+ *
+ * This is really horrible at present. It is an artifact of removing
+ * the child_pre_probe() method for SPI. Everything here could go in
+ * an automatic function, except that spi_get_bus_and_cs() wants to
+ * set it up manually and call device_probe_child().
+ *
+ * The solution may be to re-enable the child_pre_probe() method for
+ * SPI and have it do nothing if the child is already passed in via
+ * device_probe_child().
+ */
+ slave->dev = dev;
+ ret = spi_ofdata_to_platdata(gd->fdt_blob, dev->of_offset, slave);
+ if (ret)
+ return ret;
+ return cros_ec_register(dev);
+}
+
+struct dm_cros_ec_ops cros_ec_ops = {
+ .packet = cros_ec_spi_packet,
+ .command = cros_ec_spi_command,
+};
+
+static const struct udevice_id cros_ec_ids[] = {
+ { .compatible = "google,cros-ec" },
+ { }
+};
+
+U_BOOT_DRIVER(cros_ec_spi) = {
+ .name = "cros_ec",
+ .id = UCLASS_CROS_EC,
+ .of_match = cros_ec_ids,
+ .probe = cros_ec_probe,
+ .ops = &cros_ec_ops,
+};
+#endif
diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c
index 637dd97..0dea45d 100644
--- a/drivers/mmc/s5p_sdhci.c
+++ b/drivers/mmc/s5p_sdhci.c
@@ -102,6 +102,7 @@ struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS];
static int do_sdhci_init(struct sdhci_host *host)
{
+ char str[20];
int dev_id, flag;
int err = 0;
@@ -109,6 +110,8 @@ static int do_sdhci_init(struct sdhci_host *host)
dev_id = host->index + PERIPH_ID_SDMMC0;
if (fdt_gpio_isvalid(&host->pwr_gpio)) {
+ sprintf(str, "sdhci%d_power", host->index & 0xf);
+ gpio_request(host->pwr_gpio.gpio, str);
gpio_direction_output(host->pwr_gpio.gpio, 1);
err = exynos_pinmux_config(dev_id, flag);
if (err) {
@@ -118,7 +121,9 @@ static int do_sdhci_init(struct sdhci_host *host)
}
if (fdt_gpio_isvalid(&host->cd_gpio)) {
- gpio_direction_output(host->cd_gpio.gpio, 0xf);
+ sprintf(str, "sdhci%d_cd", host->index & 0xf);
+ gpio_request(host->cd_gpio.gpio, str);
+ gpio_direction_output(host->cd_gpio.gpio, 1);
if (gpio_get_value(host->cd_gpio.gpio))
return -ENODEV;
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 9e18fb4..15789a0 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -5,13 +5,18 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o
+
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_SPI_LOAD) += spi_spl_load.o
obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
endif
+#ifndef CONFIG_DM_SPI
+obj-$(CONFIG_SPI_FLASH) += sf_probe.o
+#endif
obj-$(CONFIG_CMD_SF) += sf.o
-obj-$(CONFIG_SPI_FLASH) += sf_params.o sf_probe.o sf_ops.o
+obj-$(CONFIG_SPI_FLASH) += sf_ops.o sf_params.o
obj-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
obj-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
diff --git a/drivers/mtd/spi/ramtron.c b/drivers/mtd/spi/ramtron.c
index d50da37..a23032c 100644
--- a/drivers/mtd/spi/ramtron.c
+++ b/drivers/mtd/spi/ramtron.c
@@ -35,6 +35,7 @@
#include <common.h>
#include <malloc.h>
+#include <spi.h>
#include <spi_flash.h>
#include "sf_internal.h"
diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index 98e0a34..1cf2f98 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -9,6 +9,7 @@
*/
#include <common.h>
+#include <dm.h>
#include <malloc.h>
#include <spi.h>
#include <os.h>
@@ -19,6 +20,11 @@
#include <asm/getopt.h>
#include <asm/spi.h>
#include <asm/state.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/uclass-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
/*
* The different states that our SPI flash transitions between.
@@ -34,12 +40,14 @@ enum sandbox_sf_state {
SF_ERASE, /* erase the flash */
SF_READ_STATUS, /* read the flash's status register */
SF_READ_STATUS1, /* read the flash's status register upper 8 bits*/
+ SF_WRITE_STATUS, /* write the flash's status register */
};
static const char *sandbox_sf_state_name(enum sandbox_sf_state state)
{
static const char * const states[] = {
"CMD", "ID", "ADDR", "READ", "WRITE", "ERASE", "READ_STATUS",
+ "READ_STATUS1", "WRITE_STATUS",
};
return states[state];
}
@@ -58,6 +66,7 @@ static u8 sandbox_sf_0xff[0x1000];
/* Internal state data for each SPI flash */
struct sandbox_spi_flash {
+ unsigned int cs; /* Chip select we are attached to */
/*
* As we receive data over the SPI bus, our flash transitions
* between states. For example, we start off in the SF_CMD
@@ -84,71 +93,124 @@ struct sandbox_spi_flash {
int fd;
};
-static int sandbox_sf_setup(void **priv, const char *spec)
+struct sandbox_spi_flash_plat_data {
+ const char *filename;
+ const char *device_name;
+ int bus;
+ int cs;
+};
+
+/**
+ * This is a very strange probe function. If it has platform data (which may
+ * have come from the device tree) then this function gets the filename and
+ * device type from there. Failing that it looks at the command line
+ * parameter.
+ */
+static int sandbox_sf_probe(struct udevice *dev)
{
/* spec = idcode:file */
- struct sandbox_spi_flash *sbsf;
+ struct sandbox_spi_flash *sbsf = dev_get_priv(dev);
const char *file;
size_t len, idname_len;
const struct spi_flash_params *data;
-
- file = strchr(spec, ':');
- if (!file) {
- printf("sandbox_sf: unable to parse file\n");
- goto error;
+ struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev);
+ struct sandbox_state *state = state_get_current();
+ struct udevice *bus = dev->parent;
+ const char *spec = NULL;
+ int ret = 0;
+ int cs = -1;
+ int i;
+
+ debug("%s: bus %d, looking for emul=%p: ", __func__, bus->seq, dev);
+ if (bus->seq >= 0 && bus->seq < CONFIG_SANDBOX_SPI_MAX_BUS) {
+ for (i = 0; i < CONFIG_SANDBOX_SPI_MAX_CS; i++) {
+ if (state->spi[bus->seq][i].emul == dev)
+ cs = i;
+ }
+ }
+ if (cs == -1) {
+ printf("Error: Unknown chip select for device '%s'",
+ dev->name);
+ return -EINVAL;
+ }
+ debug("found at cs %d\n", cs);
+
+ if (!pdata->filename) {
+ struct sandbox_state *state = state_get_current();
+
+ assert(bus->seq != -1);
+ if (bus->seq < CONFIG_SANDBOX_SPI_MAX_BUS)
+ spec = state->spi[bus->seq][cs].spec;
+ if (!spec)
+ return -ENOENT;
+
+ file = strchr(spec, ':');
+ if (!file) {
+ printf("sandbox_sf: unable to parse file\n");
+ ret = -EINVAL;
+ goto error;
+ }
+ idname_len = file - spec;
+ pdata->filename = file + 1;
+ pdata->device_name = spec;
+ ++file;
+ } else {
+ spec = strchr(pdata->device_name, ',');
+ if (spec)
+ spec++;
+ else
+ spec = pdata->device_name;
+ idname_len = strlen(spec);
}
- idname_len = file - spec;
- ++file;
+ debug("%s: device='%s'\n", __func__, spec);
for (data = spi_flash_params_table; data->name; data++) {
len = strlen(data->name);
if (idname_len != len)
continue;
- if (!memcmp(spec, data->name, len))
+ if (!strncasecmp(spec, data->name, len))
break;
}
if (!data->name) {
printf("sandbox_sf: unknown flash '%*s'\n", (int)idname_len,
spec);
+ ret = -EINVAL;
goto error;
}
if (sandbox_sf_0xff[0] == 0x00)
memset(sandbox_sf_0xff, 0xff, sizeof(sandbox_sf_0xff));
- sbsf = calloc(sizeof(*sbsf), 1);
- if (!sbsf) {
- printf("sandbox_sf: out of memory\n");
- goto error;
- }
-
- sbsf->fd = os_open(file, 02);
+ sbsf->fd = os_open(pdata->filename, 02);
if (sbsf->fd == -1) {
free(sbsf);
- printf("sandbox_sf: unable to open file '%s'\n", file);
+ printf("sandbox_sf: unable to open file '%s'\n",
+ pdata->filename);
+ ret = -EIO;
goto error;
}
sbsf->data = data;
+ sbsf->cs = cs;
- *priv = sbsf;
return 0;
error:
- return 1;
+ return ret;
}
-static void sandbox_sf_free(void *priv)
+static int sandbox_sf_remove(struct udevice *dev)
{
- struct sandbox_spi_flash *sbsf = priv;
+ struct sandbox_spi_flash *sbsf = dev_get_priv(dev);
os_close(sbsf->fd);
- free(sbsf);
+
+ return 0;
}
-static void sandbox_sf_cs_activate(void *priv)
+static void sandbox_sf_cs_activate(struct udevice *dev)
{
- struct sandbox_spi_flash *sbsf = priv;
+ struct sandbox_spi_flash *sbsf = dev_get_priv(dev);
debug("sandbox_sf: CS activated; state is fresh!\n");
@@ -160,11 +222,24 @@ static void sandbox_sf_cs_activate(void *priv)
sbsf->cmd = SF_CMD;
}
-static void sandbox_sf_cs_deactivate(void *priv)
+static void sandbox_sf_cs_deactivate(struct udevice *dev)
{
debug("sandbox_sf: CS deactivated; cmd done processing!\n");
}
+/*
+ * There are times when the data lines are allowed to tristate. What
+ * is actually sensed on the line depends on the hardware. It could
+ * always be 0xFF/0x00 (if there are pull ups/downs), or things could
+ * float and so we'd get garbage back. This func encapsulates that
+ * scenario so we can worry about the details here.
+ */
+static void sandbox_spi_tristate(u8 *buf, uint len)
+{
+ /* XXX: make this into a user config option ? */
+ memset(buf, 0xff, len);
+}
+
/* Figure out what command this stream is telling us to do */
static int sandbox_sf_process_cmd(struct sandbox_spi_flash *sbsf, const u8 *rx,
u8 *tx)
@@ -172,7 +247,8 @@ static int sandbox_sf_process_cmd(struct sandbox_spi_flash *sbsf, const u8 *rx,
enum sandbox_sf_state oldstate = sbsf->state;
/* We need to output a byte for the cmd byte we just ate */
- sandbox_spi_tristate(tx, 1);
+ if (tx)
+ sandbox_spi_tristate(tx, 1);
sbsf->cmd = rx[0];
switch (sbsf->cmd) {
@@ -200,6 +276,9 @@ static int sandbox_sf_process_cmd(struct sandbox_spi_flash *sbsf, const u8 *rx,
debug(" write enabled\n");
sbsf->status |= STAT_WEL;
break;
+ case CMD_WRITE_STATUS:
+ sbsf->state = SF_WRITE_STATUS;
+ break;
default: {
int flags = sbsf->data->flags;
@@ -216,7 +295,7 @@ static int sandbox_sf_process_cmd(struct sandbox_spi_flash *sbsf, const u8 *rx,
sbsf->erase_size = 64 << 10;
} else {
debug(" cmd unknown: %#x\n", sbsf->cmd);
- return 1;
+ return -EIO;
}
sbsf->state = SF_ADDR;
break;
@@ -246,20 +325,27 @@ int sandbox_erase_part(struct sandbox_spi_flash *sbsf, int size)
return 0;
}
-static int sandbox_sf_xfer(void *priv, const u8 *rx, u8 *tx,
- uint bytes)
+static int sandbox_sf_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *rxp, void *txp, unsigned long flags)
{
- struct sandbox_spi_flash *sbsf = priv;
+ struct sandbox_spi_flash *sbsf = dev_get_priv(dev);
+ const uint8_t *rx = rxp;
+ uint8_t *tx = txp;
uint cnt, pos = 0;
+ int bytes = bitlen / 8;
int ret;
debug("sandbox_sf: state:%x(%s) bytes:%u\n", sbsf->state,
sandbox_sf_state_name(sbsf->state), bytes);
+ if ((flags & SPI_XFER_BEGIN))
+ sandbox_sf_cs_activate(dev);
+
if (sbsf->state == SF_CMD) {
/* Figure out the initial state */
- if (sandbox_sf_process_cmd(sbsf, rx, tx))
- return 1;
+ ret = sandbox_sf_process_cmd(sbsf, rx, tx);
+ if (ret)
+ return ret;
++pos;
}
@@ -290,7 +376,9 @@ static int sandbox_sf_xfer(void *priv, const u8 *rx, u8 *tx,
sbsf->off = (sbsf->off << 8) | rx[pos];
debug("addr:%06x\n", sbsf->off);
- sandbox_spi_tristate(&tx[pos++], 1);
+ if (tx)
+ sandbox_spi_tristate(&tx[pos], 1);
+ pos++;
/* See if we're done processing */
if (sbsf->addr_bytes <
@@ -300,7 +388,7 @@ static int sandbox_sf_xfer(void *priv, const u8 *rx, u8 *tx,
/* Next state! */
if (os_lseek(sbsf->fd, sbsf->off, OS_SEEK_SET) < 0) {
puts("sandbox_sf: os_lseek() failed");
- return 1;
+ return -EIO;
}
switch (sbsf->cmd) {
case CMD_READ_ARRAY_FAST:
@@ -326,10 +414,11 @@ static int sandbox_sf_xfer(void *priv, const u8 *rx, u8 *tx,
cnt = bytes - pos;
debug(" tx: read(%u)\n", cnt);
+ assert(tx);
ret = os_read(sbsf->fd, tx + pos, cnt);
if (ret < 0) {
- puts("sandbox_spi: os_read() failed\n");
- return 1;
+ puts("sandbox_sf: os_read() failed\n");
+ return -EIO;
}
pos += ret;
break;
@@ -345,6 +434,10 @@ static int sandbox_sf_xfer(void *priv, const u8 *rx, u8 *tx,
memset(tx + pos, sbsf->status >> 8, cnt);
pos += cnt;
break;
+ case SF_WRITE_STATUS:
+ debug(" write status: %#x (ignored)\n", rx[pos]);
+ pos = bytes;
+ break;
case SF_WRITE:
/*
* XXX: need to handle exotic behavior:
@@ -359,11 +452,12 @@ static int sandbox_sf_xfer(void *priv, const u8 *rx, u8 *tx,
cnt = bytes - pos;
debug(" rx: write(%u)\n", cnt);
- sandbox_spi_tristate(&tx[pos], cnt);
+ if (tx)
+ sandbox_spi_tristate(&tx[pos], cnt);
ret = os_write(sbsf->fd, rx + pos, cnt);
if (ret < 0) {
puts("sandbox_spi: os_write() failed\n");
- return 1;
+ return -EIO;
}
pos += ret;
sbsf->status &= ~STAT_WEL;
@@ -388,7 +482,8 @@ static int sandbox_sf_xfer(void *priv, const u8 *rx, u8 *tx,
sbsf->erase_size);
cnt = bytes - pos;
- sandbox_spi_tristate(&tx[pos], cnt);
+ if (tx)
+ sandbox_spi_tristate(&tx[pos], cnt);
pos += cnt;
/*
@@ -410,17 +505,33 @@ static int sandbox_sf_xfer(void *priv, const u8 *rx, u8 *tx,
}
done:
- return pos == bytes ? 0 : 1;
+ if (flags & SPI_XFER_END)
+ sandbox_sf_cs_deactivate(dev);
+ return pos == bytes ? 0 : -EIO;
+}
+
+int sandbox_sf_ofdata_to_platdata(struct udevice *dev)
+{
+ struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev);
+ const void *blob = gd->fdt_blob;
+ int node = dev->of_offset;
+
+ pdata->filename = fdt_getprop(blob, node, "sandbox,filename", NULL);
+ pdata->device_name = fdt_getprop(blob, node, "compatible", NULL);
+ if (!pdata->filename || !pdata->device_name) {
+ debug("%s: Missing properties, filename=%s, device_name=%s\n",
+ __func__, pdata->filename, pdata->device_name);
+ return -EINVAL;
+ }
+
+ return 0;
}
-static const struct sandbox_spi_emu_ops sandbox_sf_ops = {
- .setup = sandbox_sf_setup,
- .free = sandbox_sf_free,
- .cs_activate = sandbox_sf_cs_activate,
- .cs_deactivate = sandbox_sf_cs_deactivate,
+static const struct dm_spi_emul_ops sandbox_sf_emul_ops = {
.xfer = sandbox_sf_xfer,
};
+#ifdef CONFIG_SPI_FLASH
static int sandbox_cmdline_cb_spi_sf(struct sandbox_state *state,
const char *arg)
{
@@ -438,8 +549,141 @@ static int sandbox_cmdline_cb_spi_sf(struct sandbox_state *state,
* spec here, but the problem is that no U-Boot init has been done
* yet. Perhaps we can figure something out.
*/
- state->spi[bus][cs].ops = &sandbox_sf_ops;
state->spi[bus][cs].spec = spec;
return 0;
}
SANDBOX_CMDLINE_OPT(spi_sf, 1, "connect a SPI flash: <bus>:<cs>:<id>:<file>");
+
+int sandbox_sf_bind_emul(struct sandbox_state *state, int busnum, int cs,
+ struct udevice *bus, int of_offset, const char *spec)
+{
+ struct udevice *emul;
+ char name[20], *str;
+ struct driver *drv;
+ int ret;
+
+ /* now the emulator */
+ strncpy(name, spec, sizeof(name) - 6);
+ name[sizeof(name) - 6] = '\0';
+ strcat(name, "-emul");
+ str = strdup(name);
+ if (!str)
+ return -ENOMEM;
+ drv = lists_driver_lookup_name("sandbox_sf_emul");
+ if (!drv) {
+ puts("Cannot find sandbox_sf_emul driver\n");
+ return -ENOENT;
+ }
+ ret = device_bind(bus, drv, str, NULL, of_offset, &emul);
+ if (ret) {
+ printf("Cannot create emul device for spec '%s' (err=%d)\n",
+ spec, ret);
+ return ret;
+ }
+ state->spi[busnum][cs].emul = emul;
+
+ return 0;
+}
+
+void sandbox_sf_unbind_emul(struct sandbox_state *state, int busnum, int cs)
+{
+ state->spi[busnum][cs].emul = NULL;
+}
+
+static int sandbox_sf_bind_bus_cs(struct sandbox_state *state, int busnum,
+ int cs, const char *spec)
+{
+ struct udevice *bus, *slave;
+ int ret;
+
+ ret = uclass_find_device_by_seq(UCLASS_SPI, busnum, true, &bus);
+ if (ret) {
+ printf("Invalid bus %d for spec '%s' (err=%d)\n", busnum,
+ spec, ret);
+ return ret;
+ }
+ ret = device_find_child_by_seq(bus, cs, true, &slave);
+ if (!ret) {
+ printf("Chip select %d already exists for spec '%s'\n", cs,
+ spec);
+ return -EEXIST;
+ }
+
+ ret = spi_bind_device(bus, cs, "spi_flash_std", spec, &slave);
+ if (ret)
+ return ret;
+
+ return sandbox_sf_bind_emul(state, busnum, cs, bus, -1, spec);
+}
+
+int sandbox_spi_get_emul(struct sandbox_state *state,
+ struct udevice *bus, struct udevice *slave,
+ struct udevice **emulp)
+{
+ struct sandbox_spi_info *info;
+ int busnum = bus->seq;
+ int cs = spi_chip_select(slave);
+ int ret;
+
+ info = &state->spi[busnum][cs];
+ if (!info->emul) {
+ /* Use the same device tree node as the SPI flash device */
+ debug("%s: busnum=%u, cs=%u: binding SPI flash emulation: ",
+ __func__, busnum, cs);
+ ret = sandbox_sf_bind_emul(state, busnum, cs, bus,
+ slave->of_offset, slave->name);
+ if (ret) {
+ debug("failed (err=%d)\n", ret);
+ return ret;
+ }
+ debug("OK\n");
+ }
+ *emulp = info->emul;
+
+ return 0;
+}
+
+int dm_scan_other(bool pre_reloc_only)
+{
+ struct sandbox_state *state = state_get_current();
+ int busnum, cs;
+
+ if (pre_reloc_only)
+ return 0;
+ for (busnum = 0; busnum < CONFIG_SANDBOX_SPI_MAX_BUS; busnum++) {
+ for (cs = 0; cs < CONFIG_SANDBOX_SPI_MAX_CS; cs++) {
+ const char *spec = state->spi[busnum][cs].spec;
+ int ret;
+
+ if (spec) {
+ ret = sandbox_sf_bind_bus_cs(state, busnum,
+ cs, spec);
+ if (ret) {
+ debug("%s: Bind failed for bus %d, cs %d\n",
+ __func__, busnum, cs);
+ return ret;
+ }
+ }
+ }
+ }
+
+ return 0;
+}
+#endif
+
+static const struct udevice_id sandbox_sf_ids[] = {
+ { .compatible = "sandbox,spi-flash" },
+ { }
+};
+
+U_BOOT_DRIVER(sandbox_sf_emul) = {
+ .name = "sandbox_sf_emul",
+ .id = UCLASS_SPI_EMUL,
+ .of_match = sandbox_sf_ids,
+ .ofdata_to_platdata = sandbox_sf_ofdata_to_platdata,
+ .probe = sandbox_sf_probe,
+ .remove = sandbox_sf_remove,
+ .priv_auto_alloc_size = sizeof(struct sandbox_spi_flash),
+ .platdata_auto_alloc_size = sizeof(struct sandbox_spi_flash_plat_data),
+ .ops = &sandbox_sf_emul_ops,
+};
diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c
new file mode 100644
index 0000000..376d815
--- /dev/null
+++ b/drivers/mtd/spi/sf-uclass.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <dm/device-internal.h>
+#include "sf_internal.h"
+
+/*
+ * TODO(sjg@chromium.org): This is an old-style function. We should remove
+ * it when all SPI flash drivers use dm
+ */
+struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode)
+{
+ struct udevice *dev;
+
+ if (spi_flash_probe_bus_cs(bus, cs, max_hz, spi_mode, &dev))
+ return NULL;
+
+ return dev->uclass_priv;
+}
+
+void spi_flash_free(struct spi_flash *flash)
+{
+ spi_flash_remove(flash->spi->dev);
+}
+
+int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs,
+ unsigned int max_hz, unsigned int spi_mode,
+ struct udevice **devp)
+{
+ struct spi_slave *slave;
+ struct udevice *bus;
+ char name[20], *str;
+ int ret;
+
+ snprintf(name, sizeof(name), "%d:%d", busnum, cs);
+ str = strdup(name);
+ ret = spi_get_bus_and_cs(busnum, cs, max_hz, spi_mode,
+ "spi_flash_std", str, &bus, &slave);
+ if (ret)
+ return ret;
+
+ *devp = slave->dev;
+ return 0;
+}
+
+int spi_flash_remove(struct udevice *dev)
+{
+ return device_remove(dev);
+}
+
+UCLASS_DRIVER(spi_flash) = {
+ .id = UCLASS_SPI_FLASH,
+ .name = "spi_flash",
+ .per_device_auto_alloc_size = sizeof(struct spi_flash),
+};
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 19d4914..5b7670c 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -10,6 +10,36 @@
#ifndef _SF_INTERNAL_H_
#define _SF_INTERNAL_H_
+#include <linux/types.h>
+#include <linux/compiler.h>
+
+/* Dual SPI flash memories - see SPI_COMM_DUAL_... */
+enum spi_dual_flash {
+ SF_SINGLE_FLASH = 0,
+ SF_DUAL_STACKED_FLASH = 1 << 0,
+ SF_DUAL_PARALLEL_FLASH = 1 << 1,
+};
+
+/* Enum list - Full read commands */
+enum spi_read_cmds {
+ ARRAY_SLOW = 1 << 0,
+ DUAL_OUTPUT_FAST = 1 << 1,
+ DUAL_IO_FAST = 1 << 2,
+ QUAD_OUTPUT_FAST = 1 << 3,
+ QUAD_IO_FAST = 1 << 4,
+};
+
+#define RD_EXTN (ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
+#define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
+
+/* sf param flags */
+enum {
+ SECT_4K = 1 << 0,
+ SECT_32K = 1 << 1,
+ E_FSR = 1 << 2,
+ WR_QPP = 1 << 3,
+};
+
#define SPI_FLASH_3B_ADDR_LEN 3
#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
#define SPI_FLASH_16MB_BOUN 0x1000000
@@ -30,12 +60,12 @@
#define CMD_WRITE_STATUS 0x01
#define CMD_PAGE_PROGRAM 0x02
#define CMD_WRITE_DISABLE 0x04
-#define CMD_READ_STATUS 0x05
+#define CMD_READ_STATUS 0x05
#define CMD_QUAD_PAGE_PROGRAM 0x32
#define CMD_READ_STATUS1 0x35
#define CMD_WRITE_ENABLE 0x06
-#define CMD_READ_CONFIG 0x35
-#define CMD_FLAG_STATUS 0x70
+#define CMD_READ_CONFIG 0x35
+#define CMD_FLAG_STATUS 0x70
/* Read commands */
#define CMD_READ_ARRAY_SLOW 0x03
@@ -57,7 +87,7 @@
/* Common status */
#define STATUS_WIP (1 << 0)
#define STATUS_QEB_WINSPAN (1 << 1)
-#define STATUS_QEB_MXIC (1 << 6)
+#define STATUS_QEB_MXIC (1 << 6)
#define STATUS_PEC (1 << 7)
#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
@@ -66,19 +96,42 @@
/* Flash timeout values */
#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
-#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
+#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
/* SST specific */
#ifdef CONFIG_SPI_FLASH_SST
-# define SST_WP 0x01 /* Supports AAI word program */
+# define SST_WP 0x01 /* Supports AAI word program */
# define CMD_SST_BP 0x02 /* Byte Program */
-# define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
+# define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
const void *buf);
#endif
+/**
+ * struct spi_flash_params - SPI/QSPI flash device params structure
+ *
+ * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
+ * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
+ * @ext_jedec: Device ext_jedec ID
+ * @sector_size: Sector size of this device
+ * @nr_sectors: No.of sectors on this device
+ * @e_rd_cmd: Enum list for read commands
+ * @flags: Important param, for flash specific behaviour
+ */
+struct spi_flash_params {
+ const char *name;
+ u32 jedec;
+ u16 ext_jedec;
+ u32 sector_size;
+ u32 nr_sectors;
+ u8 e_rd_cmd;
+ u16 flags;
+};
+
+extern const struct spi_flash_params spi_flash_params_table[];
+
/* Send a single-byte command to the device and read the response */
int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 453edf0..61545ca 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <spi.h>
#include <spi_flash.h>
#include "sf_internal.h"
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 4d148d1..2636426 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -9,6 +9,8 @@
*/
#include <common.h>
+#include <dm.h>
+#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
#include <spi.h>
@@ -95,15 +97,15 @@ static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
}
}
-static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
- u8 *idcode)
+static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode,
+ struct spi_flash *flash)
{
const struct spi_flash_params *params;
- struct spi_flash *flash;
u8 cmd;
u16 jedec = idcode[1] << 8 | idcode[2];
u16 ext_jedec = idcode[3] << 8 | idcode[4];
+ /* Validate params from spi_flash_params table */
params = spi_flash_params_table;
for (; params->name != NULL; params++) {
if ((params->jedec >> 16) == idcode[0]) {
@@ -120,13 +122,7 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
printf("SF: Unsupported flash IDs: ");
printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
idcode[0], jedec, ext_jedec);
- return NULL;
- }
-
- flash = calloc(1, sizeof(*flash));
- if (!flash) {
- debug("SF: Failed to allocate spi_flash\n");
- return NULL;
+ return -EPROTONOSUPPORT;
}
/* Assign spi data */
@@ -136,13 +132,15 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
flash->dual_flash = flash->spi->option;
/* Assign spi_flash ops */
+#ifndef CONFIG_DM_SPI_FLASH
flash->write = spi_flash_cmd_write_ops;
-#ifdef CONFIG_SPI_FLASH_SST
+#if defined(CONFIG_SPI_FLASH_SST)
if (params->flags & SST_WP)
flash->write = sst_write_wp;
#endif
flash->erase = spi_flash_cmd_erase_ops;
flash->read = spi_flash_cmd_read_ops;
+#endif
/* Compute the flash size */
flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
@@ -227,15 +225,18 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
#ifdef CONFIG_SPI_FLASH_BAR
u8 curr_bank = 0;
if (flash->size > SPI_FLASH_16MB_BOUN) {
+ int ret;
+
flash->bank_read_cmd = (idcode[0] == 0x01) ?
CMD_BANKADDR_BRRD : CMD_EXTNADDR_RDEAR;
flash->bank_write_cmd = (idcode[0] == 0x01) ?
CMD_BANKADDR_BRWR : CMD_EXTNADDR_WREAR;
- if (spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
- &curr_bank, 1)) {
+ ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
+ &curr_bank, 1);
+ if (ret) {
debug("SF: fail to read bank addr register\n");
- return NULL;
+ return ret;
}
flash->bank_curr = curr_bank;
} else {
@@ -250,7 +251,7 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
spi_flash_cmd_write_status(flash, 0);
#endif
- return flash;
+ return 0;
}
#ifdef CONFIG_OF_CONTROL
@@ -309,23 +310,29 @@ static int spi_enable_wp_pin(struct spi_flash *flash)
}
#endif
-static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi)
+/**
+ * spi_flash_probe_slave() - Probe for a SPI flash device on a bus
+ *
+ * @spi: Bus to probe
+ * @flashp: Pointer to place to put flash info, which may be NULL if the
+ * space should be allocated
+ */
+int spi_flash_probe_slave(struct spi_slave *spi, struct spi_flash *flash)
{
- struct spi_flash *flash = NULL;
u8 idcode[5];
int ret;
/* Setup spi_slave */
if (!spi) {
printf("SF: Failed to set up slave\n");
- return NULL;
+ return -ENODEV;
}
/* Claim spi bus */
ret = spi_claim_bus(spi);
if (ret) {
debug("SF: Failed to claim SPI bus: %d\n", ret);
- goto err_claim_bus;
+ return ret;
}
/* Read the ID codes */
@@ -340,10 +347,10 @@ static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi)
print_buffer(0, idcode, 1, sizeof(idcode), 0);
#endif
- /* Validate params from spi_flash_params table */
- flash = spi_flash_validate_params(spi, idcode);
- if (!flash)
+ if (spi_flash_validate_params(spi, idcode, flash)) {
+ ret = -EINVAL;
goto err_read_id;
+ }
/* Set the quad enable bit - only for quad commands */
if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
@@ -351,13 +358,15 @@ static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi)
(flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
if (spi_flash_set_qeb(flash, idcode[0])) {
debug("SF: Fail to set QEB for %02x\n", idcode[0]);
- return NULL;
+ ret = -EINVAL;
+ goto err_read_id;
}
}
#ifdef CONFIG_OF_CONTROL
if (spi_flash_decode_fdt(gd->fdt_blob, flash)) {
debug("SF: FDT decode error\n");
+ ret = -EINVAL;
goto err_read_id;
}
#endif
@@ -385,32 +394,51 @@ static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi)
/* Release spi bus */
spi_release_bus(spi);
- return flash;
+ return 0;
err_read_id:
spi_release_bus(spi);
-err_claim_bus:
- spi_free_slave(spi);
- return NULL;
+ return ret;
}
-struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+#ifndef CONFIG_DM_SPI_FLASH
+struct spi_flash *spi_flash_probe_tail(struct spi_slave *bus)
+{
+ struct spi_flash *flash;
+
+ /* Allocate space if needed (not used by sf-uclass */
+ flash = calloc(1, sizeof(*flash));
+ if (!flash) {
+ debug("SF: Failed to allocate spi_flash\n");
+ return NULL;
+ }
+
+ if (spi_flash_probe_slave(bus, flash)) {
+ spi_free_slave(bus);
+ free(flash);
+ return NULL;
+ }
+
+ return flash;
+}
+
+struct spi_flash *spi_flash_probe(unsigned int busnum, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode)
{
- struct spi_slave *spi;
+ struct spi_slave *bus;
- spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
- return spi_flash_probe_slave(spi);
+ bus = spi_setup_slave(busnum, cs, max_hz, spi_mode);
+ return spi_flash_probe_tail(bus);
}
#ifdef CONFIG_OF_SPI_FLASH
struct spi_flash *spi_flash_probe_fdt(const void *blob, int slave_node,
int spi_node)
{
- struct spi_slave *spi;
+ struct spi_slave *bus;
- spi = spi_setup_slave_fdt(blob, slave_node, spi_node);
- return spi_flash_probe_slave(spi);
+ bus = spi_setup_slave_fdt(blob, slave_node, spi_node);
+ return spi_flash_probe_tail(bus);
}
#endif
@@ -419,3 +447,61 @@ void spi_flash_free(struct spi_flash *flash)
spi_free_slave(flash->spi);
free(flash);
}
+
+#else /* defined CONFIG_DM_SPI_FLASH */
+
+static int spi_flash_std_read(struct udevice *dev, u32 offset, size_t len,
+ void *buf)
+{
+ struct spi_flash *flash = dev->uclass_priv;
+
+ return spi_flash_cmd_read_ops(flash, offset, len, buf);
+}
+
+int spi_flash_std_write(struct udevice *dev, u32 offset, size_t len,
+ const void *buf)
+{
+ struct spi_flash *flash = dev->uclass_priv;
+
+ return spi_flash_cmd_write_ops(flash, offset, len, buf);
+}
+
+int spi_flash_std_erase(struct udevice *dev, u32 offset, size_t len)
+{
+ struct spi_flash *flash = dev->uclass_priv;
+
+ return spi_flash_cmd_erase_ops(flash, offset, len);
+}
+
+int spi_flash_std_probe(struct udevice *dev)
+{
+ struct spi_slave *slave = dev_get_parentdata(dev);
+ struct spi_flash *flash;
+
+ flash = dev->uclass_priv;
+ flash->dev = dev;
+ debug("%s: slave=%p, cs=%d\n", __func__, slave, slave->cs);
+ return spi_flash_probe_slave(slave, flash);
+}
+
+static const struct dm_spi_flash_ops spi_flash_std_ops = {
+ .read = spi_flash_std_read,
+ .write = spi_flash_std_write,
+ .erase = spi_flash_std_erase,
+};
+
+static const struct udevice_id spi_flash_std_ids[] = {
+ { .compatible = "spi-flash" },
+ { }
+};
+
+U_BOOT_DRIVER(spi_flash_std) = {
+ .name = "spi_flash_std",
+ .id = UCLASS_SPI_FLASH,
+ .of_match = spi_flash_std_ids,
+ .probe = spi_flash_std_probe,
+ .priv_auto_alloc_size = sizeof(struct spi_flash),
+ .ops = &spi_flash_std_ops,
+};
+
+#endif /* CONFIG_DM_SPI_FLASH */
diff --git a/drivers/mtd/spi/spi_spl_load.c b/drivers/mtd/spi/spi_spl_load.c
index 59cca0f..2e0c871 100644
--- a/drivers/mtd/spi/spi_spl_load.c
+++ b/drivers/mtd/spi/spi_spl_load.c
@@ -10,6 +10,7 @@
*/
#include <common.h>
+#include <spi.h>
#include <spi_flash.h>
#include <spl.h>
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index b4f299b..17c56ea 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -7,8 +7,11 @@
ifdef CONFIG_DM_SERIAL
obj-y += serial-uclass.o
+obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o
else
obj-y += serial.o
+obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
+obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o
endif
@@ -25,8 +28,6 @@ obj-$(CONFIG_IMX_SERIAL) += serial_imx.o
obj-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o
obj-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
obj-$(CONFIG_MXC_UART) += serial_mxc.o
-obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
-obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
obj-$(CONFIG_SA1100_SERIAL) += serial_sa1100.o
obj-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 6dde4ea..1a75950 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -71,7 +71,7 @@ void serial_initialize(void)
serial_find_console_or_panic();
}
-void serial_putc(char ch)
+static void serial_putc_dev(struct udevice *dev, char ch)
{
struct dm_serial_ops *ops = serial_get_ops(cur_dev);
int err;
@@ -83,6 +83,11 @@ void serial_putc(char ch)
serial_putc('\r');
}
+void serial_putc(char ch)
+{
+ serial_putc_dev(cur_dev, ch);
+}
+
void serial_setbrg(void)
{
struct dm_serial_ops *ops = serial_get_ops(cur_dev);
@@ -107,28 +112,32 @@ int serial_tstc(void)
return 1;
}
-int serial_getc(void)
+static int serial_getc_dev(struct udevice *dev)
{
- struct dm_serial_ops *ops = serial_get_ops(cur_dev);
+ struct dm_serial_ops *ops = serial_get_ops(dev);
int err;
do {
- err = ops->getc(cur_dev);
+ err = ops->getc(dev);
} while (err == -EAGAIN);
return err >= 0 ? err : 0;
}
+int serial_getc(void)
+{
+ return serial_getc_dev(cur_dev);
+}
+
void serial_stdio_init(void)
{
}
-void serial_stub_putc(struct stdio_dev *sdev, const char ch)
+static void serial_stub_putc(struct stdio_dev *sdev, const char ch)
{
struct udevice *dev = sdev->priv;
- struct dm_serial_ops *ops = serial_get_ops(dev);
- ops->putc(dev, ch);
+ serial_putc_dev(dev, ch);
}
void serial_stub_puts(struct stdio_dev *sdev, const char *str)
@@ -140,15 +149,8 @@ void serial_stub_puts(struct stdio_dev *sdev, const char *str)
int serial_stub_getc(struct stdio_dev *sdev)
{
struct udevice *dev = sdev->priv;
- struct dm_serial_ops *ops = serial_get_ops(dev);
-
- int err;
- do {
- err = ops->getc(dev);
- } while (err == -EAGAIN);
-
- return err >= 0 ? err : 0;
+ return serial_getc_dev(dev);
}
int serial_stub_tstc(struct stdio_dev *sdev)
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 313d560..9ce24f9 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -5,37 +5,15 @@
*/
#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <serial_mxc.h>
#include <watchdog.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <serial.h>
#include <linux/compiler.h>
-#define __REG(x) (*((volatile u32 *)(x)))
-
-#ifndef CONFIG_MXC_UART_BASE
-#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
-#endif
-
-#define UART_PHYS CONFIG_MXC_UART_BASE
-
-/* Register definitions */
-#define URXD 0x0 /* Receiver Register */
-#define UTXD 0x40 /* Transmitter Register */
-#define UCR1 0x80 /* Control Register 1 */
-#define UCR2 0x84 /* Control Register 2 */
-#define UCR3 0x88 /* Control Register 3 */
-#define UCR4 0x8c /* Control Register 4 */
-#define UFCR 0x90 /* FIFO Control Register */
-#define USR1 0x94 /* Status Register 1 */
-#define USR2 0x98 /* Status Register 2 */
-#define UESC 0x9c /* Escape Character Register */
-#define UTIM 0xa0 /* Escape Timer Register */
-#define UBIR 0xa4 /* BRM Incremental Register */
-#define UBMR 0xa8 /* BRM Modulator Register */
-#define UBRC 0xac /* Baud Rate Count Register */
-#define UTS 0xb4 /* UART Test Register (mx31) */
-
/* UART Control Register Bit Fields.*/
#define URXD_CHARRDY (1<<15)
#define URXD_ERR (1<<14)
@@ -128,6 +106,33 @@
#define UTS_RXFULL (1<<3) /* RxFIFO full */
#define UTS_SOFTRST (1<<0) /* Software reset */
+#ifndef CONFIG_DM_SERIAL
+
+#ifndef CONFIG_MXC_UART_BASE
+#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
+#endif
+
+#define UART_PHYS CONFIG_MXC_UART_BASE
+
+#define __REG(x) (*((volatile u32 *)(x)))
+
+/* Register definitions */
+#define URXD 0x0 /* Receiver Register */
+#define UTXD 0x40 /* Transmitter Register */
+#define UCR1 0x80 /* Control Register 1 */
+#define UCR2 0x84 /* Control Register 2 */
+#define UCR3 0x88 /* Control Register 3 */
+#define UCR4 0x8c /* Control Register 4 */
+#define UFCR 0x90 /* FIFO Control Register */
+#define USR1 0x94 /* Status Register 1 */
+#define USR2 0x98 /* Status Register 2 */
+#define UESC 0x9c /* Escape Character Register */
+#define UTIM 0xa0 /* Escape Timer Register */
+#define UBIR 0xa4 /* BRM Incremental Register */
+#define UBMR 0xa8 /* BRM Modulator Register */
+#define UBRC 0xac /* Baud Rate Count Register */
+#define UTS 0xb4 /* UART Test Register (mx31) */
+
DECLARE_GLOBAL_DATA_PTR;
static void mxc_serial_setbrg(void)
@@ -222,3 +227,118 @@ __weak struct serial_device *default_serial_console(void)
{
return &mxc_serial_drv;
}
+#endif
+
+#ifdef CONFIG_DM_SERIAL
+
+struct mxc_uart {
+ u32 rxd;
+ u32 spare0[15];
+
+ u32 txd;
+ u32 spare1[15];
+
+ u32 cr1;
+ u32 cr2;
+ u32 cr3;
+ u32 cr4;
+
+ u32 fcr;
+ u32 sr1;
+ u32 sr2;
+ u32 esc;
+
+ u32 tim;
+ u32 bir;
+ u32 bmr;
+ u32 brc;
+
+ u32 onems;
+ u32 ts;
+};
+
+int mxc_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ struct mxc_serial_platdata *plat = dev->platdata;
+ struct mxc_uart *const uart = plat->reg;
+ u32 clk = imx_get_uartclk();
+
+ writel(4 << 7, &uart->fcr); /* divide input clock by 2 */
+ writel(0xf, &uart->bir);
+ writel(clk / (2 * baudrate), &uart->bmr);
+
+ writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
+ &uart->cr2);
+ writel(UCR1_UARTEN, &uart->cr1);
+
+ return 0;
+}
+
+static int mxc_serial_probe(struct udevice *dev)
+{
+ struct mxc_serial_platdata *plat = dev->platdata;
+ struct mxc_uart *const uart = plat->reg;
+
+ writel(0, &uart->cr1);
+ writel(0, &uart->cr2);
+ while (!(readl(&uart->cr2) & UCR2_SRST));
+ writel(0x704 | UCR3_ADNIMP, &uart->cr3);
+ writel(0x8000, &uart->cr4);
+ writel(0x2b, &uart->esc);
+ writel(0, &uart->tim);
+ writel(0, &uart->ts);
+
+ return 0;
+}
+
+static int mxc_serial_getc(struct udevice *dev)
+{
+ struct mxc_serial_platdata *plat = dev->platdata;
+ struct mxc_uart *const uart = plat->reg;
+
+ if (readl(&uart->ts) & UTS_RXEMPTY)
+ return -EAGAIN;
+
+ return readl(&uart->rxd) & URXD_RX_DATA;
+}
+
+static int mxc_serial_putc(struct udevice *dev, const char ch)
+{
+ struct mxc_serial_platdata *plat = dev->platdata;
+ struct mxc_uart *const uart = plat->reg;
+
+ if (!(readl(&uart->ts) & UTS_TXEMPTY))
+ return -EAGAIN;
+
+ writel(ch, &uart->txd);
+
+ return 0;
+}
+
+static int mxc_serial_pending(struct udevice *dev, bool input)
+{
+ struct mxc_serial_platdata *plat = dev->platdata;
+ struct mxc_uart *const uart = plat->reg;
+ uint32_t sr2 = readl(&uart->sr2);
+
+ if (input)
+ return sr2 & USR2_RDR ? 1 : 0;
+ else
+ return sr2 & USR2_TXDC ? 0 : 1;
+}
+
+static const struct dm_serial_ops mxc_serial_ops = {
+ .putc = mxc_serial_putc,
+ .pending = mxc_serial_pending,
+ .getc = mxc_serial_getc,
+ .setbrg = mxc_serial_setbrg,
+};
+
+U_BOOT_DRIVER(serial_mxc) = {
+ .name = "serial_mxc",
+ .id = UCLASS_SERIAL,
+ .probe = mxc_serial_probe,
+ .ops = &mxc_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+#endif
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index dfb610e..e6313ad 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -12,125 +12,90 @@
/* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
#include <common.h>
+#include <dm.h>
+#include <errno.h>
#include <watchdog.h>
#include <asm/io.h>
#include <serial.h>
+#include <serial_pl01x.h>
#include <linux/compiler.h>
-#include "serial_pl01x.h"
+#include "serial_pl01x_internal.h"
+
+#ifndef CONFIG_DM_SERIAL
-/*
- * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
- * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
- * Versatile PB has four UARTs.
- */
-#define CONSOLE_PORT CONFIG_CONS_INDEX
static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
+static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
+static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
#define NUM_PORTS (sizeof(port)/sizeof(port[0]))
-static void pl01x_putc (int portnum, char c);
-static int pl01x_getc (int portnum);
-static int pl01x_tstc (int portnum);
-unsigned int baudrate = CONFIG_BAUDRATE;
DECLARE_GLOBAL_DATA_PTR;
+#endif
-static struct pl01x_regs *pl01x_get_regs(int portnum)
-{
- return (struct pl01x_regs *) port[portnum];
-}
-
-#ifdef CONFIG_PL010_SERIAL
-
-static int pl01x_serial_init(void)
+static int pl01x_putc(struct pl01x_regs *regs, char c)
{
- struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
- unsigned int divisor;
-
- /* First, disable everything */
- writel(0, &regs->pl010_cr);
+ /* Wait until there is space in the FIFO */
+ if (readl(&regs->fr) & UART_PL01x_FR_TXFF)
+ return -EAGAIN;
- /* Set baud rate */
- switch (baudrate) {
- case 9600:
- divisor = UART_PL010_BAUD_9600;
- break;
+ /* Send the character */
+ writel(c, &regs->dr);
- case 19200:
- divisor = UART_PL010_BAUD_9600;
- break;
+ return 0;
+}
- case 38400:
- divisor = UART_PL010_BAUD_38400;
- break;
+static int pl01x_getc(struct pl01x_regs *regs)
+{
+ unsigned int data;
- case 57600:
- divisor = UART_PL010_BAUD_57600;
- break;
+ /* Wait until there is data in the FIFO */
+ if (readl(&regs->fr) & UART_PL01x_FR_RXFE)
+ return -EAGAIN;
- case 115200:
- divisor = UART_PL010_BAUD_115200;
- break;
+ data = readl(&regs->dr);
- default:
- divisor = UART_PL010_BAUD_38400;
+ /* Check for an error flag */
+ if (data & 0xFFFFFF00) {
+ /* Clear the error */
+ writel(0xFFFFFFFF, &regs->ecr);
+ return -1;
}
- writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
- writel(divisor & 0xff, &regs->pl010_lcrl);
-
- /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
- writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, &regs->pl010_lcrh);
-
- /* Finally, enable the UART */
- writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
-
- return 0;
+ return (int) data;
}
-#endif /* CONFIG_PL010_SERIAL */
-
-#ifdef CONFIG_PL011_SERIAL
+static int pl01x_tstc(struct pl01x_regs *regs)
+{
+ WATCHDOG_RESET();
+ return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
+}
-static int pl01x_serial_init(void)
+static int pl01x_generic_serial_init(struct pl01x_regs *regs,
+ enum pl01x_type type)
{
- struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
- unsigned int temp;
- unsigned int divider;
- unsigned int remainder;
- unsigned int fraction;
unsigned int lcr;
#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
- /* Empty RX fifo if necessary */
- if (readl(&regs->pl011_cr) & UART_PL011_CR_UARTEN) {
- while (!(readl(&regs->fr) & UART_PL01x_FR_RXFE))
- readl(&regs->dr);
+ if (type == TYPE_PL011) {
+ /* Empty RX fifo if necessary */
+ if (readl(&regs->pl011_cr) & UART_PL011_CR_UARTEN) {
+ while (!(readl(&regs->fr) & UART_PL01x_FR_RXFE))
+ readl(&regs->dr);
+ }
}
#endif
/* First, disable everything */
- writel(0, &regs->pl011_cr);
-
- /*
- * Set baud rate
- *
- * IBRD = UART_CLK / (16 * BAUD_RATE)
- * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
- */
- temp = 16 * baudrate;
- divider = CONFIG_PL011_CLOCK / temp;
- remainder = CONFIG_PL011_CLOCK % temp;
- temp = (8 * remainder) / baudrate;
- fraction = (temp >> 1) + (temp & 1);
-
- writel(divider, &regs->pl011_ibrd);
- writel(fraction, &regs->pl011_fbrd);
+ writel(0, &regs->pl010_cr);
/* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
writel(lcr, &regs->pl011_lcrh);
+ switch (type) {
+ case TYPE_PL010:
+ break;
+ case TYPE_PL011: {
#ifdef CONFIG_PL011_SERIAL_RLCR
- {
int i;
/*
@@ -144,90 +109,151 @@ static int pl01x_serial_init(void)
writel(lcr, &regs->pl011_rlcr);
/* lcrh needs to be set again for change to be effective */
writel(lcr, &regs->pl011_lcrh);
- }
#endif
- /* Finally, enable the UART */
- writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE |
- UART_PL011_CR_RTS, &regs->pl011_cr);
+ break;
+ }
+ default:
+ return -EINVAL;
+ }
return 0;
}
-#endif /* CONFIG_PL011_SERIAL */
-
-static void pl01x_serial_putc(const char c)
+static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
+ int clock, int baudrate)
{
- if (c == '\n')
- pl01x_putc (CONSOLE_PORT, '\r');
+ switch (type) {
+ case TYPE_PL010: {
+ unsigned int divisor;
+
+ switch (baudrate) {
+ case 9600:
+ divisor = UART_PL010_BAUD_9600;
+ break;
+ case 19200:
+ divisor = UART_PL010_BAUD_9600;
+ break;
+ case 38400:
+ divisor = UART_PL010_BAUD_38400;
+ break;
+ case 57600:
+ divisor = UART_PL010_BAUD_57600;
+ break;
+ case 115200:
+ divisor = UART_PL010_BAUD_115200;
+ break;
+ default:
+ divisor = UART_PL010_BAUD_38400;
+ }
+
+ writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
+ writel(divisor & 0xff, &regs->pl010_lcrl);
+
+ /* Finally, enable the UART */
+ writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
+ break;
+ }
+ case TYPE_PL011: {
+ unsigned int temp;
+ unsigned int divider;
+ unsigned int remainder;
+ unsigned int fraction;
- pl01x_putc (CONSOLE_PORT, c);
-}
+ /*
+ * Set baud rate
+ *
+ * IBRD = UART_CLK / (16 * BAUD_RATE)
+ * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
+ * / (16 * BAUD_RATE))
+ */
+ temp = 16 * baudrate;
+ divider = clock / temp;
+ remainder = clock % temp;
+ temp = (8 * remainder) / baudrate;
+ fraction = (temp >> 1) + (temp & 1);
+
+ writel(divider, &regs->pl011_ibrd);
+ writel(fraction, &regs->pl011_fbrd);
+
+ /* Finally, enable the UART */
+ writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
+ UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);
+ break;
+ }
+ default:
+ return -EINVAL;
+ }
-static int pl01x_serial_getc(void)
-{
- return pl01x_getc (CONSOLE_PORT);
+ return 0;
}
-static int pl01x_serial_tstc(void)
+#ifndef CONFIG_DM_SERIAL
+static void pl01x_serial_init_baud(int baudrate)
{
- return pl01x_tstc (CONSOLE_PORT);
+ int clock = 0;
+
+#if defined(CONFIG_PL010_SERIAL)
+ pl01x_type = TYPE_PL010;
+#elif defined(CONFIG_PL011_SERIAL)
+ pl01x_type = TYPE_PL011;
+ clock = CONFIG_PL011_CLOCK;
+#endif
+ base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
+
+ pl01x_generic_serial_init(base_regs, pl01x_type);
+ pl01x_generic_setbrg(base_regs, TYPE_PL010, clock, baudrate);
}
-static void pl01x_serial_setbrg(void)
+/*
+ * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
+ * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
+ * Versatile PB has four UARTs.
+ */
+int pl01x_serial_init(void)
{
- struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
+ pl01x_serial_init_baud(CONFIG_BAUDRATE);
- baudrate = gd->baudrate;
- /*
- * Flush FIFO and wait for non-busy before changing baudrate to avoid
- * crap in console
- */
- while (!(readl(&regs->fr) & UART_PL01x_FR_TXFE))
- WATCHDOG_RESET();
- while (readl(&regs->fr) & UART_PL01x_FR_BUSY)
- WATCHDOG_RESET();
- serial_init();
+ return 0;
}
-static void pl01x_putc (int portnum, char c)
+static void pl01x_serial_putc(const char c)
{
- struct pl01x_regs *regs = pl01x_get_regs(portnum);
-
- /* Wait until there is space in the FIFO */
- while (readl(&regs->fr) & UART_PL01x_FR_TXFF)
- WATCHDOG_RESET();
+ if (c == '\n')
+ while (pl01x_putc(base_regs, '\r') == -EAGAIN);
- /* Send the character */
- writel(c, &regs->dr);
+ while (pl01x_putc(base_regs, c) == -EAGAIN);
}
-static int pl01x_getc (int portnum)
+static int pl01x_serial_getc(void)
{
- struct pl01x_regs *regs = pl01x_get_regs(portnum);
- unsigned int data;
+ while (1) {
+ int ch = pl01x_getc(base_regs);
- /* Wait until there is data in the FIFO */
- while (readl(&regs->fr) & UART_PL01x_FR_RXFE)
- WATCHDOG_RESET();
-
- data = readl(&regs->dr);
+ if (ch == -EAGAIN) {
+ WATCHDOG_RESET();
+ continue;
+ }
- /* Check for an error flag */
- if (data & 0xFFFFFF00) {
- /* Clear the error */
- writel(0xFFFFFFFF, &regs->ecr);
- return -1;
+ return ch;
}
-
- return (int) data;
}
-static int pl01x_tstc (int portnum)
+static int pl01x_serial_tstc(void)
{
- struct pl01x_regs *regs = pl01x_get_regs(portnum);
+ return pl01x_tstc(base_regs);
+}
- WATCHDOG_RESET();
- return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
+static void pl01x_serial_setbrg(void)
+{
+ /*
+ * Flush FIFO and wait for non-busy before changing baudrate to avoid
+ * crap in console
+ */
+ while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
+ WATCHDOG_RESET();
+ while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
+ WATCHDOG_RESET();
+ pl01x_serial_init_baud(gd->baudrate);
}
static struct serial_device pl01x_serial_drv = {
@@ -250,3 +276,74 @@ __weak struct serial_device *default_serial_console(void)
{
return &pl01x_serial_drv;
}
+
+#endif /* nCONFIG_DM_SERIAL */
+
+#ifdef CONFIG_DM_SERIAL
+
+struct pl01x_priv {
+ struct pl01x_regs *regs;
+ enum pl01x_type type;
+};
+
+static int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
+ struct pl01x_priv *priv = dev_get_priv(dev);
+
+ pl01x_generic_setbrg(priv->regs, priv->type, plat->clock, baudrate);
+
+ return 0;
+}
+
+static int pl01x_serial_probe(struct udevice *dev)
+{
+ struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
+ struct pl01x_priv *priv = dev_get_priv(dev);
+
+ priv->regs = (struct pl01x_regs *)plat->base;
+ priv->type = plat->type;
+ return pl01x_generic_serial_init(priv->regs, priv->type);
+}
+
+static int pl01x_serial_getc(struct udevice *dev)
+{
+ struct pl01x_priv *priv = dev_get_priv(dev);
+
+ return pl01x_getc(priv->regs);
+}
+
+static int pl01x_serial_putc(struct udevice *dev, const char ch)
+{
+ struct pl01x_priv *priv = dev_get_priv(dev);
+
+ return pl01x_putc(priv->regs, ch);
+}
+
+static int pl01x_serial_pending(struct udevice *dev, bool input)
+{
+ struct pl01x_priv *priv = dev_get_priv(dev);
+ unsigned int fr = readl(&priv->regs->fr);
+
+ if (input)
+ return pl01x_tstc(priv->regs);
+ else
+ return fr & UART_PL01x_FR_TXFF ? 0 : 1;
+}
+
+static const struct dm_serial_ops pl01x_serial_ops = {
+ .putc = pl01x_serial_putc,
+ .pending = pl01x_serial_pending,
+ .getc = pl01x_serial_getc,
+ .setbrg = pl01x_serial_setbrg,
+};
+
+U_BOOT_DRIVER(serial_pl01x) = {
+ .name = "serial_pl01x",
+ .id = UCLASS_SERIAL,
+ .probe = pl01x_serial_probe,
+ .ops = &pl01x_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+#endif
diff --git a/drivers/serial/serial_pl01x.h b/drivers/serial/serial_pl01x_internal.h
index 288a4f1..288a4f1 100644
--- a/drivers/serial/serial_pl01x.h
+++ b/drivers/serial/serial_pl01x_internal.h
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index 98c62b4..8469afd 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -9,6 +9,8 @@
*/
#include <common.h>
+#include <dm.h>
+#include <errno.h>
#include <fdtdec.h>
#include <linux/compiler.h>
#include <asm/io.h>
@@ -18,26 +20,18 @@
DECLARE_GLOBAL_DATA_PTR;
-#define RX_FIFO_COUNT_MASK 0xff
-#define RX_FIFO_FULL_MASK (1 << 8)
-#define TX_FIFO_FULL_MASK (1 << 24)
+#define RX_FIFO_COUNT_SHIFT 0
+#define RX_FIFO_COUNT_MASK (0xff << RX_FIFO_COUNT_SHIFT)
+#define RX_FIFO_FULL (1 << 8)
+#define TX_FIFO_COUNT_SHIFT 16
+#define TX_FIFO_COUNT_MASK (0xff << TX_FIFO_COUNT_SHIFT)
+#define TX_FIFO_FULL (1 << 24)
/* Information about a serial port */
-struct fdt_serial {
- u32 base_addr; /* address of registers in physical memory */
+struct s5p_serial_platdata {
+ struct s5p_uart *reg; /* address of registers in physical memory */
u8 port_id; /* uart port number */
- u8 enabled; /* 1 if enabled, 0 if disabled */
-} config __attribute__ ((section(".data")));
-
-static inline struct s5p_uart *s5p_get_base_uart(int dev_index)
-{
-#ifdef CONFIG_OF_CONTROL
- return (struct s5p_uart *)(config.base_addr);
-#else
- u32 offset = dev_index * sizeof(struct s5p_uart);
- return (struct s5p_uart *)(samsung_get_base_uart() + offset);
-#endif
-}
+};
/*
* The coefficient, used to calculate the baudrate on S5P UARTs is
@@ -65,23 +59,13 @@ static const int udivslot[] = {
0xffdf,
};
-static void serial_setbrg_dev(const int dev_index)
+int s5p_serial_setbrg(struct udevice *dev, int baudrate)
{
- struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
- u32 uclk = get_uart_clk(dev_index);
- u32 baudrate = gd->baudrate;
+ struct s5p_serial_platdata *plat = dev->platdata;
+ struct s5p_uart *const uart = plat->reg;
+ u32 uclk = get_uart_clk(plat->port_id);
u32 val;
-#if defined(CONFIG_SILENT_CONSOLE) && \
- defined(CONFIG_OF_CONTROL) && \
- !defined(CONFIG_SPL_BUILD)
- if (fdtdec_get_config_int(gd->fdt_blob, "silent_console", 0))
- gd->flags |= GD_FLG_SILENT;
-#endif
-
- if (!config.enabled)
- return;
-
val = uclk / baudrate;
writel(val / 16 - 1, &uart->ubrdiv);
@@ -90,15 +74,14 @@ static void serial_setbrg_dev(const int dev_index)
writew(udivslot[val % 16], &uart->rest.slot);
else
writeb(val % 16, &uart->rest.value);
+
+ return 0;
}
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- */
-static int serial_init_dev(const int dev_index)
+static int s5p_serial_probe(struct udevice *dev)
{
- struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
+ struct s5p_serial_platdata *plat = dev->platdata;
+ struct s5p_uart *const uart = plat->reg;
/* enable FIFOs, auto clear Rx FIFO */
writel(0x3, &uart->ufcon);
@@ -108,14 +91,11 @@ static int serial_init_dev(const int dev_index)
/* No interrupts, no DMA, pure polling */
writel(0x245, &uart->ucon);
- serial_setbrg_dev(dev_index);
-
return 0;
}
-static int serial_err_check(const int dev_index, int op)
+static int serial_err_check(const struct s5p_uart *const uart, int op)
{
- struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
unsigned int mask;
/*
@@ -133,169 +113,78 @@ static int serial_err_check(const int dev_index, int op)
return readl(&uart->uerstat) & mask;
}
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-static int serial_getc_dev(const int dev_index)
+static int s5p_serial_getc(struct udevice *dev)
{
- struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
-
- if (!config.enabled)
- return 0;
+ struct s5p_serial_platdata *plat = dev->platdata;
+ struct s5p_uart *const uart = plat->reg;
- /* wait for character to arrive */
- while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK |
- RX_FIFO_FULL_MASK))) {
- if (serial_err_check(dev_index, 0))
- return 0;
- }
+ if (!(readl(&uart->ufstat) & RX_FIFO_COUNT_MASK))
+ return -EAGAIN;
+ serial_err_check(uart, 0);
return (int)(readb(&uart->urxh) & 0xff);
}
-/*
- * Output a single byte to the serial port.
- */
-static void serial_putc_dev(const char c, const int dev_index)
+static int s5p_serial_putc(struct udevice *dev, const char ch)
{
- struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
-
- if (!config.enabled)
- return;
-
- /* wait for room in the tx FIFO */
- while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) {
- if (serial_err_check(dev_index, 1))
- return;
- }
+ struct s5p_serial_platdata *plat = dev->platdata;
+ struct s5p_uart *const uart = plat->reg;
- writeb(c, &uart->utxh);
+ if (readl(&uart->ufstat) & TX_FIFO_FULL)
+ return -EAGAIN;
- /* If \n, also do \r */
- if (c == '\n')
- serial_putc('\r');
-}
-
-/*
- * Test whether a character is in the RX buffer
- */
-static int serial_tstc_dev(const int dev_index)
-{
- struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
+ writeb(ch, &uart->utxh);
+ serial_err_check(uart, 1);
- if (!config.enabled)
- return 0;
-
- return (int)(readl(&uart->utrstat) & 0x1);
+ return 0;
}
-static void serial_puts_dev(const char *s, const int dev_index)
+static int s5p_serial_pending(struct udevice *dev, bool input)
{
- while (*s)
- serial_putc_dev(*s++, dev_index);
-}
+ struct s5p_serial_platdata *plat = dev->platdata;
+ struct s5p_uart *const uart = plat->reg;
+ uint32_t ufstat = readl(&uart->ufstat);
-/* Multi serial device functions */
-#define DECLARE_S5P_SERIAL_FUNCTIONS(port) \
-static int s5p_serial##port##_init(void) { return serial_init_dev(port); } \
-static void s5p_serial##port##_setbrg(void) { serial_setbrg_dev(port); } \
-static int s5p_serial##port##_getc(void) { return serial_getc_dev(port); } \
-static int s5p_serial##port##_tstc(void) { return serial_tstc_dev(port); } \
-static void s5p_serial##port##_putc(const char c) { serial_putc_dev(c, port); } \
-static void s5p_serial##port##_puts(const char *s) { serial_puts_dev(s, port); }
-
-#define INIT_S5P_SERIAL_STRUCTURE(port, __name) { \
- .name = __name, \
- .start = s5p_serial##port##_init, \
- .stop = NULL, \
- .setbrg = s5p_serial##port##_setbrg, \
- .getc = s5p_serial##port##_getc, \
- .tstc = s5p_serial##port##_tstc, \
- .putc = s5p_serial##port##_putc, \
- .puts = s5p_serial##port##_puts, \
+ if (input)
+ return (ufstat & RX_FIFO_COUNT_MASK) >> RX_FIFO_COUNT_SHIFT;
+ else
+ return (ufstat & TX_FIFO_COUNT_MASK) >> TX_FIFO_COUNT_SHIFT;
}
-DECLARE_S5P_SERIAL_FUNCTIONS(0);
-struct serial_device s5p_serial0_device =
- INIT_S5P_SERIAL_STRUCTURE(0, "s5pser0");
-DECLARE_S5P_SERIAL_FUNCTIONS(1);
-struct serial_device s5p_serial1_device =
- INIT_S5P_SERIAL_STRUCTURE(1, "s5pser1");
-DECLARE_S5P_SERIAL_FUNCTIONS(2);
-struct serial_device s5p_serial2_device =
- INIT_S5P_SERIAL_STRUCTURE(2, "s5pser2");
-DECLARE_S5P_SERIAL_FUNCTIONS(3);
-struct serial_device s5p_serial3_device =
- INIT_S5P_SERIAL_STRUCTURE(3, "s5pser3");
-
-#ifdef CONFIG_OF_CONTROL
-int fdtdec_decode_console(int *index, struct fdt_serial *uart)
+static int s5p_serial_ofdata_to_platdata(struct udevice *dev)
{
- const void *blob = gd->fdt_blob;
- int node;
+ struct s5p_serial_platdata *plat = dev->platdata;
+ fdt_addr_t addr;
- node = fdt_path_offset(blob, "console");
- if (node < 0)
- return node;
+ addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
- uart->base_addr = fdtdec_get_addr(blob, node, "reg");
- if (uart->base_addr == FDT_ADDR_T_NONE)
- return -FDT_ERR_NOTFOUND;
-
- uart->port_id = fdtdec_get_int(blob, node, "id", -1);
- uart->enabled = fdtdec_get_is_enabled(blob, node);
+ plat->reg = (struct s5p_uart *)addr;
+ plat->port_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "id", -1);
return 0;
}
-#endif
-__weak struct serial_device *default_serial_console(void)
-{
-#ifdef CONFIG_OF_CONTROL
- int index = 0;
-
- if ((!config.base_addr) && (fdtdec_decode_console(&index, &config))) {
- debug("Cannot decode default console node\n");
- return NULL;
- }
-
- switch (config.port_id) {
- case 0:
- return &s5p_serial0_device;
- case 1:
- return &s5p_serial1_device;
- case 2:
- return &s5p_serial2_device;
- case 3:
- return &s5p_serial3_device;
- default:
- debug("Unknown config.port_id: %d", config.port_id);
- break;
- }
-
- return NULL;
-#else
- config.enabled = 1;
-#if defined(CONFIG_SERIAL0)
- return &s5p_serial0_device;
-#elif defined(CONFIG_SERIAL1)
- return &s5p_serial1_device;
-#elif defined(CONFIG_SERIAL2)
- return &s5p_serial2_device;
-#elif defined(CONFIG_SERIAL3)
- return &s5p_serial3_device;
-#else
-#error "CONFIG_SERIAL? missing."
-#endif
-#endif
-}
+static const struct dm_serial_ops s5p_serial_ops = {
+ .putc = s5p_serial_putc,
+ .pending = s5p_serial_pending,
+ .getc = s5p_serial_getc,
+ .setbrg = s5p_serial_setbrg,
+};
-void s5p_serial_initialize(void)
-{
- serial_register(&s5p_serial0_device);
- serial_register(&s5p_serial1_device);
- serial_register(&s5p_serial2_device);
- serial_register(&s5p_serial3_device);
-}
+static const struct udevice_id s5p_serial_ids[] = {
+ { .compatible = "samsung,exynos4210-uart" },
+ { }
+};
+
+U_BOOT_DRIVER(serial_s5p) = {
+ .name = "serial_s5p",
+ .id = UCLASS_SERIAL,
+ .of_match = s5p_serial_ids,
+ .ofdata_to_platdata = s5p_serial_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct s5p_serial_platdata),
+ .probe = s5p_serial_probe,
+ .ops = &s5p_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index f02c35a..eabbf27 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -6,7 +6,14 @@
#
# There are many options which enable SPI, so make this library available
+ifdef CONFIG_DM_SPI
+obj-y += spi-uclass.o
+obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o
+obj-$(CONFIG_SOFT_SPI) += soft_spi.o
+else
obj-y += spi.o
+obj-$(CONFIG_SOFT_SPI) += soft_spi_legacy.o
+endif
obj-$(CONFIG_EP93XX_SPI) += ep93xx_spi.o
obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
@@ -30,11 +37,9 @@ obj-$(CONFIG_MXS_SPI) += mxs_spi.o
obj-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
-obj-$(CONFIG_SOFT_SPI) += soft_spi.o
obj-$(CONFIG_SH_SPI) += sh_spi.o
obj-$(CONFIG_SH_QSPI) += sh_qspi.o
obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
-obj-$(CONFIG_FDT_SPI) += fdt_spi.o
obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c
index 2969184..f078973 100644
--- a/drivers/spi/exynos_spi.c
+++ b/drivers/spi/exynos_spi.c
@@ -6,6 +6,8 @@
*/
#include <common.h>
+#include <dm.h>
+#include <errno.h>
#include <malloc.h>
#include <spi.h>
#include <fdtdec.h>
@@ -19,176 +21,35 @@
DECLARE_GLOBAL_DATA_PTR;
-/* Information about each SPI controller */
-struct spi_bus {
+struct exynos_spi_platdata {
enum periph_id periph_id;
s32 frequency; /* Default clock frequency, -1 for none */
struct exynos_spi *regs;
- int inited; /* 1 if this bus is ready for use */
- int node;
uint deactivate_delay_us; /* Delay to wait after deactivate */
};
-/* A list of spi buses that we know about */
-static struct spi_bus spi_bus[EXYNOS5_SPI_NUM_CONTROLLERS];
-static unsigned int bus_count;
-
-struct exynos_spi_slave {
- struct spi_slave slave;
+struct exynos_spi_priv {
struct exynos_spi *regs;
unsigned int freq; /* Default frequency */
unsigned int mode;
enum periph_id periph_id; /* Peripheral ID for this device */
unsigned int fifo_size;
int skip_preamble;
- struct spi_bus *bus; /* Pointer to our SPI bus info */
ulong last_transaction_us; /* Time of last transaction end */
};
-static struct spi_bus *spi_get_bus(unsigned dev_index)
-{
- if (dev_index < bus_count)
- return &spi_bus[dev_index];
- debug("%s: invalid bus %d", __func__, dev_index);
-
- return NULL;
-}
-
-static inline struct exynos_spi_slave *to_exynos_spi(struct spi_slave *slave)
-{
- return container_of(slave, struct exynos_spi_slave, slave);
-}
-
-/**
- * Setup the driver private data
- *
- * @param bus ID of the bus that the slave is attached to
- * @param cs ID of the chip select connected to the slave
- * @param max_hz Required spi frequency
- * @param mode Required spi mode (clk polarity, clk phase and
- * master or slave)
- * @return new device or NULL
- */
-struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct exynos_spi_slave *spi_slave;
- struct spi_bus *bus;
-
- if (!spi_cs_is_valid(busnum, cs)) {
- debug("%s: Invalid bus/chip select %d, %d\n", __func__,
- busnum, cs);
- return NULL;
- }
-
- spi_slave = spi_alloc_slave(struct exynos_spi_slave, busnum, cs);
- if (!spi_slave) {
- debug("%s: Could not allocate spi_slave\n", __func__);
- return NULL;
- }
-
- bus = &spi_bus[busnum];
- spi_slave->bus = bus;
- spi_slave->regs = bus->regs;
- spi_slave->mode = mode;
- spi_slave->periph_id = bus->periph_id;
- if (bus->periph_id == PERIPH_ID_SPI1 ||
- bus->periph_id == PERIPH_ID_SPI2)
- spi_slave->fifo_size = 64;
- else
- spi_slave->fifo_size = 256;
-
- spi_slave->skip_preamble = 0;
- spi_slave->last_transaction_us = timer_get_us();
-
- spi_slave->freq = bus->frequency;
- if (max_hz)
- spi_slave->freq = min(max_hz, spi_slave->freq);
-
- return &spi_slave->slave;
-}
-
-/**
- * Free spi controller
- *
- * @param slave Pointer to spi_slave to which controller has to
- * communicate with
- */
-void spi_free_slave(struct spi_slave *slave)
-{
- struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
-
- free(spi_slave);
-}
-
/**
* Flush spi tx, rx fifos and reset the SPI controller
*
- * @param slave Pointer to spi_slave to which controller has to
- * communicate with
+ * @param regs Pointer to SPI registers
*/
-static void spi_flush_fifo(struct spi_slave *slave)
+static void spi_flush_fifo(struct exynos_spi *regs)
{
- struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
- struct exynos_spi *regs = spi_slave->regs;
-
clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
setbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
}
-/**
- * Initialize the spi base registers, set the required clock frequency and
- * initialize the gpios
- *
- * @param slave Pointer to spi_slave to which controller has to
- * communicate with
- * @return zero on success else a negative value
- */
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
- struct exynos_spi *regs = spi_slave->regs;
- u32 reg = 0;
- int ret;
-
- ret = set_spi_clk(spi_slave->periph_id,
- spi_slave->freq);
- if (ret < 0) {
- debug("%s: Failed to setup spi clock\n", __func__);
- return ret;
- }
-
- exynos_pinmux_config(spi_slave->periph_id, PINMUX_FLAG_NONE);
-
- spi_flush_fifo(slave);
-
- reg = readl(&regs->ch_cfg);
- reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
-
- if (spi_slave->mode & SPI_CPHA)
- reg |= SPI_CH_CPHA_B;
-
- if (spi_slave->mode & SPI_CPOL)
- reg |= SPI_CH_CPOL_L;
-
- writel(reg, &regs->ch_cfg);
- writel(SPI_FB_DELAY_180, &regs->fb_clk);
-
- return 0;
-}
-
-/**
- * Reset the spi H/W and flush the tx and rx fifos
- *
- * @param slave Pointer to spi_slave to which controller has to
- * communicate with
- */
-void spi_release_bus(struct spi_slave *slave)
-{
- spi_flush_fifo(slave);
-}
-
static void spi_get_fifo_levels(struct exynos_spi *regs,
int *rx_lvl, int *tx_lvl)
{
@@ -208,6 +69,8 @@ static void spi_get_fifo_levels(struct exynos_spi *regs,
*/
static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
{
+ debug("%s: regs=%p, count=%d, step=%d\n", __func__, regs, count, step);
+
/* For word address we need to swap bytes */
if (step == 4) {
setbits_le32(&regs->mode_cfg,
@@ -230,10 +93,10 @@ static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
writel(count | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
}
-static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
+static int spi_rx_tx(struct exynos_spi_priv *priv, int todo,
void **dinp, void const **doutp, unsigned long flags)
{
- struct exynos_spi *regs = spi_slave->regs;
+ struct exynos_spi *regs = priv->regs;
uchar *rxp = *dinp;
const uchar *txp = *doutp;
int rx_lvl, tx_lvl;
@@ -245,8 +108,8 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
out_bytes = in_bytes = todo;
- stopping = spi_slave->skip_preamble && (flags & SPI_XFER_END) &&
- !(spi_slave->mode & SPI_SLAVE);
+ stopping = priv->skip_preamble && (flags & SPI_XFER_END) &&
+ !(priv->mode & SPI_SLAVE);
/*
* Try to transfer words if we can. This helps read performance at
@@ -254,7 +117,7 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
*/
step = 1;
if (!((todo | (uintptr_t)rxp | (uintptr_t)txp) & 3) &&
- !spi_slave->skip_preamble)
+ !priv->skip_preamble)
step = 4;
/*
@@ -279,7 +142,7 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
* Don't completely fill the txfifo, since we don't want our
* rxfifo to overflow, and it may already contain data.
*/
- while (tx_lvl < spi_slave->fifo_size/2 && out_bytes) {
+ while (tx_lvl < priv->fifo_size/2 && out_bytes) {
if (!txp)
temp = -1;
else if (step == 4)
@@ -295,9 +158,9 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
if (rx_lvl >= step) {
while (rx_lvl >= step) {
temp = readl(&regs->rx_data);
- if (spi_slave->skip_preamble) {
+ if (priv->skip_preamble) {
if (temp == SPI_PREAMBLE_END_BYTE) {
- spi_slave->skip_preamble = 0;
+ priv->skip_preamble = 0;
stopping = 0;
}
} else {
@@ -326,7 +189,7 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
txp = NULL;
spi_request_bytes(regs, toread, step);
}
- if (spi_slave->skip_preamble && get_timer(start) > 100) {
+ if (priv->skip_preamble && get_timer(start) > 100) {
printf("SPI timeout: in_bytes=%d, out_bytes=%d, ",
in_bytes, out_bytes);
return -1;
@@ -340,94 +203,29 @@ static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
}
/**
- * Transfer and receive data
- *
- * @param slave Pointer to spi_slave to which controller has to
- * communicate with
- * @param bitlen No of bits to tranfer or receive
- * @param dout Pointer to transfer buffer
- * @param din Pointer to receive buffer
- * @param flags Flags for transfer begin and end
- * @return zero on success else a negative value
- */
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
-{
- struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
- int upto, todo;
- int bytelen;
- int ret = 0;
-
- /* spi core configured to do 8 bit transfers */
- if (bitlen % 8) {
- debug("Non byte aligned SPI transfer.\n");
- return -1;
- }
-
- /* Start the transaction, if necessary. */
- if ((flags & SPI_XFER_BEGIN))
- spi_cs_activate(slave);
-
- /*
- * Exynos SPI limits each transfer to 65535 transfers. To keep
- * things simple, allow a maximum of 65532 bytes. We could allow
- * more in word mode, but the performance difference is small.
- */
- bytelen = bitlen / 8;
- for (upto = 0; !ret && upto < bytelen; upto += todo) {
- todo = min(bytelen - upto, (1 << 16) - 4);
- ret = spi_rx_tx(spi_slave, todo, &din, &dout, flags);
- if (ret)
- break;
- }
-
- /* Stop the transaction, if necessary. */
- if ((flags & SPI_XFER_END) && !(spi_slave->mode & SPI_SLAVE)) {
- spi_cs_deactivate(slave);
- if (spi_slave->skip_preamble) {
- assert(!spi_slave->skip_preamble);
- debug("Failed to complete premable transaction\n");
- ret = -1;
- }
- }
-
- return ret;
-}
-
-/**
- * Validates the bus and chip select numbers
- *
- * @param bus ID of the bus that the slave is attached to
- * @param cs ID of the chip select connected to the slave
- * @return one on success else zero
- */
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return spi_get_bus(bus) && cs == 0;
-}
-
-/**
* Activate the CS by driving it LOW
*
* @param slave Pointer to spi_slave to which controller has to
* communicate with
*/
-void spi_cs_activate(struct spi_slave *slave)
+static void spi_cs_activate(struct udevice *dev)
{
- struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
+ struct udevice *bus = dev->parent;
+ struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
+ struct exynos_spi_priv *priv = dev_get_priv(bus);
/* If it's too soon to do another transaction, wait */
- if (spi_slave->bus->deactivate_delay_us &&
- spi_slave->last_transaction_us) {
+ if (pdata->deactivate_delay_us &&
+ priv->last_transaction_us) {
ulong delay_us; /* The delay completed so far */
- delay_us = timer_get_us() - spi_slave->last_transaction_us;
- if (delay_us < spi_slave->bus->deactivate_delay_us)
- udelay(spi_slave->bus->deactivate_delay_us - delay_us);
+ delay_us = timer_get_us() - priv->last_transaction_us;
+ if (delay_us < pdata->deactivate_delay_us)
+ udelay(pdata->deactivate_delay_us - delay_us);
}
- clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
- debug("Activate CS, bus %d\n", spi_slave->slave.bus);
- spi_slave->skip_preamble = spi_slave->mode & SPI_PREAMBLE;
+ clrbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
+ debug("Activate CS, bus '%s'\n", bus->name);
+ priv->skip_preamble = priv->mode & SPI_PREAMBLE;
}
/**
@@ -436,148 +234,197 @@ void spi_cs_activate(struct spi_slave *slave)
* @param slave Pointer to spi_slave to which controller has to
* communicate with
*/
-void spi_cs_deactivate(struct spi_slave *slave)
+static void spi_cs_deactivate(struct udevice *dev)
{
- struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
+ struct udevice *bus = dev->parent;
+ struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
+ struct exynos_spi_priv *priv = dev_get_priv(bus);
- setbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
+ setbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
/* Remember time of this transaction so we can honour the bus delay */
- if (spi_slave->bus->deactivate_delay_us)
- spi_slave->last_transaction_us = timer_get_us();
+ if (pdata->deactivate_delay_us)
+ priv->last_transaction_us = timer_get_us();
- debug("Deactivate CS, bus %d\n", spi_slave->slave.bus);
+ debug("Deactivate CS, bus '%s'\n", bus->name);
}
-static inline struct exynos_spi *get_spi_base(int dev_index)
+static int exynos_spi_ofdata_to_platdata(struct udevice *bus)
{
- if (dev_index < 3)
- return (struct exynos_spi *)samsung_get_base_spi() + dev_index;
- else
- return (struct exynos_spi *)samsung_get_base_spi_isp() +
- (dev_index - 3);
-}
+ struct exynos_spi_platdata *plat = bus->platdata;
+ const void *blob = gd->fdt_blob;
+ int node = bus->of_offset;
-/*
- * Read the SPI config from the device tree node.
- *
- * @param blob FDT blob to read from
- * @param node Node offset to read from
- * @param bus SPI bus structure to fill with information
- * @return 0 if ok, or -FDT_ERR_NOTFOUND if something was missing
- */
-#ifdef CONFIG_OF_CONTROL
-static int spi_get_config(const void *blob, int node, struct spi_bus *bus)
-{
- bus->node = node;
- bus->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg");
- bus->periph_id = pinmux_decode_periph_id(blob, node);
+ plat->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg");
+ plat->periph_id = pinmux_decode_periph_id(blob, node);
- if (bus->periph_id == PERIPH_ID_NONE) {
+ if (plat->periph_id == PERIPH_ID_NONE) {
debug("%s: Invalid peripheral ID %d\n", __func__,
- bus->periph_id);
+ plat->periph_id);
return -FDT_ERR_NOTFOUND;
}
/* Use 500KHz as a suitable default */
- bus->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+ plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
500000);
- bus->deactivate_delay_us = fdtdec_get_int(blob, node,
+ plat->deactivate_delay_us = fdtdec_get_int(blob, node,
"spi-deactivate-delay", 0);
+ debug("%s: regs=%p, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
+ __func__, plat->regs, plat->periph_id, plat->frequency,
+ plat->deactivate_delay_us);
return 0;
}
-/*
- * Process a list of nodes, adding them to our list of SPI ports.
- *
- * @param blob fdt blob
- * @param node_list list of nodes to process (any <=0 are ignored)
- * @param count number of nodes to process
- * @param is_dvc 1 if these are DVC ports, 0 if standard I2C
- * @return 0 if ok, -1 on error
- */
-static int process_nodes(const void *blob, int node_list[], int count)
+static int exynos_spi_probe(struct udevice *bus)
{
- int i;
+ struct exynos_spi_platdata *plat = dev_get_platdata(bus);
+ struct exynos_spi_priv *priv = dev_get_priv(bus);
- /* build the i2c_controllers[] for each controller */
- for (i = 0; i < count; i++) {
- int node = node_list[i];
- struct spi_bus *bus;
+ priv->regs = plat->regs;
+ if (plat->periph_id == PERIPH_ID_SPI1 ||
+ plat->periph_id == PERIPH_ID_SPI2)
+ priv->fifo_size = 64;
+ else
+ priv->fifo_size = 256;
- if (node <= 0)
- continue;
+ priv->skip_preamble = 0;
+ priv->last_transaction_us = timer_get_us();
+ priv->freq = plat->frequency;
+ priv->periph_id = plat->periph_id;
- bus = &spi_bus[i];
- if (spi_get_config(blob, node, bus)) {
- printf("exynos spi_init: failed to decode bus %d\n",
- i);
- return -1;
- }
+ return 0;
+}
- debug("spi: controller bus %d at %p, periph_id %d\n",
- i, bus->regs, bus->periph_id);
- bus->inited = 1;
- bus_count++;
- }
+static int exynos_spi_claim_bus(struct udevice *bus)
+{
+ struct exynos_spi_priv *priv = dev_get_priv(bus);
+
+ exynos_pinmux_config(priv->periph_id, PINMUX_FLAG_NONE);
+ spi_flush_fifo(priv->regs);
+
+ writel(SPI_FB_DELAY_180, &priv->regs->fb_clk);
return 0;
}
-#endif
-/**
- * Set up a new SPI slave for an fdt node
- *
- * @param blob Device tree blob
- * @param node SPI peripheral node to use
- * @return 0 if ok, -1 on error
- */
-struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
- int spi_node)
+static int exynos_spi_release_bus(struct udevice *bus)
{
- struct spi_bus *bus;
- unsigned int i;
+ struct exynos_spi_priv *priv = dev_get_priv(bus);
+
+ spi_flush_fifo(priv->regs);
+
+ return 0;
+}
+
+static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct exynos_spi_priv *priv = dev_get_priv(bus);
+ int upto, todo;
+ int bytelen;
+ int ret = 0;
+
+ /* spi core configured to do 8 bit transfers */
+ if (bitlen % 8) {
+ debug("Non byte aligned SPI transfer.\n");
+ return -1;
+ }
+
+ /* Start the transaction, if necessary. */
+ if ((flags & SPI_XFER_BEGIN))
+ spi_cs_activate(dev);
+
+ /*
+ * Exynos SPI limits each transfer to 65535 transfers. To keep
+ * things simple, allow a maximum of 65532 bytes. We could allow
+ * more in word mode, but the performance difference is small.
+ */
+ bytelen = bitlen / 8;
+ for (upto = 0; !ret && upto < bytelen; upto += todo) {
+ todo = min(bytelen - upto, (1 << 16) - 4);
+ ret = spi_rx_tx(priv, todo, &din, &dout, flags);
+ if (ret)
+ break;
+ }
- for (i = 0, bus = spi_bus; i < bus_count; i++, bus++) {
- if (bus->node == spi_node)
- return spi_base_setup_slave_fdt(blob, i, slave_node);
+ /* Stop the transaction, if necessary. */
+ if ((flags & SPI_XFER_END) && !(priv->mode & SPI_SLAVE)) {
+ spi_cs_deactivate(dev);
+ if (priv->skip_preamble) {
+ assert(!priv->skip_preamble);
+ debug("Failed to complete premable transaction\n");
+ ret = -1;
+ }
}
- debug("%s: Failed to find bus node %d\n", __func__, spi_node);
- return NULL;
+ return ret;
}
-/* Sadly there is no error return from this function */
-void spi_init(void)
+static int exynos_spi_set_speed(struct udevice *bus, uint speed)
{
- int count;
+ struct exynos_spi_platdata *plat = bus->platdata;
+ struct exynos_spi_priv *priv = dev_get_priv(bus);
+ int ret;
-#ifdef CONFIG_OF_CONTROL
- int node_list[EXYNOS5_SPI_NUM_CONTROLLERS];
- const void *blob = gd->fdt_blob;
+ if (speed > plat->frequency)
+ speed = plat->frequency;
+ ret = set_spi_clk(priv->periph_id, speed);
+ if (ret)
+ return ret;
+ priv->freq = speed;
+ debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
+
+ return 0;
+}
- count = fdtdec_find_aliases_for_id(blob, "spi",
- COMPAT_SAMSUNG_EXYNOS_SPI, node_list,
- EXYNOS5_SPI_NUM_CONTROLLERS);
- if (process_nodes(blob, node_list, count))
- return;
+static int exynos_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct exynos_spi_priv *priv = dev_get_priv(bus);
+ uint32_t reg;
-#else
- struct spi_bus *bus;
+ reg = readl(&priv->regs->ch_cfg);
+ reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
- for (count = 0; count < EXYNOS5_SPI_NUM_CONTROLLERS; count++) {
- bus = &spi_bus[count];
- bus->regs = get_spi_base(count);
- bus->periph_id = PERIPH_ID_SPI0 + count;
+ if (mode & SPI_CPHA)
+ reg |= SPI_CH_CPHA_B;
- /* Although Exynos5 supports upto 50Mhz speed,
- * we are setting it to 10Mhz for safe side
- */
- bus->frequency = 10000000;
- bus->inited = 1;
- bus->node = 0;
- bus_count = EXYNOS5_SPI_NUM_CONTROLLERS;
- }
-#endif
+ if (mode & SPI_CPOL)
+ reg |= SPI_CH_CPOL_L;
+
+ writel(reg, &priv->regs->ch_cfg);
+ priv->mode = mode;
+ debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
+
+ return 0;
}
+
+static const struct dm_spi_ops exynos_spi_ops = {
+ .claim_bus = exynos_spi_claim_bus,
+ .release_bus = exynos_spi_release_bus,
+ .xfer = exynos_spi_xfer,
+ .set_speed = exynos_spi_set_speed,
+ .set_mode = exynos_spi_set_mode,
+ /*
+ * cs_info is not needed, since we require all chip selects to be
+ * in the device tree explicitly
+ */
+};
+
+static const struct udevice_id exynos_spi_ids[] = {
+ { .compatible = "samsung,exynos-spi" },
+ { }
+};
+
+U_BOOT_DRIVER(exynos_spi) = {
+ .name = "exynos_spi",
+ .id = UCLASS_SPI,
+ .of_match = exynos_spi_ids,
+ .ops = &exynos_spi_ops,
+ .ofdata_to_platdata = exynos_spi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct exynos_spi_platdata),
+ .priv_auto_alloc_size = sizeof(struct exynos_spi_priv),
+ .per_child_auto_alloc_size = sizeof(struct spi_slave),
+ .probe = exynos_spi_probe,
+};
diff --git a/drivers/spi/fdt_spi.c b/drivers/spi/fdt_spi.c
deleted file mode 100644
index 58f139a..0000000
--- a/drivers/spi/fdt_spi.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * Common fdt based SPI driver front end
- *
- * Copyright (c) 2013 NVIDIA Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/arch/clock.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra20/tegra20_sflash.h>
-#include <asm/arch-tegra20/tegra20_slink.h>
-#include <asm/arch-tegra114/tegra114_spi.h>
-#include <spi.h>
-#include <fdtdec.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct fdt_spi_driver {
- int compat;
- int max_ctrls;
- int (*init)(int *node_list, int count);
- int (*claim_bus)(struct spi_slave *slave);
- int (*release_bus)(struct spi_slave *slave);
- int (*cs_is_valid)(unsigned int bus, unsigned int cs);
- struct spi_slave *(*setup_slave)(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode);
- void (*free_slave)(struct spi_slave *slave);
- void (*cs_activate)(struct spi_slave *slave);
- void (*cs_deactivate)(struct spi_slave *slave);
- int (*xfer)(struct spi_slave *slave, unsigned int bitlen,
- const void *data_out, void *data_in, unsigned long flags);
-};
-
-static struct fdt_spi_driver fdt_spi_drivers[] = {
-#ifdef CONFIG_TEGRA20_SFLASH
- {
- .compat = COMPAT_NVIDIA_TEGRA20_SFLASH,
- .max_ctrls = 1,
- .init = tegra20_spi_init,
- .claim_bus = tegra20_spi_claim_bus,
- .cs_is_valid = tegra20_spi_cs_is_valid,
- .setup_slave = tegra20_spi_setup_slave,
- .free_slave = tegra20_spi_free_slave,
- .cs_activate = tegra20_spi_cs_activate,
- .cs_deactivate = tegra20_spi_cs_deactivate,
- .xfer = tegra20_spi_xfer,
- },
-#endif
-#ifdef CONFIG_TEGRA20_SLINK
- {
- .compat = COMPAT_NVIDIA_TEGRA20_SLINK,
- .max_ctrls = CONFIG_TEGRA_SLINK_CTRLS,
- .init = tegra30_spi_init,
- .claim_bus = tegra30_spi_claim_bus,
- .cs_is_valid = tegra30_spi_cs_is_valid,
- .setup_slave = tegra30_spi_setup_slave,
- .free_slave = tegra30_spi_free_slave,
- .cs_activate = tegra30_spi_cs_activate,
- .cs_deactivate = tegra30_spi_cs_deactivate,
- .xfer = tegra30_spi_xfer,
- },
-#endif
-#ifdef CONFIG_TEGRA114_SPI
- {
- .compat = COMPAT_NVIDIA_TEGRA114_SPI,
- .max_ctrls = CONFIG_TEGRA114_SPI_CTRLS,
- .init = tegra114_spi_init,
- .claim_bus = tegra114_spi_claim_bus,
- .cs_is_valid = tegra114_spi_cs_is_valid,
- .setup_slave = tegra114_spi_setup_slave,
- .free_slave = tegra114_spi_free_slave,
- .cs_activate = tegra114_spi_cs_activate,
- .cs_deactivate = tegra114_spi_cs_deactivate,
- .xfer = tegra114_spi_xfer,
- },
-#endif
-};
-
-static struct fdt_spi_driver *driver;
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- if (!driver)
- return 0;
- else if (!driver->cs_is_valid)
- return 1;
- else
- return driver->cs_is_valid(bus, cs);
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- if (!driver || !driver->setup_slave)
- return NULL;
-
- return driver->setup_slave(bus, cs, max_hz, mode);
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- if (driver && driver->free_slave)
- return driver->free_slave(slave);
-}
-
-static int spi_init_driver(struct fdt_spi_driver *driver)
-{
- int count;
- int node_list[driver->max_ctrls];
-
- count = fdtdec_find_aliases_for_id(gd->fdt_blob, "spi",
- driver->compat,
- node_list,
- driver->max_ctrls);
- return driver->init(node_list, count);
-}
-
-void spi_init(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(fdt_spi_drivers); i++) {
- driver = &fdt_spi_drivers[i];
- if (!spi_init_driver(driver))
- break;
- }
- if (i == ARRAY_SIZE(fdt_spi_drivers))
- driver = NULL;
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- if (!driver)
- return 1;
- if (!driver->claim_bus)
- return 0;
-
- return driver->claim_bus(slave);
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
- if (driver && driver->release_bus)
- driver->release_bus(slave);
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- if (driver && driver->cs_activate)
- driver->cs_activate(slave);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- if (driver && driver->cs_deactivate)
- driver->cs_deactivate(slave);
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *data_out, void *data_in, unsigned long flags)
-{
- if (!driver || !driver->xfer)
- return -1;
-
- return driver->xfer(slave, bitlen, data_out, data_in, flags);
-}
diff --git a/drivers/spi/sandbox_spi.c b/drivers/spi/sandbox_spi.c
index 12e9bda..e717424 100644
--- a/drivers/spi/sandbox_spi.c
+++ b/drivers/spi/sandbox_spi.c
@@ -9,26 +9,23 @@
*/
#include <common.h>
+#include <dm.h>
#include <malloc.h>
#include <spi.h>
+#include <spi_flash.h>
#include <os.h>
#include <asm/errno.h>
#include <asm/spi.h>
#include <asm/state.h>
+#include <dm/device-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SPI_IDLE_VAL
# define CONFIG_SPI_IDLE_VAL 0xFF
#endif
-struct sandbox_spi_slave {
- struct spi_slave slave;
- const struct sandbox_spi_emu_ops *ops;
- void *priv;
-};
-
-#define to_sandbox_spi_slave(s) container_of(s, struct sandbox_spi_slave, slave)
-
const char *sandbox_spi_parse_spec(const char *arg, unsigned long *bus,
unsigned long *cs)
{
@@ -45,120 +42,52 @@ const char *sandbox_spi_parse_spec(const char *arg, unsigned long *bus,
return endp + 1;
}
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus < CONFIG_SANDBOX_SPI_MAX_BUS &&
- cs < CONFIG_SANDBOX_SPI_MAX_CS;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- struct sandbox_spi_slave *sss = to_sandbox_spi_slave(slave);
-
- debug("sandbox_spi: activating CS\n");
- if (sss->ops->cs_activate)
- sss->ops->cs_activate(sss->priv);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct sandbox_spi_slave *sss = to_sandbox_spi_slave(slave);
-
- debug("sandbox_spi: deactivating CS\n");
- if (sss->ops->cs_deactivate)
- sss->ops->cs_deactivate(sss->priv);
-}
-
-void spi_init(void)
-{
-}
-
-void spi_set_speed(struct spi_slave *slave, uint hz)
+__weak int sandbox_spi_get_emul(struct sandbox_state *state,
+ struct udevice *bus, struct udevice *slave,
+ struct udevice **emulp)
{
+ return -ENOENT;
}
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static int sandbox_spi_xfer(struct udevice *slave, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
{
- struct sandbox_spi_slave *sss;
+ struct udevice *bus = slave->parent;
struct sandbox_state *state = state_get_current();
- const char *spec;
-
- if (!spi_cs_is_valid(bus, cs)) {
- debug("sandbox_spi: Invalid SPI bus/cs\n");
- return NULL;
- }
-
- sss = spi_alloc_slave(struct sandbox_spi_slave, bus, cs);
- if (!sss) {
- debug("sandbox_spi: Out of memory\n");
- return NULL;
- }
-
- spec = state->spi[bus][cs].spec;
- sss->ops = state->spi[bus][cs].ops;
- if (!spec || !sss->ops || sss->ops->setup(&sss->priv, spec)) {
- free(sss);
- printf("sandbox_spi: unable to locate a slave client\n");
- return NULL;
- }
-
- return &sss->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct sandbox_spi_slave *sss = to_sandbox_spi_slave(slave);
-
- debug("sandbox_spi: releasing slave\n");
-
- if (sss->ops->free)
- sss->ops->free(sss->priv);
-
- free(sss);
-}
-
-static int spi_bus_claim_cnt[CONFIG_SANDBOX_SPI_MAX_BUS];
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- if (spi_bus_claim_cnt[slave->bus]++) {
- printf("sandbox_spi: error: bus already claimed: %d!\n",
- spi_bus_claim_cnt[slave->bus]);
- }
-
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
- if (--spi_bus_claim_cnt[slave->bus]) {
- printf("sandbox_spi: error: bus freed too often: %d!\n",
- spi_bus_claim_cnt[slave->bus]);
- }
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
-{
- struct sandbox_spi_slave *sss = to_sandbox_spi_slave(slave);
+ struct dm_spi_emul_ops *ops;
+ struct udevice *emul;
uint bytes = bitlen / 8, i;
- int ret = 0;
+ int ret;
u8 *tx = (void *)dout, *rx = din;
+ uint busnum, cs;
if (bitlen == 0)
- goto done;
+ return 0;
/* we can only do 8 bit transfers */
if (bitlen % 8) {
printf("sandbox_spi: xfer: invalid bitlen size %u; needs to be 8bit\n",
bitlen);
- flags |= SPI_XFER_END;
- goto done;
+ return -EINVAL;
}
- if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
+ busnum = bus->seq;
+ cs = spi_chip_select(slave);
+ if (busnum >= CONFIG_SANDBOX_SPI_MAX_BUS ||
+ cs >= CONFIG_SANDBOX_SPI_MAX_CS) {
+ printf("%s: busnum=%u, cs=%u: out of range\n", __func__,
+ busnum, cs);
+ return -ENOENT;
+ }
+ ret = sandbox_spi_get_emul(state, bus, slave, &emul);
+ if (ret) {
+ printf("%s: busnum=%u, cs=%u: no emulation available (err=%d)\n",
+ __func__, busnum, cs, ret);
+ return -ENOENT;
+ }
+ ret = device_probe(emul);
+ if (ret)
+ return ret;
/* make sure rx/tx buffers are full so clients can assume */
if (!tx) {
@@ -178,12 +107,8 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
}
}
- debug("sandbox_spi: xfer: bytes = %u\n tx:", bytes);
- for (i = 0; i < bytes; ++i)
- debug(" %u:%02x", i, tx[i]);
- debug("\n");
-
- ret = sss->ops->xfer(sss->priv, tx, rx, bytes);
+ ops = spi_emul_get_ops(emul);
+ ret = ops->xfer(emul, bitlen, dout, din, flags);
debug("sandbox_spi: xfer: got back %i (that's %s)\n rx:",
ret, ret ? "bad" : "good");
@@ -196,22 +121,45 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
if (rx != din)
free(rx);
- done:
- if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
-
return ret;
}
-/**
- * Set up a new SPI slave for an fdt node
- *
- * @param blob Device tree blob
- * @param node SPI peripheral node to use
- * @return 0 if ok, -1 on error
- */
-struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
- int spi_node)
+static int sandbox_spi_set_speed(struct udevice *bus, uint speed)
+{
+ return 0;
+}
+
+static int sandbox_spi_set_mode(struct udevice *bus, uint mode)
+{
+ return 0;
+}
+
+static int sandbox_cs_info(struct udevice *bus, uint cs,
+ struct spi_cs_info *info)
{
- return NULL;
+ /* Always allow activity on CS 0 */
+ if (cs >= 1)
+ return -ENODEV;
+
+ return 0;
}
+
+static const struct dm_spi_ops sandbox_spi_ops = {
+ .xfer = sandbox_spi_xfer,
+ .set_speed = sandbox_spi_set_speed,
+ .set_mode = sandbox_spi_set_mode,
+ .cs_info = sandbox_cs_info,
+};
+
+static const struct udevice_id sandbox_spi_ids[] = {
+ { .compatible = "sandbox,spi" },
+ { }
+};
+
+U_BOOT_DRIVER(spi_sandbox) = {
+ .name = "spi_sandbox",
+ .id = UCLASS_SPI,
+ .of_match = sandbox_spi_ids,
+ .per_child_auto_alloc_size = sizeof(struct spi_slave),
+ .ops = &sandbox_spi_ops,
+};
diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c
index c969be3..5588036 100644
--- a/drivers/spi/soft_spi.c
+++ b/drivers/spi/soft_spi.c
@@ -1,4 +1,6 @@
/*
+ * Copyright (c) 2014 Google, Inc
+ *
* (C) Copyright 2002
* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
*
@@ -9,94 +11,81 @@
*/
#include <common.h>
-#include <spi.h>
-
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
#include <malloc.h>
+#include <spi.h>
+#include <asm/gpio.h>
-/*-----------------------------------------------------------------------
- * Definitions
- */
+DECLARE_GLOBAL_DATA_PTR;
-#ifdef DEBUG_SPI
-#define PRINTD(fmt,args...) printf (fmt ,##args)
-#else
-#define PRINTD(fmt,args...)
-#endif
+struct soft_spi_platdata {
+ struct fdt_gpio_state cs;
+ struct fdt_gpio_state sclk;
+ struct fdt_gpio_state mosi;
+ struct fdt_gpio_state miso;
+ int spi_delay_us;
+};
-struct soft_spi_slave {
- struct spi_slave slave;
+struct soft_spi_priv {
unsigned int mode;
};
-static inline struct soft_spi_slave *to_soft_spi(struct spi_slave *slave)
+static int soft_spi_scl(struct udevice *dev, int bit)
{
- return container_of(slave, struct soft_spi_slave, slave);
-}
+ struct soft_spi_platdata *plat = dev->platdata;
+ struct soft_spi_priv *priv = dev_get_priv(dev);
-/*=====================================================================*/
-/* Public Functions */
-/*=====================================================================*/
+ gpio_set_value(plat->sclk.gpio, priv->mode & SPI_CPOL ? bit : !bit);
-/*-----------------------------------------------------------------------
- * Initialization
- */
-void spi_init (void)
-{
-#ifdef SPI_INIT
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-
- SPI_INIT;
-#endif
+ return 0;
}
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static int soft_spi_sda(struct udevice *dev, int bit)
{
- struct soft_spi_slave *ss;
+ struct soft_spi_platdata *plat = dev->platdata;
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
+ gpio_set_value(plat->mosi.gpio, bit);
- ss = spi_alloc_slave(struct soft_spi_slave, bus, cs);
- if (!ss)
- return NULL;
+ return 0;
+}
- ss->mode = mode;
+static int soft_spi_cs_activate(struct udevice *dev)
+{
+ struct soft_spi_platdata *plat = dev->platdata;
+ struct soft_spi_priv *priv = dev_get_priv(dev);
- /* TODO: Use max_hz to limit the SCK rate */
+ gpio_set_value(plat->cs.gpio, !(priv->mode & SPI_CS_HIGH));
+ gpio_set_value(plat->sclk.gpio, priv->mode & SPI_CPOL);
+ gpio_set_value(plat->cs.gpio, priv->mode & SPI_CS_HIGH);
- return &ss->slave;
+ return 0;
}
-void spi_free_slave(struct spi_slave *slave)
+static int soft_spi_cs_deactivate(struct udevice *dev)
{
- struct soft_spi_slave *ss = to_soft_spi(slave);
+ struct soft_spi_platdata *plat = dev->platdata;
+ struct soft_spi_priv *priv = dev_get_priv(dev);
- free(ss);
+ gpio_set_value(plat->cs.gpio, !(priv->mode & SPI_CS_HIGH));
+
+ return 0;
}
-int spi_claim_bus(struct spi_slave *slave)
+static int soft_spi_claim_bus(struct udevice *dev)
{
-#ifdef CONFIG_SYS_IMMR
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-#endif
- struct soft_spi_slave *ss = to_soft_spi(slave);
-
/*
* Make sure the SPI clock is in idle state as defined for
* this slave.
*/
- if (ss->mode & SPI_CPOL)
- SPI_SCL(1);
- else
- SPI_SCL(0);
-
- return 0;
+ return soft_spi_scl(dev, 0);
}
-void spi_release_bus(struct spi_slave *slave)
+static int soft_spi_release_bus(struct udevice *dev)
{
/* Nothing to do */
+ return 0;
}
/*-----------------------------------------------------------------------
@@ -111,28 +100,27 @@ void spi_release_bus(struct spi_slave *slave)
* input data overwrites the output data (since both are buffered by
* temporary variables, this is OK).
*/
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *dout, void *din, unsigned long flags)
+static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
{
-#ifdef CONFIG_SYS_IMMR
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-#endif
- struct soft_spi_slave *ss = to_soft_spi(slave);
+ struct soft_spi_priv *priv = dev_get_priv(dev);
+ struct soft_spi_platdata *plat = dev->platdata;
uchar tmpdin = 0;
uchar tmpdout = 0;
const u8 *txd = dout;
u8 *rxd = din;
- int cpol = ss->mode & SPI_CPOL;
- int cpha = ss->mode & SPI_CPHA;
+ int cpol = priv->mode & SPI_CPOL;
+ int cpha = priv->mode & SPI_CPHA;
unsigned int j;
- PRINTD("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
- slave->bus, slave->cs, *(uint *)txd, *(uint *)rxd, bitlen);
+ debug("spi_xfer: slave %s:%s dout %08X din %08X bitlen %u\n",
+ dev->parent->name, dev->name, *(uint *)txd, *(uint *)rxd,
+ bitlen);
if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
+ soft_spi_cs_activate(dev);
- for(j = 0; j < bitlen; j++) {
+ for (j = 0; j < bitlen; j++) {
/*
* Check if it is time to work on a new byte.
*/
@@ -141,7 +129,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
tmpdout = *txd++;
else
tmpdout = 0;
- if(j != 0) {
+ if (j != 0) {
if (rxd)
*rxd++ = tmpdin;
}
@@ -149,19 +137,19 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
}
if (!cpha)
- SPI_SCL(!cpol);
- SPI_SDA(tmpdout & 0x80);
- SPI_DELAY;
+ soft_spi_scl(dev, !cpol);
+ soft_spi_sda(dev, tmpdout & 0x80);
+ udelay(plat->spi_delay_us);
if (cpha)
- SPI_SCL(!cpol);
+ soft_spi_scl(dev, !cpol);
else
- SPI_SCL(cpol);
+ soft_spi_scl(dev, cpol);
tmpdin <<= 1;
- tmpdin |= SPI_READ;
+ tmpdin |= gpio_get_value(plat->miso.gpio);
tmpdout <<= 1;
- SPI_DELAY;
+ udelay(plat->spi_delay_us);
if (cpha)
- SPI_SCL(cpol);
+ soft_spi_scl(dev, cpol);
}
/*
* If the number of bits isn't a multiple of 8, shift the last
@@ -175,7 +163,90 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
}
if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
+ soft_spi_cs_deactivate(dev);
- return(0);
+ return 0;
}
+
+static int soft_spi_set_speed(struct udevice *dev, unsigned int speed)
+{
+ /* Accept any speed */
+ return 0;
+}
+
+static int soft_spi_set_mode(struct udevice *dev, unsigned int mode)
+{
+ struct soft_spi_priv *priv = dev_get_priv(dev);
+
+ priv->mode = mode;
+
+ return 0;
+}
+
+static int soft_spi_child_pre_probe(struct udevice *dev)
+{
+ struct spi_slave *slave = dev_get_parentdata(dev);
+
+ slave->dev = dev;
+ return spi_ofdata_to_platdata(gd->fdt_blob, dev->of_offset, slave);
+}
+
+static const struct dm_spi_ops soft_spi_ops = {
+ .claim_bus = soft_spi_claim_bus,
+ .release_bus = soft_spi_release_bus,
+ .xfer = soft_spi_xfer,
+ .set_speed = soft_spi_set_speed,
+ .set_mode = soft_spi_set_mode,
+};
+
+static int soft_spi_ofdata_to_platdata(struct udevice *dev)
+{
+ struct soft_spi_platdata *plat = dev->platdata;
+ const void *blob = gd->fdt_blob;
+ int node = dev->of_offset;
+
+ if (fdtdec_decode_gpio(blob, node, "cs-gpio", &plat->cs) ||
+ fdtdec_decode_gpio(blob, node, "sclk-gpio", &plat->sclk) ||
+ fdtdec_decode_gpio(blob, node, "mosi-gpio", &plat->mosi) ||
+ fdtdec_decode_gpio(blob, node, "miso-gpio", &plat->miso))
+ return -EINVAL;
+ plat->spi_delay_us = fdtdec_get_int(blob, node, "spi-delay-us", 0);
+
+ return 0;
+}
+
+static int soft_spi_probe(struct udevice *dev)
+{
+ struct spi_slave *slave = dev_get_parentdata(dev);
+ struct soft_spi_platdata *plat = dev->platdata;
+
+ gpio_request(plat->cs.gpio, "soft_spi_cs");
+ gpio_request(plat->sclk.gpio, "soft_spi_sclk");
+ gpio_request(plat->mosi.gpio, "soft_spi_mosi");
+ gpio_request(plat->miso.gpio, "soft_spi_miso");
+
+ gpio_direction_output(plat->sclk.gpio, slave->mode & SPI_CPOL);
+ gpio_direction_output(plat->mosi.gpio, 1);
+ gpio_direction_input(plat->miso.gpio);
+ gpio_direction_output(plat->cs.gpio, !(slave->mode & SPI_CS_HIGH));
+
+ return 0;
+}
+
+static const struct udevice_id soft_spi_ids[] = {
+ { .compatible = "u-boot,soft-spi" },
+ { }
+};
+
+U_BOOT_DRIVER(soft_spi) = {
+ .name = "soft_spi",
+ .id = UCLASS_SPI,
+ .of_match = soft_spi_ids,
+ .ops = &soft_spi_ops,
+ .ofdata_to_platdata = soft_spi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct soft_spi_platdata),
+ .priv_auto_alloc_size = sizeof(struct soft_spi_priv),
+ .per_child_auto_alloc_size = sizeof(struct spi_slave),
+ .probe = soft_spi_probe,
+ .child_pre_probe = soft_spi_child_pre_probe,
+};
diff --git a/drivers/spi/soft_spi_legacy.c b/drivers/spi/soft_spi_legacy.c
new file mode 100644
index 0000000..941daa7
--- /dev/null
+++ b/drivers/spi/soft_spi_legacy.c
@@ -0,0 +1,176 @@
+/*
+ * (C) Copyright 2002
+ * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
+ *
+ * Influenced by code from:
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi.h>
+
+#include <malloc.h>
+
+/*-----------------------------------------------------------------------
+ * Definitions
+ */
+
+#ifdef DEBUG_SPI
+#define PRINTD(fmt,args...) printf (fmt ,##args)
+#else
+#define PRINTD(fmt,args...)
+#endif
+
+struct soft_spi_slave {
+ struct spi_slave slave;
+ unsigned int mode;
+};
+
+static inline struct soft_spi_slave *to_soft_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct soft_spi_slave, slave);
+}
+
+/*=====================================================================*/
+/* Public Functions */
+/*=====================================================================*/
+
+/*-----------------------------------------------------------------------
+ * Initialization
+ */
+void spi_init (void)
+{
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct soft_spi_slave *ss;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ ss = spi_alloc_slave(struct soft_spi_slave, bus, cs);
+ if (!ss)
+ return NULL;
+
+ ss->mode = mode;
+
+ /* TODO: Use max_hz to limit the SCK rate */
+
+ return &ss->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct soft_spi_slave *ss = to_soft_spi(slave);
+
+ free(ss);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+#ifdef CONFIG_SYS_IMMR
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+#endif
+ struct soft_spi_slave *ss = to_soft_spi(slave);
+
+ /*
+ * Make sure the SPI clock is in idle state as defined for
+ * this slave.
+ */
+ if (ss->mode & SPI_CPOL)
+ SPI_SCL(1);
+ else
+ SPI_SCL(0);
+
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ /* Nothing to do */
+}
+
+/*-----------------------------------------------------------------------
+ * SPI transfer
+ *
+ * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks
+ * "bitlen" bits in the SPI MISO port. That's just the way SPI works.
+ *
+ * The source of the outgoing bits is the "dout" parameter and the
+ * destination of the input bits is the "din" parameter. Note that "dout"
+ * and "din" can point to the same memory location, in which case the
+ * input data overwrites the output data (since both are buffered by
+ * temporary variables, this is OK).
+ */
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+#ifdef CONFIG_SYS_IMMR
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+#endif
+ struct soft_spi_slave *ss = to_soft_spi(slave);
+ uchar tmpdin = 0;
+ uchar tmpdout = 0;
+ const u8 *txd = dout;
+ u8 *rxd = din;
+ int cpol = ss->mode & SPI_CPOL;
+ int cpha = ss->mode & SPI_CPHA;
+ unsigned int j;
+
+ PRINTD("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
+ slave->bus, slave->cs, *(uint *)txd, *(uint *)rxd, bitlen);
+
+ if (flags & SPI_XFER_BEGIN)
+ spi_cs_activate(slave);
+
+ for(j = 0; j < bitlen; j++) {
+ /*
+ * Check if it is time to work on a new byte.
+ */
+ if ((j % 8) == 0) {
+ if (txd)
+ tmpdout = *txd++;
+ else
+ tmpdout = 0;
+ if(j != 0) {
+ if (rxd)
+ *rxd++ = tmpdin;
+ }
+ tmpdin = 0;
+ }
+
+ if (!cpha)
+ SPI_SCL(!cpol);
+ SPI_SDA(tmpdout & 0x80);
+ SPI_DELAY;
+ if (cpha)
+ SPI_SCL(!cpol);
+ else
+ SPI_SCL(cpol);
+ tmpdin <<= 1;
+ tmpdin |= SPI_READ;
+ tmpdout <<= 1;
+ SPI_DELAY;
+ if (cpha)
+ SPI_SCL(cpol);
+ }
+ /*
+ * If the number of bits isn't a multiple of 8, shift the last
+ * bits over to left-justify them. Then store the last byte
+ * read in.
+ */
+ if (rxd) {
+ if ((bitlen % 8) != 0)
+ tmpdin <<= 8 - (bitlen % 8);
+ *rxd++ = tmpdin;
+ }
+
+ if (flags & SPI_XFER_END)
+ spi_cs_deactivate(slave);
+
+ return(0);
+}
diff --git a/drivers/spi/spi-emul-uclass.c b/drivers/spi/spi-emul-uclass.c
new file mode 100644
index 0000000..b436a0e
--- /dev/null
+++ b/drivers/spi/spi-emul-uclass.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spi.h>
+#include <spi_flash.h>
+
+UCLASS_DRIVER(spi_emul) = {
+ .id = UCLASS_SPI_EMUL,
+ .name = "spi_emul",
+};
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
new file mode 100644
index 0000000..13c6b77
--- /dev/null
+++ b/drivers/spi/spi-uclass.c
@@ -0,0 +1,390 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <spi.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
+#include <dm/root.h>
+#include <dm/lists.h>
+#include <dm/util.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int spi_set_speed_mode(struct udevice *bus, int speed, int mode)
+{
+ struct dm_spi_ops *ops;
+ int ret;
+
+ ops = spi_get_ops(bus);
+ if (ops->set_speed)
+ ret = ops->set_speed(bus, speed);
+ else
+ ret = -EINVAL;
+ if (ret) {
+ printf("Cannot set speed (err=%d)\n", ret);
+ return ret;
+ }
+
+ if (ops->set_mode)
+ ret = ops->set_mode(bus, mode);
+ else
+ ret = -EINVAL;
+ if (ret) {
+ printf("Cannot set mode (err=%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct udevice *dev = slave->dev;
+ struct udevice *bus = dev->parent;
+ struct dm_spi_ops *ops = spi_get_ops(bus);
+ struct dm_spi_bus *spi = bus->uclass_priv;
+ int speed;
+ int ret;
+
+ speed = slave->max_hz;
+ if (spi->max_hz) {
+ if (speed)
+ speed = min(speed, spi->max_hz);
+ else
+ speed = spi->max_hz;
+ }
+ if (!speed)
+ speed = 100000;
+ ret = spi_set_speed_mode(bus, speed, slave->mode);
+ if (ret)
+ return ret;
+
+ return ops->claim_bus ? ops->claim_bus(bus) : 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ struct udevice *dev = slave->dev;
+ struct udevice *bus = dev->parent;
+ struct dm_spi_ops *ops = spi_get_ops(bus);
+
+ if (ops->release_bus)
+ ops->release_bus(bus);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *dev = slave->dev;
+ struct udevice *bus = dev->parent;
+
+ if (bus->uclass->uc_drv->id != UCLASS_SPI)
+ return -EOPNOTSUPP;
+
+ return spi_get_ops(bus)->xfer(dev, bitlen, dout, din, flags);
+}
+
+int spi_post_bind(struct udevice *dev)
+{
+ /* Scan the bus for devices */
+ return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+}
+
+int spi_post_probe(struct udevice *dev)
+{
+ struct dm_spi_bus *spi = dev->uclass_priv;
+
+ spi->max_hz = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "spi-max-frequency", 0);
+
+ return 0;
+}
+
+int spi_chip_select(struct udevice *dev)
+{
+ struct spi_slave *slave = dev_get_parentdata(dev);
+
+ return slave ? slave->cs : -ENOENT;
+}
+
+/**
+ * spi_find_chip_select() - Find the slave attached to chip select
+ *
+ * @bus: SPI bus to search
+ * @cs: Chip select to look for
+ * @devp: Returns the slave device if found
+ * @return 0 if found, -ENODEV on error
+ */
+static int spi_find_chip_select(struct udevice *bus, int cs,
+ struct udevice **devp)
+{
+ struct udevice *dev;
+
+ for (device_find_first_child(bus, &dev); dev;
+ device_find_next_child(&dev)) {
+ struct spi_slave store;
+ struct spi_slave *slave = dev_get_parentdata(dev);
+
+ if (!slave) {
+ slave = &store;
+ spi_ofdata_to_platdata(gd->fdt_blob, dev->of_offset,
+ slave);
+ }
+ debug("%s: slave=%p, cs=%d\n", __func__, slave,
+ slave ? slave->cs : -1);
+ if (slave && slave->cs == cs) {
+ *devp = dev;
+ return 0;
+ }
+ }
+
+ return -ENODEV;
+}
+
+int spi_cs_is_valid(unsigned int busnum, unsigned int cs)
+{
+ struct spi_cs_info info;
+ struct udevice *bus;
+ int ret;
+
+ ret = uclass_find_device_by_seq(UCLASS_SPI, busnum, false, &bus);
+ if (ret) {
+ debug("%s: No bus %d\n", __func__, busnum);
+ return ret;
+ }
+
+ return spi_cs_info(bus, cs, &info);
+}
+
+int spi_cs_info(struct udevice *bus, uint cs, struct spi_cs_info *info)
+{
+ struct spi_cs_info local_info;
+ struct dm_spi_ops *ops;
+ int ret;
+
+ if (!info)
+ info = &local_info;
+
+ /* If there is a device attached, return it */
+ info->dev = NULL;
+ ret = spi_find_chip_select(bus, cs, &info->dev);
+ if (!ret)
+ return 0;
+
+ /*
+ * Otherwise ask the driver. For the moment we don't have CS info.
+ * When we do we could provide the driver with a helper function
+ * to figure out what chip selects are valid, or just handle the
+ * request.
+ */
+ ops = spi_get_ops(bus);
+ if (ops->cs_info)
+ return ops->cs_info(bus, cs, info);
+
+ /*
+ * We could assume there is at least one valid chip select, but best
+ * to be sure and return an error in this case. The driver didn't
+ * care enough to tell us.
+ */
+ return -ENODEV;
+}
+
+int spi_bind_device(struct udevice *bus, int cs, const char *drv_name,
+ const char *dev_name, struct udevice **devp)
+{
+ struct driver *drv;
+ int ret;
+
+ drv = lists_driver_lookup_name(drv_name);
+ if (!drv) {
+ printf("Cannot find driver '%s'\n", drv_name);
+ return -ENOENT;
+ }
+ ret = device_bind(bus, drv, dev_name, NULL, -1, devp);
+ if (ret) {
+ printf("Cannot create device named '%s' (err=%d)\n",
+ dev_name, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp,
+ struct udevice **devp)
+{
+ struct udevice *bus, *dev;
+ int ret;
+
+ ret = uclass_find_device_by_seq(UCLASS_SPI, busnum, false, &bus);
+ if (ret) {
+ debug("%s: No bus %d\n", __func__, busnum);
+ return ret;
+ }
+ ret = spi_find_chip_select(bus, cs, &dev);
+ if (ret) {
+ debug("%s: No cs %d\n", __func__, cs);
+ return ret;
+ }
+ *busp = bus;
+ *devp = dev;
+
+ return ret;
+}
+
+int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode,
+ const char *drv_name, const char *dev_name,
+ struct udevice **busp, struct spi_slave **devp)
+{
+ struct udevice *bus, *dev;
+ struct spi_slave *slave;
+ bool created = false;
+ int ret;
+
+ ret = uclass_get_device_by_seq(UCLASS_SPI, busnum, &bus);
+ if (ret) {
+ printf("Invalid bus %d (err=%d)\n", busnum, ret);
+ return ret;
+ }
+ ret = spi_find_chip_select(bus, cs, &dev);
+
+ /*
+ * If there is no such device, create one automatically. This means
+ * that we don't need a device tree node or platform data for the
+ * SPI flash chip - we will bind to the correct driver.
+ */
+ if (ret == -ENODEV && drv_name) {
+ debug("%s: Binding new device '%s', busnum=%d, cs=%d, driver=%s\n",
+ __func__, dev_name, busnum, cs, drv_name);
+ ret = spi_bind_device(bus, cs, drv_name, dev_name, &dev);
+ if (ret)
+ return ret;
+ created = true;
+ } else if (ret) {
+ printf("Invalid chip select %d:%d (err=%d)\n", busnum, cs,
+ ret);
+ return ret;
+ }
+
+ if (!device_active(dev)) {
+ slave = (struct spi_slave *)calloc(1,
+ sizeof(struct spi_slave));
+ if (!slave) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ ret = spi_ofdata_to_platdata(gd->fdt_blob, dev->of_offset,
+ slave);
+ if (ret)
+ goto err;
+ slave->cs = cs;
+ slave->dev = dev;
+ ret = device_probe_child(dev, slave);
+ free(slave);
+ if (ret)
+ goto err;
+ }
+
+ ret = spi_set_speed_mode(bus, speed, mode);
+ if (ret)
+ goto err;
+
+ *busp = bus;
+ *devp = dev_get_parentdata(dev);
+ debug("%s: bus=%p, slave=%p\n", __func__, bus, *devp);
+
+ return 0;
+
+err:
+ if (created) {
+ device_remove(dev);
+ device_unbind(dev);
+ }
+
+ return ret;
+}
+
+/* Compatibility function - to be removed */
+struct spi_slave *spi_setup_slave_fdt(const void *blob, int node,
+ int bus_node)
+{
+ struct udevice *bus, *dev;
+ int ret;
+
+ ret = uclass_get_device_by_of_offset(UCLASS_SPI, bus_node, &bus);
+ if (ret)
+ return NULL;
+ ret = device_get_child_by_of_offset(bus, node, &dev);
+ if (ret)
+ return NULL;
+ return dev_get_parentdata(dev);
+}
+
+/* Compatibility function - to be removed */
+struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs,
+ unsigned int speed, unsigned int mode)
+{
+ struct spi_slave *slave;
+ struct udevice *dev;
+ int ret;
+
+ ret = spi_get_bus_and_cs(busnum, cs, speed, mode, NULL, 0, &dev,
+ &slave);
+ if (ret)
+ return NULL;
+
+ return slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ device_remove(slave->dev);
+ slave->dev = NULL;
+}
+
+int spi_ofdata_to_platdata(const void *blob, int node,
+ struct spi_slave *spi)
+{
+ int mode = 0;
+
+ spi->cs = fdtdec_get_int(blob, node, "reg", -1);
+ spi->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 0);
+ if (fdtdec_get_bool(blob, node, "spi-cpol"))
+ mode |= SPI_CPOL;
+ if (fdtdec_get_bool(blob, node, "spi-cpha"))
+ mode |= SPI_CPHA;
+ if (fdtdec_get_bool(blob, node, "spi-cs-high"))
+ mode |= SPI_CS_HIGH;
+ if (fdtdec_get_bool(blob, node, "spi-half-duplex"))
+ mode |= SPI_PREAMBLE;
+ spi->mode = mode;
+
+ return 0;
+}
+
+UCLASS_DRIVER(spi) = {
+ .id = UCLASS_SPI,
+ .name = "spi",
+ .post_bind = spi_post_bind,
+ .post_probe = spi_post_probe,
+ .per_device_auto_alloc_size = sizeof(struct dm_spi_bus),
+};
+
+UCLASS_DRIVER(spi_generic) = {
+ .id = UCLASS_SPI_GENERIC,
+ .name = "spi_generic",
+};
+
+U_BOOT_DRIVER(spi_generic_drv) = {
+ .name = "spi_generic_drv",
+ .id = UCLASS_SPI_GENERIC,
+};
diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index 810fa47..2d97625 100644
--- a/drivers/spi/tegra114_spi.c
+++ b/drivers/spi/tegra114_spi.c
@@ -22,14 +22,13 @@
*/
#include <common.h>
-#include <malloc.h>
+#include <dm.h>
#include <asm/io.h>
-#include <asm/gpio.h>
#include <asm/arch/clock.h>
#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra114/tegra114_spi.h>
#include <spi.h>
#include <fdtdec.h>
+#include "tegra_spi.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -104,130 +103,63 @@ struct spi_regs {
u32 spare_ctl; /* 18c:SPI_SPARE_CTRL register */
};
-struct tegra_spi_ctrl {
+struct tegra114_spi_priv {
struct spi_regs *regs;
unsigned int freq;
unsigned int mode;
int periph_id;
int valid;
+ int last_transaction_us;
};
-struct tegra_spi_slave {
- struct spi_slave slave;
- struct tegra_spi_ctrl *ctrl;
-};
-
-static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA114_SPI_CTRLS];
-
-static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
+static int tegra114_spi_ofdata_to_platdata(struct udevice *bus)
{
- return container_of(slave, struct tegra_spi_slave, slave);
-}
+ struct tegra_spi_platdata *plat = bus->platdata;
+ const void *blob = gd->fdt_blob;
+ int node = bus->of_offset;
-int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- if (bus >= CONFIG_TEGRA114_SPI_CTRLS || cs > 3 || !spi_ctrls[bus].valid)
- return 0;
- else
- return 1;
-}
+ plat->base = fdtdec_get_addr(blob, node, "reg");
+ plat->periph_id = clock_decode_periph_id(blob, node);
-struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct tegra_spi_slave *spi;
-
- debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__,
- bus, cs, max_hz, mode);
-
- if (!spi_cs_is_valid(bus, cs)) {
- printf("SPI error: unsupported bus %d / chip select %d\n",
- bus, cs);
- return NULL;
- }
-
- if (max_hz > TEGRA_SPI_MAX_FREQ) {
- printf("SPI error: unsupported frequency %d Hz. Max frequency"
- " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
- return NULL;
+ if (plat->periph_id == PERIPH_ID_NONE) {
+ debug("%s: could not decode periph id %d\n", __func__,
+ plat->periph_id);
+ return -FDT_ERR_NOTFOUND;
}
- spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs);
- if (!spi) {
- printf("SPI error: malloc of SPI structure failed\n");
- return NULL;
- }
- spi->ctrl = &spi_ctrls[bus];
- if (!spi->ctrl) {
- printf("SPI error: could not find controller for bus %d\n",
- bus);
- return NULL;
- }
+ /* Use 500KHz as a suitable default */
+ plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+ 500000);
+ plat->deactivate_delay_us = fdtdec_get_int(blob, node,
+ "spi-deactivate-delay", 0);
+ debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
+ __func__, plat->base, plat->periph_id, plat->frequency,
+ plat->deactivate_delay_us);
- if (max_hz < spi->ctrl->freq) {
- debug("%s: limiting frequency from %u to %u\n", __func__,
- spi->ctrl->freq, max_hz);
- spi->ctrl->freq = max_hz;
- }
- spi->ctrl->mode = mode;
-
- return &spi->slave;
-}
-
-void tegra114_spi_free_slave(struct spi_slave *slave)
-{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
-
- free(spi);
+ return 0;
}
-int tegra114_spi_init(int *node_list, int count)
+static int tegra114_spi_probe(struct udevice *bus)
{
- struct tegra_spi_ctrl *ctrl;
- int i;
- int node = 0;
- int found = 0;
-
- for (i = 0; i < count; i++) {
- ctrl = &spi_ctrls[i];
- node = node_list[i];
-
- ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
- node, "reg");
- if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
- debug("%s: no spi register found\n", __func__);
- continue;
- }
- ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
- "spi-max-frequency", 0);
- if (!ctrl->freq) {
- debug("%s: no spi max frequency found\n", __func__);
- continue;
- }
+ struct tegra_spi_platdata *plat = dev_get_platdata(bus);
+ struct tegra114_spi_priv *priv = dev_get_priv(bus);
- ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
- if (ctrl->periph_id == PERIPH_ID_NONE) {
- debug("%s: could not decode periph id\n", __func__);
- continue;
- }
- ctrl->valid = 1;
- found = 1;
+ priv->regs = (struct spi_regs *)plat->base;
- debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
- __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
- }
+ priv->last_transaction_us = timer_get_us();
+ priv->freq = plat->frequency;
+ priv->periph_id = plat->periph_id;
- return !found;
+ return 0;
}
-int tegra114_spi_claim_bus(struct spi_slave *slave)
+static int tegra114_spi_claim_bus(struct udevice *bus)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct tegra114_spi_priv *priv = dev_get_priv(bus);
+ struct spi_regs *regs = priv->regs;
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
- clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
- spi->ctrl->freq);
+ clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
/* Clear stale status here */
setbits_le32(&regs->fifo_status,
@@ -244,33 +176,64 @@ int tegra114_spi_claim_bus(struct spi_slave *slave)
/* Set master mode and sw controlled CS */
setbits_le32(&regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
- (spi->ctrl->mode << SPI_CMD1_MODE_SHIFT));
+ (priv->mode << SPI_CMD1_MODE_SHIFT));
debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1));
return 0;
}
-void tegra114_spi_cs_activate(struct spi_slave *slave)
+/**
+ * Activate the CS by driving it LOW
+ *
+ * @param slave Pointer to spi_slave to which controller has to
+ * communicate with
+ */
+static void spi_cs_activate(struct udevice *dev)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct udevice *bus = dev->parent;
+ struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+ struct tegra114_spi_priv *priv = dev_get_priv(bus);
+
+ /* If it's too soon to do another transaction, wait */
+ if (pdata->deactivate_delay_us &&
+ priv->last_transaction_us) {
+ ulong delay_us; /* The delay completed so far */
+ delay_us = timer_get_us() - priv->last_transaction_us;
+ if (delay_us < pdata->deactivate_delay_us)
+ udelay(pdata->deactivate_delay_us - delay_us);
+ }
- clrbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL);
+ clrbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
}
-void tegra114_spi_cs_deactivate(struct spi_slave *slave)
+/**
+ * Deactivate the CS by driving it HIGH
+ *
+ * @param slave Pointer to spi_slave to which controller has to
+ * communicate with
+ */
+static void spi_cs_deactivate(struct udevice *dev)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct udevice *bus = dev->parent;
+ struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+ struct tegra114_spi_priv *priv = dev_get_priv(bus);
+
+ setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
- setbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL);
+ /* Remember time of this transaction so we can honour the bus delay */
+ if (pdata->deactivate_delay_us)
+ priv->last_transaction_us = timer_get_us();
+
+ debug("Deactivate CS, bus '%s'\n", bus->name);
}
-int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *data_out, void *data_in, unsigned long flags)
+static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *data_out, void *data_in,
+ unsigned long flags)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct udevice *bus = dev->parent;
+ struct tegra114_spi_priv *priv = dev_get_priv(bus);
+ struct spi_regs *regs = priv->regs;
u32 reg, tmpdout, tmpdin = 0;
const u8 *dout = data_out;
u8 *din = data_in;
@@ -278,7 +241,7 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
int ret;
debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
- __func__, slave->bus, slave->cs, dout, din, bitlen);
+ __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
if (bitlen % 8)
return -1;
num_bytes = bitlen / 8;
@@ -291,13 +254,13 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
clrsetbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL,
SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE |
- (slave->cs << SPI_CMD1_CS_SEL_SHIFT));
+ (spi_chip_select(dev) << SPI_CMD1_CS_SEL_SHIFT));
/* set xfer size to 1 block (32 bits) */
writel(0, &regs->dma_blk);
if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
+ spi_cs_activate(dev);
/* handle data in 32-bit chunks */
while (num_bytes > 0) {
@@ -383,7 +346,7 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
}
if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
+ spi_cs_deactivate(dev);
debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
__func__, tmpdin, readl(&regs->fifo_status));
@@ -394,5 +357,56 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
return -1;
}
+ return ret;
+}
+
+static int tegra114_spi_set_speed(struct udevice *bus, uint speed)
+{
+ struct tegra_spi_platdata *plat = bus->platdata;
+ struct tegra114_spi_priv *priv = dev_get_priv(bus);
+
+ if (speed > plat->frequency)
+ speed = plat->frequency;
+ priv->freq = speed;
+ debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
+
return 0;
}
+
+static int tegra114_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct tegra114_spi_priv *priv = dev_get_priv(bus);
+
+ priv->mode = mode;
+ debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
+
+ return 0;
+}
+
+static const struct dm_spi_ops tegra114_spi_ops = {
+ .claim_bus = tegra114_spi_claim_bus,
+ .xfer = tegra114_spi_xfer,
+ .set_speed = tegra114_spi_set_speed,
+ .set_mode = tegra114_spi_set_mode,
+ /*
+ * cs_info is not needed, since we require all chip selects to be
+ * in the device tree explicitly
+ */
+};
+
+static const struct udevice_id tegra114_spi_ids[] = {
+ { .compatible = "nvidia,tegra114-spi" },
+ { }
+};
+
+U_BOOT_DRIVER(tegra114_spi) = {
+ .name = "tegra114_spi",
+ .id = UCLASS_SPI,
+ .of_match = tegra114_spi_ids,
+ .ops = &tegra114_spi_ops,
+ .ofdata_to_platdata = tegra114_spi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
+ .priv_auto_alloc_size = sizeof(struct tegra114_spi_priv),
+ .per_child_auto_alloc_size = sizeof(struct spi_slave),
+ .probe = tegra114_spi_probe,
+};
diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index b5d561b..7d0d0f3 100644
--- a/drivers/spi/tegra20_sflash.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -7,15 +7,16 @@
*/
#include <common.h>
-#include <malloc.h>
+#include <dm.h>
+#include <errno.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/clock.h>
#include <asm/arch/pinmux.h>
#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra20/tegra20_sflash.h>
#include <spi.h>
#include <fdtdec.h>
+#include "tegra_spi.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -64,129 +65,75 @@ struct spi_regs {
u32 rx_fifo; /* SPI_RX_FIFO_0 register */
};
-struct tegra_spi_ctrl {
+struct tegra20_sflash_priv {
struct spi_regs *regs;
unsigned int freq;
unsigned int mode;
int periph_id;
int valid;
+ int last_transaction_us;
};
-struct tegra_spi_slave {
- struct spi_slave slave;
- struct tegra_spi_ctrl *ctrl;
-};
-
-/* tegra20 only supports one SFLASH controller */
-static struct tegra_spi_ctrl spi_ctrls[1];
-
-static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
-{
- return container_of(slave, struct tegra_spi_slave, slave);
-}
-
-int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs)
+int tegra20_sflash_cs_info(struct udevice *bus, unsigned int cs,
+ struct spi_cs_info *info)
{
/* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
- if (bus != 0 || cs != 0)
- return 0;
+ if (cs != 0)
+ return -ENODEV;
else
- return 1;
+ return 0;
}
-struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static int tegra20_sflash_ofdata_to_platdata(struct udevice *bus)
{
- struct tegra_spi_slave *spi;
+ struct tegra_spi_platdata *plat = bus->platdata;
+ const void *blob = gd->fdt_blob;
+ int node = bus->of_offset;
- if (!spi_cs_is_valid(bus, cs)) {
- printf("SPI error: unsupported bus %d / chip select %d\n",
- bus, cs);
- return NULL;
- }
+ plat->base = fdtdec_get_addr(blob, node, "reg");
+ plat->periph_id = clock_decode_periph_id(blob, node);
- if (max_hz > TEGRA_SPI_MAX_FREQ) {
- printf("SPI error: unsupported frequency %d Hz. Max frequency"
- " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
- return NULL;
+ if (plat->periph_id == PERIPH_ID_NONE) {
+ debug("%s: could not decode periph id %d\n", __func__,
+ plat->periph_id);
+ return -FDT_ERR_NOTFOUND;
}
- spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs);
- if (!spi) {
- printf("SPI error: malloc of SPI structure failed\n");
- return NULL;
- }
- spi->ctrl = &spi_ctrls[bus];
- if (!spi->ctrl) {
- printf("SPI error: could not find controller for bus %d\n",
- bus);
- return NULL;
- }
+ /* Use 500KHz as a suitable default */
+ plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+ 500000);
+ plat->deactivate_delay_us = fdtdec_get_int(blob, node,
+ "spi-deactivate-delay", 0);
+ debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
+ __func__, plat->base, plat->periph_id, plat->frequency,
+ plat->deactivate_delay_us);
- if (max_hz < spi->ctrl->freq) {
- debug("%s: limiting frequency from %u to %u\n", __func__,
- spi->ctrl->freq, max_hz);
- spi->ctrl->freq = max_hz;
- }
- spi->ctrl->mode = mode;
-
- return &spi->slave;
+ return 0;
}
-void tegra20_spi_free_slave(struct spi_slave *slave)
+static int tegra20_sflash_probe(struct udevice *bus)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
-
- free(spi);
-}
+ struct tegra_spi_platdata *plat = dev_get_platdata(bus);
+ struct tegra20_sflash_priv *priv = dev_get_priv(bus);
-int tegra20_spi_init(int *node_list, int count)
-{
- struct tegra_spi_ctrl *ctrl;
- int i;
- int node = 0;
- int found = 0;
-
- for (i = 0; i < count; i++) {
- ctrl = &spi_ctrls[i];
- node = node_list[i];
-
- ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
- node, "reg");
- if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
- debug("%s: no slink register found\n", __func__);
- continue;
- }
- ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
- "spi-max-frequency", 0);
- if (!ctrl->freq) {
- debug("%s: no slink max frequency found\n", __func__);
- continue;
- }
+ priv->regs = (struct spi_regs *)plat->base;
- ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
- if (ctrl->periph_id == PERIPH_ID_NONE) {
- debug("%s: could not decode periph id\n", __func__);
- continue;
- }
- ctrl->valid = 1;
- found = 1;
+ priv->last_transaction_us = timer_get_us();
+ priv->freq = plat->frequency;
+ priv->periph_id = plat->periph_id;
- debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
- __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
- }
- return !found;
+ return 0;
}
-int tegra20_spi_claim_bus(struct spi_slave *slave)
+static int tegra20_sflash_claim_bus(struct udevice *bus)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct tegra20_sflash_priv *priv = dev_get_priv(bus);
+ struct spi_regs *regs = priv->regs;
u32 reg;
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
- clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
- spi->ctrl->freq);
+ clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
+ priv->freq);
/* Clear stale status here */
reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
@@ -197,8 +144,8 @@ int tegra20_spi_claim_bus(struct spi_slave *slave)
/*
* Use sw-controlled CS, so we can clock in data after ReadID, etc.
*/
- reg = (spi->ctrl->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
- if (spi->ctrl->mode & 2)
+ reg = (priv->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
+ if (priv->mode & 2)
reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
clrsetbits_le32(&regs->command, SPI_CMD_ACTIVE_SCLK_MASK |
SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
@@ -215,37 +162,54 @@ int tegra20_spi_claim_bus(struct spi_slave *slave)
return 0;
}
-void tegra20_spi_cs_activate(struct spi_slave *slave)
+static void spi_cs_activate(struct udevice *dev)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct udevice *bus = dev->parent;
+ struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+ struct tegra20_sflash_priv *priv = dev_get_priv(bus);
+
+ /* If it's too soon to do another transaction, wait */
+ if (pdata->deactivate_delay_us &&
+ priv->last_transaction_us) {
+ ulong delay_us; /* The delay completed so far */
+ delay_us = timer_get_us() - priv->last_transaction_us;
+ if (delay_us < pdata->deactivate_delay_us)
+ udelay(pdata->deactivate_delay_us - delay_us);
+ }
/* CS is negated on Tegra, so drive a 1 to get a 0 */
- setbits_le32(&regs->command, SPI_CMD_CS_VAL);
+ setbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
}
-void tegra20_spi_cs_deactivate(struct spi_slave *slave)
+static void spi_cs_deactivate(struct udevice *dev)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct udevice *bus = dev->parent;
+ struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+ struct tegra20_sflash_priv *priv = dev_get_priv(bus);
/* CS is negated on Tegra, so drive a 0 to get a 1 */
- clrbits_le32(&regs->command, SPI_CMD_CS_VAL);
+ clrbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
+
+ /* Remember time of this transaction so we can honour the bus delay */
+ if (pdata->deactivate_delay_us)
+ priv->last_transaction_us = timer_get_us();
}
-int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *data_out, void *data_in, unsigned long flags)
+static int tegra20_sflash_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *data_out, void *data_in,
+ unsigned long flags)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct udevice *bus = dev->parent;
+ struct tegra20_sflash_priv *priv = dev_get_priv(bus);
+ struct spi_regs *regs = priv->regs;
u32 reg, tmpdout, tmpdin = 0;
const u8 *dout = data_out;
u8 *din = data_in;
int num_bytes;
int ret;
- debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
- slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen);
+ debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
+ __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
if (bitlen % 8)
return -1;
num_bytes = bitlen / 8;
@@ -262,7 +226,7 @@ int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
debug("spi_xfer: COMMAND = %08x\n", readl(&regs->command));
if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
+ spi_cs_activate(dev);
/* handle data in 32-bit chunks */
while (num_bytes > 0) {
@@ -327,7 +291,7 @@ int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
}
if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
+ spi_cs_deactivate(dev);
debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
tmpdin, readl(&regs->status));
@@ -339,3 +303,51 @@ int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
return 0;
}
+
+static int tegra20_sflash_set_speed(struct udevice *bus, uint speed)
+{
+ struct tegra_spi_platdata *plat = bus->platdata;
+ struct tegra20_sflash_priv *priv = dev_get_priv(bus);
+
+ if (speed > plat->frequency)
+ speed = plat->frequency;
+ priv->freq = speed;
+ debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
+
+ return 0;
+}
+
+static int tegra20_sflash_set_mode(struct udevice *bus, uint mode)
+{
+ struct tegra20_sflash_priv *priv = dev_get_priv(bus);
+
+ priv->mode = mode;
+ debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
+
+ return 0;
+}
+
+static const struct dm_spi_ops tegra20_sflash_ops = {
+ .claim_bus = tegra20_sflash_claim_bus,
+ .xfer = tegra20_sflash_xfer,
+ .set_speed = tegra20_sflash_set_speed,
+ .set_mode = tegra20_sflash_set_mode,
+ .cs_info = tegra20_sflash_cs_info,
+};
+
+static const struct udevice_id tegra20_sflash_ids[] = {
+ { .compatible = "nvidia,tegra20-sflash" },
+ { }
+};
+
+U_BOOT_DRIVER(tegra20_sflash) = {
+ .name = "tegra20_sflash",
+ .id = UCLASS_SPI,
+ .of_match = tegra20_sflash_ids,
+ .ops = &tegra20_sflash_ops,
+ .ofdata_to_platdata = tegra20_sflash_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
+ .priv_auto_alloc_size = sizeof(struct tegra20_sflash_priv),
+ .per_child_auto_alloc_size = sizeof(struct spi_slave),
+ .probe = tegra20_sflash_probe,
+};
diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c
index 664de6e..213fa5f 100644
--- a/drivers/spi/tegra20_slink.c
+++ b/drivers/spi/tegra20_slink.c
@@ -22,14 +22,13 @@
*/
#include <common.h>
-#include <malloc.h>
+#include <dm.h>
#include <asm/io.h>
-#include <asm/gpio.h>
#include <asm/arch/clock.h>
#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra20/tegra20_slink.h>
#include <spi.h>
#include <fdtdec.h>
+#include "tegra_spi.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -87,130 +86,70 @@ struct spi_regs {
u32 rx_fifo; /* SLINK_RX_FIFO_0 reg off 180h */
};
-struct tegra_spi_ctrl {
+struct tegra30_spi_priv {
struct spi_regs *regs;
unsigned int freq;
unsigned int mode;
int periph_id;
int valid;
+ int last_transaction_us;
};
struct tegra_spi_slave {
struct spi_slave slave;
- struct tegra_spi_ctrl *ctrl;
+ struct tegra30_spi_priv *ctrl;
};
-static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA_SLINK_CTRLS];
-
-static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
-{
- return container_of(slave, struct tegra_spi_slave, slave);
-}
-
-int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs)
+static int tegra30_spi_ofdata_to_platdata(struct udevice *bus)
{
- if (bus >= CONFIG_TEGRA_SLINK_CTRLS || cs > 3 || !spi_ctrls[bus].valid)
- return 0;
- else
- return 1;
-}
+ struct tegra_spi_platdata *plat = bus->platdata;
+ const void *blob = gd->fdt_blob;
+ int node = bus->of_offset;
-struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct tegra_spi_slave *spi;
+ plat->base = fdtdec_get_addr(blob, node, "reg");
+ plat->periph_id = clock_decode_periph_id(blob, node);
- debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__,
- bus, cs, max_hz, mode);
-
- if (!spi_cs_is_valid(bus, cs)) {
- printf("SPI error: unsupported bus %d / chip select %d\n",
- bus, cs);
- return NULL;
- }
-
- if (max_hz > TEGRA_SPI_MAX_FREQ) {
- printf("SPI error: unsupported frequency %d Hz. Max frequency"
- " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
- return NULL;
+ if (plat->periph_id == PERIPH_ID_NONE) {
+ debug("%s: could not decode periph id %d\n", __func__,
+ plat->periph_id);
+ return -FDT_ERR_NOTFOUND;
}
- spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs);
- if (!spi) {
- printf("SPI error: malloc of SPI structure failed\n");
- return NULL;
- }
- spi->ctrl = &spi_ctrls[bus];
- if (!spi->ctrl) {
- printf("SPI error: could not find controller for bus %d\n",
- bus);
- return NULL;
- }
+ /* Use 500KHz as a suitable default */
+ plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+ 500000);
+ plat->deactivate_delay_us = fdtdec_get_int(blob, node,
+ "spi-deactivate-delay", 0);
+ debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
+ __func__, plat->base, plat->periph_id, plat->frequency,
+ plat->deactivate_delay_us);
- if (max_hz < spi->ctrl->freq) {
- debug("%s: limiting frequency from %u to %u\n", __func__,
- spi->ctrl->freq, max_hz);
- spi->ctrl->freq = max_hz;
- }
- spi->ctrl->mode = mode;
-
- return &spi->slave;
+ return 0;
}
-void tegra30_spi_free_slave(struct spi_slave *slave)
+static int tegra30_spi_probe(struct udevice *bus)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
-
- free(spi);
-}
+ struct tegra_spi_platdata *plat = dev_get_platdata(bus);
+ struct tegra30_spi_priv *priv = dev_get_priv(bus);
-int tegra30_spi_init(int *node_list, int count)
-{
- struct tegra_spi_ctrl *ctrl;
- int i;
- int node = 0;
- int found = 0;
-
- for (i = 0; i < count; i++) {
- ctrl = &spi_ctrls[i];
- node = node_list[i];
-
- ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
- node, "reg");
- if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
- debug("%s: no slink register found\n", __func__);
- continue;
- }
- ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
- "spi-max-frequency", 0);
- if (!ctrl->freq) {
- debug("%s: no slink max frequency found\n", __func__);
- continue;
- }
+ priv->regs = (struct spi_regs *)plat->base;
- ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
- if (ctrl->periph_id == PERIPH_ID_NONE) {
- debug("%s: could not decode periph id\n", __func__);
- continue;
- }
- ctrl->valid = 1;
- found = 1;
+ priv->last_transaction_us = timer_get_us();
+ priv->freq = plat->frequency;
+ priv->periph_id = plat->periph_id;
- debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
- __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
- }
- return !found;
+ return 0;
}
-int tegra30_spi_claim_bus(struct spi_slave *slave)
+static int tegra30_spi_claim_bus(struct udevice *bus)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct tegra30_spi_priv *priv = dev_get_priv(bus);
+ struct spi_regs *regs = priv->regs;
u32 reg;
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
- clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
- spi->ctrl->freq);
+ clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
+ priv->freq);
/* Clear stale status here */
reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \
@@ -227,29 +166,46 @@ int tegra30_spi_claim_bus(struct spi_slave *slave)
return 0;
}
-void tegra30_spi_cs_activate(struct spi_slave *slave)
+static void spi_cs_activate(struct udevice *dev)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct udevice *bus = dev->parent;
+ struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+ struct tegra30_spi_priv *priv = dev_get_priv(bus);
+
+ /* If it's too soon to do another transaction, wait */
+ if (pdata->deactivate_delay_us &&
+ priv->last_transaction_us) {
+ ulong delay_us; /* The delay completed so far */
+ delay_us = timer_get_us() - priv->last_transaction_us;
+ if (delay_us < pdata->deactivate_delay_us)
+ udelay(pdata->deactivate_delay_us - delay_us);
+ }
/* CS is negated on Tegra, so drive a 1 to get a 0 */
- setbits_le32(&regs->command, SLINK_CMD_CS_VAL);
+ setbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL);
}
-void tegra30_spi_cs_deactivate(struct spi_slave *slave)
+static void spi_cs_deactivate(struct udevice *dev)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct udevice *bus = dev->parent;
+ struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
+ struct tegra30_spi_priv *priv = dev_get_priv(bus);
/* CS is negated on Tegra, so drive a 0 to get a 1 */
- clrbits_le32(&regs->command, SLINK_CMD_CS_VAL);
+ clrbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL);
+
+ /* Remember time of this transaction so we can honour the bus delay */
+ if (pdata->deactivate_delay_us)
+ priv->last_transaction_us = timer_get_us();
}
-int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
- const void *data_out, void *data_in, unsigned long flags)
+static int tegra30_spi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *data_out, void *data_in,
+ unsigned long flags)
{
- struct tegra_spi_slave *spi = to_tegra_spi(slave);
- struct spi_regs *regs = spi->ctrl->regs;
+ struct udevice *bus = dev->parent;
+ struct tegra30_spi_priv *priv = dev_get_priv(bus);
+ struct spi_regs *regs = priv->regs;
u32 reg, tmpdout, tmpdin = 0;
const u8 *dout = data_out;
u8 *din = data_in;
@@ -257,7 +213,7 @@ int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
int ret;
debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
- __func__, slave->bus, slave->cs, dout, din, bitlen);
+ __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
if (bitlen % 8)
return -1;
num_bytes = bitlen / 8;
@@ -276,11 +232,11 @@ int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
clrsetbits_le32(&regs->command2, SLINK_CMD2_SS_EN_MASK,
SLINK_CMD2_TXEN | SLINK_CMD2_RXEN |
- (slave->cs << SLINK_CMD2_SS_EN_SHIFT));
+ (spi_chip_select(dev) << SLINK_CMD2_SS_EN_SHIFT));
debug("%s entry: COMMAND2 = %08x\n", __func__, readl(&regs->command2));
if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
+ spi_cs_activate(dev);
/* handle data in 32-bit chunks */
while (num_bytes > 0) {
@@ -344,7 +300,7 @@ int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
}
if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
+ spi_cs_deactivate(dev);
debug("%s: transfer ended. Value=%08x, status = %08x\n",
__func__, tmpdin, readl(&regs->status));
@@ -357,3 +313,54 @@ int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
return 0;
}
+
+static int tegra30_spi_set_speed(struct udevice *bus, uint speed)
+{
+ struct tegra_spi_platdata *plat = bus->platdata;
+ struct tegra30_spi_priv *priv = dev_get_priv(bus);
+
+ if (speed > plat->frequency)
+ speed = plat->frequency;
+ priv->freq = speed;
+ debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
+
+ return 0;
+}
+
+static int tegra30_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct tegra30_spi_priv *priv = dev_get_priv(bus);
+
+ priv->mode = mode;
+ debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
+
+ return 0;
+}
+
+static const struct dm_spi_ops tegra30_spi_ops = {
+ .claim_bus = tegra30_spi_claim_bus,
+ .xfer = tegra30_spi_xfer,
+ .set_speed = tegra30_spi_set_speed,
+ .set_mode = tegra30_spi_set_mode,
+ /*
+ * cs_info is not needed, since we require all chip selects to be
+ * in the device tree explicitly
+ */
+};
+
+static const struct udevice_id tegra30_spi_ids[] = {
+ { .compatible = "nvidia,tegra20-slink" },
+ { }
+};
+
+U_BOOT_DRIVER(tegra30_spi) = {
+ .name = "tegra20_slink",
+ .id = UCLASS_SPI,
+ .of_match = tegra30_spi_ids,
+ .ops = &tegra30_spi_ops,
+ .ofdata_to_platdata = tegra30_spi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
+ .priv_auto_alloc_size = sizeof(struct tegra30_spi_priv),
+ .per_child_auto_alloc_size = sizeof(struct spi_slave),
+ .probe = tegra30_spi_probe,
+};
diff --git a/drivers/spi/tegra_spi.h b/drivers/spi/tegra_spi.h
new file mode 100644
index 0000000..fb2b50f
--- /dev/null
+++ b/drivers/spi/tegra_spi.h
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+struct tegra_spi_platdata {
+ enum periph_id periph_id;
+ int frequency; /* Default clock frequency, -1 for none */
+ ulong base;
+ uint deactivate_delay_us; /* Delay to wait after deactivate */
+};