diff options
Diffstat (limited to 'drivers')
60 files changed, 4940 insertions, 744 deletions
diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile index dd9c102..feba4da 100644 --- a/drivers/bios_emulator/Makefile +++ b/drivers/bios_emulator/Makefile @@ -23,6 +23,7 @@ EXTRA_CFLAGS += -I. -I./include -I$(TOPDIR)/include \ CFLAGS += $(EXTRA_CFLAGS) HOSTCFLAGS += $(EXTRA_CFLAGS) +CPPFLAGS += $(EXTRA_CFLAGS) all: $(LIB) diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 4a12976..b860e89 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -33,6 +33,7 @@ COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o +COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o diff --git a/drivers/i2c/bfin-twi_i2c.c b/drivers/i2c/bfin-twi_i2c.c index e790634..73a78d2 100644 --- a/drivers/i2c/bfin-twi_i2c.c +++ b/drivers/i2c/bfin-twi_i2c.c @@ -26,6 +26,7 @@ #ifdef TWI0_CLKDIV #define bfin_write_TWI_CLKDIV(val) bfin_write_TWI0_CLKDIV(val) +#define bfin_read_TWI_CLKDIV(val) bfin_read_TWI0_CLKDIV(val) #define bfin_write_TWI_CONTROL(val) bfin_write_TWI0_CONTROL(val) #define bfin_read_TWI_CONTROL(val) bfin_read_TWI0_CONTROL(val) #define bfin_write_TWI_MASTER_ADDR(val) bfin_write_TWI0_MASTER_ADDR(val) @@ -44,8 +45,21 @@ #ifdef CONFIG_TWICLK_KHZ # error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED #endif -#if CONFIG_SYS_I2C_SPEED > 400000 -# error The Blackfin I2C hardware can only operate at 400KHz max + +/* + * The way speed is changed into duty often results in integer truncation + * with 50% duty, so we'll force rounding up to the next duty by adding 1 + * to the max. In practice this will get us a speed of something like + * 385 KHz. The other limit is easy to handle as it is only 8 bits. + */ +#define I2C_SPEED_MAX 400000 +#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed)) +#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1) +#define I2C_DUTY_MIN 0xff /* 8 bit limited */ +#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED) +/* Note: duty is inverse of speed, so the comparisons below are correct */ +#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN +# error "The Blackfin I2C hardware can only operate 20KHz - 400KHz" #endif /* All transfers are described by this data structure */ @@ -60,6 +74,9 @@ struct i2c_msg { u8 *abuf; /* addr buffer */ }; +/* Allow msec timeout per ~byte transfer */ +#define I2C_TIMEOUT 10 + /** * wait_for_completion - manage the actual i2c transfer * @msg: the i2c msg @@ -67,8 +84,9 @@ struct i2c_msg { static int wait_for_completion(struct i2c_msg *msg) { uint16_t int_stat; + ulong timebase = get_timer(0); - while (!ctrlc()) { + do { int_stat = bfin_read_TWI_INT_STAT(); if (int_stat & XMTSERV) { @@ -103,7 +121,7 @@ static int wait_for_completion(struct i2c_msg *msg) debugi("processing MERR"); bfin_write_TWI_INT_STAT(MERR); SSYNC(); - break; + return msg->len; } if (int_stat & MCOMP) { debugi("processing MCOMP"); @@ -116,7 +134,12 @@ static int wait_for_completion(struct i2c_msg *msg) } else break; } - } + + /* If we were able to do something, reset timeout */ + if (int_stat) + timebase = get_timer(0); + + } while (get_timer(timebase) < I2C_TIMEOUT); return msg->len; } @@ -204,7 +227,36 @@ static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, return ret; } -/* +/** + * i2c_set_bus_speed - set i2c bus speed + * @speed: bus speed (in HZ) + */ +int i2c_set_bus_speed(unsigned int speed) +{ + u16 clkdiv = I2C_SPEED_TO_DUTY(speed); + + /* Set TWI interface clock */ + if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN) + return -1; + bfin_write_TWI_CLKDIV((clkdiv << 8) | (clkdiv & 0xff)); + + /* Don't turn it on */ + bfin_write_TWI_MASTER_CTL(speed > 100000 ? FAST : 0); + + return 0; +} + +/** + * i2c_get_bus_speed - get i2c bus speed + * @speed: bus speed (in HZ) + */ +unsigned int i2c_get_bus_speed(void) +{ + /* 10 MHz / (2 * CLKDIV) -> 5 MHz / CLKDIV */ + return 5000000 / (bfin_read_TWI_CLKDIV() & 0xff); +} + +/** * i2c_init - initialize the i2c bus * @speed: bus speed (in HZ) * @slaveaddr: address of device in slave mode (0 - not slave) @@ -220,15 +272,9 @@ void i2c_init(int speed, int slaveaddr) bfin_write_TWI_CONTROL(prescale); /* Set TWI interface clock as specified */ - bfin_write_TWI_CLKDIV( - ((5 * 1024 / (speed / 1000)) << 8) | - ((5 * 1024 / (speed / 1000)) & 0xFF) - ); - - /* Don't turn it on */ - bfin_write_TWI_MASTER_CTL(speed > 100000 ? FAST : 0); + i2c_set_bus_speed(speed); - /* But enable it */ + /* Enable it */ bfin_write_TWI_CONTROL(TWI_ENA | prescale); SSYNC(); diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 1a4c8c9..ff18991 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -29,6 +29,11 @@ static void wait_for_bb (void); static u16 wait_for_pin (void); static void flush_fifo(void); +static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE; + +static unsigned int bus_initialized[I2C_BUS_MAX]; +static unsigned int current_bus; + void i2c_init (int speed, int slaveadd) { int psc, fsscll, fssclh; @@ -95,30 +100,32 @@ void i2c_init (int speed, int slaveadd) sclh = (unsigned int)fssclh; } - writew(0x2, I2C_SYSC); /* for ES2 after soft reset */ + writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */ udelay(1000); - writew(0x0, I2C_SYSC); /* will probably self clear but */ + writew(0x0, &i2c_base->sysc); /* will probably self clear but */ - if (readw (I2C_CON) & I2C_CON_EN) { - writew (0, I2C_CON); + if (readw (&i2c_base->con) & I2C_CON_EN) { + writew (0, &i2c_base->con); udelay (50000); } - writew(psc, I2C_PSC); - writew(scll, I2C_SCLL); - writew(sclh, I2C_SCLH); + writew(psc, &i2c_base->psc); + writew(scll, &i2c_base->scll); + writew(sclh, &i2c_base->sclh); /* own address */ - writew (slaveadd, I2C_OA); - writew (I2C_CON_EN, I2C_CON); + writew (slaveadd, &i2c_base->oa); + writew (I2C_CON_EN, &i2c_base->con); /* have to enable intrrupts or OMAP i2c module doesn't work */ writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | - I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE); + I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); udelay (1000); flush_fifo(); - writew (0xFFFF, I2C_STAT); - writew (0, I2C_CNT); + writew (0xFFFF, &i2c_base->stat); + writew (0, &i2c_base->cnt); + + bus_initialized[current_bus] = 1; } static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) @@ -130,19 +137,19 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) wait_for_bb (); /* one byte only */ - writew (1, I2C_CNT); + writew (1, &i2c_base->cnt); /* set slave address */ - writew (devaddr, I2C_SA); + writew (devaddr, &i2c_base->sa); /* no stop bit needed here */ - writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c_base->con); status = wait_for_pin (); if (status & I2C_STAT_XRDY) { /* Important: have to use byte access */ - writeb (regoffset, I2C_DATA); + writeb (regoffset, &i2c_base->data); udelay (20000); - if (readw (I2C_STAT) & I2C_STAT_NACK) { + if (readw (&i2c_base->stat) & I2C_STAT_NACK) { i2c_error = 1; } } else { @@ -151,28 +158,28 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) if (!i2c_error) { /* free bus, otherwise we can't use a combined transction */ - writew (0, I2C_CON); - while (readw (I2C_STAT) || (readw (I2C_CON) & I2C_CON_MST)) { + writew (0, &i2c_base->con); + while (readw (&i2c_base->stat) || (readw (&i2c_base->con) & I2C_CON_MST)) { udelay (10000); /* Have to clear pending interrupt to clear I2C_STAT */ - writew (0xFFFF, I2C_STAT); + writew (0xFFFF, &i2c_base->stat); } wait_for_bb (); /* set slave address */ - writew (devaddr, I2C_SA); + writew (devaddr, &i2c_base->sa); /* read one byte from slave */ - writew (1, I2C_CNT); + writew (1, &i2c_base->cnt); /* need stop bit here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, - I2C_CON); + &i2c_base->con); status = wait_for_pin (); if (status & I2C_STAT_RRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) - *value = readb (I2C_DATA); + *value = readb (&i2c_base->data); #else - *value = readw (I2C_DATA); + *value = readw (&i2c_base->data); #endif udelay (20000); } else { @@ -180,17 +187,17 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) } if (!i2c_error) { - writew (I2C_CON_EN, I2C_CON); - while (readw (I2C_STAT) - || (readw (I2C_CON) & I2C_CON_MST)) { + writew (I2C_CON_EN, &i2c_base->con); + while (readw (&i2c_base->stat) + || (readw (&i2c_base->con) & I2C_CON_MST)) { udelay (10000); - writew (0xFFFF, I2C_STAT); + writew (0xFFFF, &i2c_base->stat); } } } flush_fifo(); - writew (0xFFFF, I2C_STAT); - writew (0, I2C_CNT); + writew (0xFFFF, &i2c_base->stat); + writew (0, &i2c_base->cnt); return i2c_error; } @@ -203,12 +210,12 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) wait_for_bb (); /* two bytes */ - writew (2, I2C_CNT); + writew (2, &i2c_base->cnt); /* set slave address */ - writew (devaddr, I2C_SA); + writew (devaddr, &i2c_base->sa); /* stop bit needed here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | - I2C_CON_STP, I2C_CON); + I2C_CON_STP, &i2c_base->con); /* wait until state change */ status = wait_for_pin (); @@ -216,24 +223,24 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) if (status & I2C_STAT_XRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) /* send out 1 byte */ - writeb (regoffset, I2C_DATA); - writew (I2C_STAT_XRDY, I2C_STAT); + writeb (regoffset, &i2c_base->data); + writew (I2C_STAT_XRDY, &i2c_base->stat); status = wait_for_pin (); if ((status & I2C_STAT_XRDY)) { /* send out next 1 byte */ - writeb (value, I2C_DATA); - writew (I2C_STAT_XRDY, I2C_STAT); + writeb (value, &i2c_base->data); + writew (I2C_STAT_XRDY, &i2c_base->stat); } else { i2c_error = 1; } #else /* send out two bytes */ - writew ((value << 8) + regoffset, I2C_DATA); + writew ((value << 8) + regoffset, &i2c_base->data); #endif /* must have enough delay to allow BB bit to go low */ udelay (50000); - if (readw (I2C_STAT) & I2C_STAT_NACK) { + if (readw (&i2c_base->stat) & I2C_STAT_NACK) { i2c_error = 1; } } else { @@ -243,18 +250,18 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) if (!i2c_error) { int eout = 200; - writew (I2C_CON_EN, I2C_CON); - while ((stat = readw (I2C_STAT)) || (readw (I2C_CON) & I2C_CON_MST)) { + writew (I2C_CON_EN, &i2c_base->con); + while ((stat = readw (&i2c_base->stat)) || (readw (&i2c_base->con) & I2C_CON_MST)) { udelay (1000); /* have to read to clear intrrupt */ - writew (0xFFFF, I2C_STAT); + writew (0xFFFF, &i2c_base->stat); if(--eout == 0) /* better leave with error than hang */ break; } } flush_fifo(); - writew (0xFFFF, I2C_STAT); - writew (0, I2C_CNT); + writew (0xFFFF, &i2c_base->stat); + writew (0, &i2c_base->cnt); return i2c_error; } @@ -265,14 +272,14 @@ static void flush_fifo(void) * you get a bus error */ while(1){ - stat = readw(I2C_STAT); + stat = readw(&i2c_base->stat); if(stat == I2C_STAT_RRDY){ #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) - readb(I2C_DATA); + readb(&i2c_base->data); #else - readw(I2C_DATA); + readw(&i2c_base->data); #endif - writew(I2C_STAT_RRDY,I2C_STAT); + writew(I2C_STAT_RRDY,&i2c_base->stat); udelay(1000); }else break; @@ -283,7 +290,7 @@ int i2c_probe (uchar chip) { int res = 1; /* default = fail */ - if (chip == readw (I2C_OA)) { + if (chip == readw (&i2c_base->oa)) { return res; } @@ -291,27 +298,27 @@ int i2c_probe (uchar chip) wait_for_bb (); /* try to read one byte */ - writew (1, I2C_CNT); + writew (1, &i2c_base->cnt); /* set slave address */ - writew (chip, I2C_SA); + writew (chip, &i2c_base->sa); /* stop bit needed here */ - writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con); /* enough delay for the NACK bit set */ udelay (50000); - if (!(readw (I2C_STAT) & I2C_STAT_NACK)) { + if (!(readw (&i2c_base->stat) & I2C_STAT_NACK)) { res = 0; /* success case */ flush_fifo(); - writew(0xFFFF, I2C_STAT); + writew(0xFFFF, &i2c_base->stat); } else { - writew(0xFFFF, I2C_STAT); /* failue, clear sources*/ - writew (readw (I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */ + writew(0xFFFF, &i2c_base->stat); /* failue, clear sources*/ + writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); /* finish up xfer */ udelay(20000); wait_for_bb (); } flush_fifo(); - writew (0, I2C_CNT); /* don't allow any more data in...we don't want it.*/ - writew(0xFFFF, I2C_STAT); + writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/ + writew(0xFFFF, &i2c_base->stat); return res; } @@ -370,17 +377,17 @@ static void wait_for_bb (void) int timeout = 10; u16 stat; - writew(0xFFFF, I2C_STAT); /* clear current interruts...*/ - while ((stat = readw (I2C_STAT) & I2C_STAT_BB) && timeout--) { - writew (stat, I2C_STAT); + writew(0xFFFF, &i2c_base->stat); /* clear current interruts...*/ + while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) { + writew (stat, &i2c_base->stat); udelay (50000); } if (timeout <= 0) { printf ("timed out in wait_for_bb: I2C_STAT=%x\n", - readw (I2C_STAT)); + readw (&i2c_base->stat)); } - writew(0xFFFF, I2C_STAT); /* clear delayed stuff*/ + writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/ } static u16 wait_for_pin (void) @@ -390,7 +397,7 @@ static u16 wait_for_pin (void) do { udelay (1000); - status = readw (I2C_STAT); + status = readw (&i2c_base->stat); } while ( !(status & (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | @@ -398,8 +405,33 @@ static u16 wait_for_pin (void) if (timeout <= 0) { printf ("timed out in wait_for_pin: I2C_STAT=%x\n", - readw (I2C_STAT)); - writew(0xFFFF, I2C_STAT); + readw (&i2c_base->stat)); + writew(0xFFFF, &i2c_base->stat); } return status; } + +int i2c_set_bus_num(unsigned int bus) +{ + if ((bus < 0) || (bus >= I2C_BUS_MAX)) { + printf("Bad bus: %d\n", bus); + return -1; + } + +#if I2C_BUS_MAX==3 + if (bus == 2) + i2c_base = (struct i2c *)I2C_BASE3; + else +#endif + if (bus == 1) + i2c_base = (struct i2c *)I2C_BASE2; + else + i2c_base = (struct i2c *)I2C_BASE1; + + current_bus = bus; + + if(!bus_initialized[current_bus]) + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + return 0; +} diff --git a/drivers/i2c/pca9564_i2c.c b/drivers/i2c/pca9564_i2c.c new file mode 100644 index 0000000..199a9ee --- /dev/null +++ b/drivers/i2c/pca9564_i2c.c @@ -0,0 +1,189 @@ +/* + * File: drivers/i2c/pca9564.c + * Based on: drivers/i2c/s3c44b0_i2c.c + * Author: + * + * Created: 2009-06-23 + * Description: PCA9564 i2c bridge driver + * + * Modified: + * Copyright 2009 CJSC "NII STT", http://www.niistt.ru/ + * + * Bugs: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <common.h> +#include <i2c.h> +#include <pca9564.h> +#include <asm/io.h> + +#define PCA_STA (CONFIG_PCA9564_BASE + 0) +#define PCA_TO (CONFIG_PCA9564_BASE + 0) +#define PCA_DAT (CONFIG_PCA9564_BASE + (1 << 2)) +#define PCA_ADR (CONFIG_PCA9564_BASE + (2 << 2)) +#define PCA_CON (CONFIG_PCA9564_BASE + (3 << 2)) + +static unsigned char pca_read_reg(unsigned int reg) +{ + return readb((void *)reg); +} + +static void pca_write_reg(unsigned int reg, unsigned char value) +{ + writeb(value, (void *)reg); +} + +static int pca_wait_busy(void) +{ + unsigned int timeout = 10000; + + while (!(pca_read_reg(PCA_CON) & PCA_CON_SI) && --timeout) + udelay(1); + + if (timeout == 0) + debug("I2C timeout!\n"); + + debug("CON = 0x%02x, STA = 0x%02x\n", pca_read_reg(PCA_CON), + pca_read_reg(PCA_STA)); + + return timeout ? 0 : 1; +} + +/*=====================================================================*/ +/* Public Functions */ +/*=====================================================================*/ + +/*----------------------------------------------------------------------- + * Initialization + */ +void i2c_init(int speed, int slaveaddr) +{ + pca_write_reg(PCA_CON, PCA_CON_ENSIO | speed); +} + +/* + * Probe the given I2C chip address. Returns 0 if a chip responded, + * not 0 on failure. + */ + +int i2c_probe(uchar chip) +{ + unsigned char res; + + pca_write_reg(PCA_CON, PCA_CON_STA | PCA_CON_ENSIO); + pca_wait_busy(); + + pca_write_reg(PCA_CON, PCA_CON_STA | PCA_CON_ENSIO); + + pca_write_reg(PCA_DAT, (chip << 1) | 1); + res = pca_wait_busy(); + + if ((res == 0) && (pca_read_reg(PCA_STA) == 0x48)) + res = 1; + + pca_write_reg(PCA_CON, PCA_CON_STO | PCA_CON_ENSIO); + + return res; +} + +/* + * Read/Write interface: + * chip: I2C chip address, range 0..127 + * addr: Memory (register) address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * buffer: Where to read/write the data + * len: How many bytes to read/write + * + * Returns: 0 on success, not 0 on failure + */ +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + int i; + + pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STA); + pca_wait_busy(); + + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + + pca_write_reg(PCA_DAT, (chip << 1)); + pca_wait_busy(); + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + + if (alen > 0) { + pca_write_reg(PCA_DAT, addr); + pca_wait_busy(); + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + } + + pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STO); + + udelay(500); + + pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STA); + pca_wait_busy(); + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + + pca_write_reg(PCA_DAT, (chip << 1) | 1); + pca_wait_busy(); + + for (i = 0; i < len; ++i) { + if (i == len - 1) + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + else + pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_AA); + + pca_wait_busy(); + buffer[i] = pca_read_reg(PCA_DAT); + + } + + pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STO); + + return 0; +} + +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + int i; + + pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STA); + pca_wait_busy(); + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + + pca_write_reg(PCA_DAT, chip << 1); + pca_wait_busy(); + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + + if (alen > 0) { + pca_write_reg(PCA_DAT, addr); + pca_wait_busy(); + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + } + + for (i = 0; i < len; ++i) { + pca_write_reg(PCA_DAT, buffer[i]); + pca_wait_busy(); + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + } + + pca_write_reg(PCA_CON, PCA_CON_STO | PCA_CON_ENSIO); + + return 0; +} diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 59883a5..9a48783 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -34,6 +34,11 @@ #include <asm/io.h> #include <asm/arch/hardware.h> #endif +#ifdef CONFIG_AT91SAM9263 /* only valid for AT91SAM9263 */ +#include <asm/arch/at91_pmc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#endif #ifdef CONFIG_IXP425 /* only valid for IXP425 */ #include <asm/arch/ixp425.h> #endif diff --git a/drivers/misc/twl4030_led.c b/drivers/misc/twl4030_led.c index bfdafef..33cea11 100644 --- a/drivers/misc/twl4030_led.c +++ b/drivers/misc/twl4030_led.c @@ -34,19 +34,15 @@ #include <twl4030.h> -#define LEDAON (0x1 << 0) -#define LEDBON (0x1 << 1) -#define LEDAPWM (0x1 << 4) -#define LEDBPWM (0x1 << 5) - -void twl4030_led_init(void) +void twl4030_led_init(unsigned char ledon_mask) { - unsigned char byte; - - /* enable LED */ - byte = LEDBPWM | LEDAPWM | LEDBON | LEDAON; + /* LEDs need to have corresponding PWMs enabled */ + if (ledon_mask & TWL4030_LED_LEDEN_LEDAON) + ledon_mask |= TWL4030_LED_LEDEN_LEDAPWM; + if (ledon_mask & TWL4030_LED_LEDEN_LEDBON) + ledon_mask |= TWL4030_LED_LEDEN_LEDBPWM; - twl4030_i2c_write_u8(TWL4030_CHIP_LED, byte, + twl4030_i2c_write_u8(TWL4030_CHIP_LED, ledon_mask, TWL4030_LED_LEDEN); } diff --git a/drivers/mmc/omap3_mmc.c b/drivers/mmc/omap3_mmc.c index 513dd25..96c0e65 100644 --- a/drivers/mmc/omap3_mmc.c +++ b/drivers/mmc/omap3_mmc.c @@ -63,7 +63,9 @@ unsigned char mmc_board_init(void) { t2_t *t2_base = (t2_t *)T2_BASE; +#if defined(CONFIG_TWL4030_POWER) twl4030_power_mmc_init(); +#endif writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 | PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index eabaf3e..bfc2acf 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -59,14 +59,111 @@ static emif_registers *const emif_regs = (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE; +/* + * Exploit the little endianness of the ARM to do multi-byte transfers + * per device read. This can perform over twice as quickly as individual + * byte transfers when buffer alignment is conducive. + * + * NOTE: This only works if the NAND is not connected to the 2 LSBs of + * the address bus. On Davinci EVM platforms this has always been true. + */ +static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + struct nand_chip *chip = mtd->priv; + const u32 *nand = chip->IO_ADDR_R; + + /* Make sure that buf is 32 bit aligned */ + if (((int)buf & 0x3) != 0) { + if (((int)buf & 0x1) != 0) { + if (len) { + *buf = readb(nand); + buf += 1; + len--; + } + } + + if (((int)buf & 0x3) != 0) { + if (len >= 2) { + *(u16 *)buf = readw(nand); + buf += 2; + len -= 2; + } + } + } + + /* copy aligned data */ + while (len >= 4) { + *(u32 *)buf = readl(nand); + buf += 4; + len -= 4; + } + + /* mop up any remaining bytes */ + if (len) { + if (len >= 2) { + *(u16 *)buf = readw(nand); + buf += 2; + len -= 2; + } + + if (len) + *buf = readb(nand); + } +} + +static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf, + int len) +{ + struct nand_chip *chip = mtd->priv; + const u32 *nand = chip->IO_ADDR_W; + + /* Make sure that buf is 32 bit aligned */ + if (((int)buf & 0x3) != 0) { + if (((int)buf & 0x1) != 0) { + if (len) { + writeb(*buf, nand); + buf += 1; + len--; + } + } + + if (((int)buf & 0x3) != 0) { + if (len >= 2) { + writew(*(u16 *)buf, nand); + buf += 2; + len -= 2; + } + } + } + + /* copy aligned data */ + while (len >= 4) { + writel(*(u32 *)buf, nand); + buf += 4; + len -= 4; + } + + /* mop up any remaining bytes */ + if (len) { + if (len >= 2) { + writew(*(u16 *)buf, nand); + buf += 2; + len -= 2; + } + + if (len) + writeb(*buf, nand); + } +} + static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct nand_chip *this = mtd->priv; u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W; - IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); - if (ctrl & NAND_CTRL_CHANGE) { + IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); + if ( ctrl & NAND_CLE ) IO_ADDR_W |= MASK_CLE; if ( ctrl & NAND_ALE ) @@ -75,33 +172,28 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int c } if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); + writeb(cmd, IO_ADDR_W); } #ifdef CONFIG_SYS_NAND_HW_ECC static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) { - int dummy; + u_int32_t val; - dummy = emif_regs->NANDF1ECC; + (void)readl(&(emif_regs->NANDFECC[CONFIG_SYS_NAND_CS - 2])); - /* FIXME: only chipselect 0 is supported for now */ - emif_regs->NANDFCR |= 1 << 8; + val = readl(&emif_regs->NANDFCR); + val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); + val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS); + writel(val, &emif_regs->NANDFCR); } static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) { u_int32_t ecc = 0; - if (region == 1) - ecc = emif_regs->NANDF1ECC; - else if (region == 2) - ecc = emif_regs->NANDF2ECC; - else if (region == 3) - ecc = emif_regs->NANDF3ECC; - else if (region == 4) - ecc = emif_regs->NANDF4ECC; + ecc = readl(&(emif_regs->NANDFECC[region - 1])); return(ecc); } @@ -182,13 +274,7 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char * #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = { -/* - * TI uses a different layout for 4K page deviecs. Since the - * eccpos filed can hold only a limited number of entries, adding - * support for 4K page will result in compilation warnings - * 4K Support will be added later - */ -#ifdef CONFIG_SYS_NAND_PAGE_2K +#if defined(CONFIG_SYS_NAND_PAGE_2K) .eccbytes = 40, .eccpos = { 24, 25, 26, 27, 28, @@ -200,6 +286,21 @@ static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = { .oobfree = { {.offset = 2, .length = 22, }, }, +#elif defined(CONFIG_SYS_NAND_PAGE_4K) + .eccbytes = 80, + .eccpos = { + 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, + 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, + 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, + 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, + 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, + 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, + 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, + }, + .oobfree = { + {.offset = 2, .length = 46, }, + }, #endif }; @@ -214,8 +315,12 @@ static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode) * Start a new ECC calculation for reading or writing 512 bytes * of data. */ - val = (emif_regs->NANDFCR & ~(3 << 4)) | (1 << 12); - emif_regs->NANDFCR = val; + val = readl(&emif_regs->NANDFCR); + val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK; + val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); + val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS); + val |= DAVINCI_NANDFCR_4BIT_ECC_START; + writel(val, &emif_regs->NANDFCR); break; case NAND_ECC_READSYN: val = emif_regs->NAND4BITECC1; @@ -239,59 +344,55 @@ static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, uint8_t *ecc_code) { - unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }; - unsigned int const1 = 0, const2 = 0; - unsigned char count1 = 0; + unsigned int hw_4ecc[4]; + unsigned int i; nand_davinci_4bit_readecc(mtd, hw_4ecc); /*Convert 10 bit ecc value to 8 bit */ - for (count1 = 0; count1 < 2; count1++) { - const2 = count1 * 5; - const1 = count1 * 2; + for (i = 0; i < 2; i++) { + unsigned int hw_ecc_low = hw_4ecc[i * 2]; + unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1]; /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */ - ecc_code[const2] = hw_4ecc[const1] & 0xFF; + *ecc_code++ = hw_ecc_low & 0xFF; /* * Take 2 bits as LSB bits from val1 (count1=0) or val5 * (count1=1) and 6 bits from val2 (count1=0) or * val5 (count1=1) */ - ecc_code[const2 + 1] = - ((hw_4ecc[const1] >> 8) & 0x3) | ((hw_4ecc[const1] >> 14) & - 0xFC); + *ecc_code++ = + ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC); /* * Take 4 bits from val2 (count1=0) or val5 (count1=1) and * 4 bits from val3 (count1=0) or val6 (count1=1) */ - ecc_code[const2 + 2] = - ((hw_4ecc[const1] >> 22) & 0xF) | - ((hw_4ecc[const1 + 1] << 4) & 0xF0); + *ecc_code++ = + ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0); /* * Take 6 bits from val3(count1=0) or val6 (count1=1) and * 2 bits from val4 (count1=0) or val7 (count1=1) */ - ecc_code[const2 + 3] = - ((hw_4ecc[const1 + 1] >> 4) & 0x3F) | - ((hw_4ecc[const1 + 1] >> 10) & 0xC0); + *ecc_code++ = + ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0); /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */ - ecc_code[const2 + 4] = (hw_4ecc[const1 + 1] >> 18) & 0xFF; + *ecc_code++ = (hw_ecc_hi >> 18) & 0xFF; } + return 0; } - static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc) { - unsigned short ecc_10bit[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; int i; - unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }, iserror = 0; - unsigned short *pspare = NULL, *pspare1 = NULL; + unsigned int hw_4ecc[4]; + unsigned int iserror; + unsigned short *ecc16; unsigned int numerrors, erroraddress, errorvalue; u32 val; @@ -308,44 +409,41 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat, return 0; /* Convert 8 bit in to 10 bit */ - pspare = (unsigned short *)&read_ecc[2]; - pspare1 = (unsigned short *)&read_ecc[0]; + ecc16 = (unsigned short *)&read_ecc[0]; - /* Take 10 bits from 0th and 1st bytes */ - ecc_10bit[0] = (*pspare1) & 0x3FF; + /* + * Write the parity values in the NAND Flash 4-bit ECC Load register. + * Write each parity value one at a time starting from 4bit_ecc_val8 + * to 4bit_ecc_val1. + */ - /* Take 6 bits from 1st byte and 4 bits from 2nd byte */ - ecc_10bit[1] = (((*pspare1) >> 10) & 0x3F) - | (((pspare[0]) << 6) & 0x3C0); + /*Take 2 bits from 8th byte and 8 bits from 9th byte */ + writel(((ecc16[4]) >> 6) & 0x3FF, &emif_regs->NAND4BITECCLOAD); - /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */ - ecc_10bit[2] = ((pspare[0]) >> 4) & 0x3FF; + /* Take 4 bits from 7th byte and 6 bits from 8th byte */ + writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0), + &emif_regs->NAND4BITECCLOAD); - /*Take 2 bits from 3rd byte and 8 bits from 4th byte */ - ecc_10bit[3] = (((pspare[0]) >> 14) & 0x3) - | ((((pspare[1])) << 2) & 0x3FC); + /* Take 6 bits from 6th byte and 4 bits from 7th byte */ + writel((ecc16[3] >> 2) & 0x3FF, &emif_regs->NAND4BITECCLOAD); /* Take 8 bits from 5th byte and 2 bits from 6th byte */ - ecc_10bit[4] = ((pspare[1]) >> 8) - | ((((pspare[2])) << 8) & 0x300); + writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300), + &emif_regs->NAND4BITECCLOAD); - /* Take 6 bits from 6th byte and 4 bits from 7th byte */ - ecc_10bit[5] = (pspare[2] >> 2) & 0x3FF; + /*Take 2 bits from 3rd byte and 8 bits from 4th byte */ + writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC), + &emif_regs->NAND4BITECCLOAD); - /* Take 4 bits from 7th byte and 6 bits from 8th byte */ - ecc_10bit[6] = (((pspare[2]) >> 12) & 0xF) - | ((((pspare[3])) << 4) & 0x3F0); + /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */ + writel(((ecc16[1]) >> 4) & 0x3FF, &emif_regs->NAND4BITECCLOAD); - /*Take 2 bits from 8th byte and 8 bits from 9th byte */ - ecc_10bit[7] = ((pspare[3]) >> 6) & 0x3FF; + /* Take 6 bits from 1st byte and 4 bits from 2nd byte */ + writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0), + &emif_regs->NAND4BITECCLOAD); - /* - * Write the parity values in the NAND Flash 4-bit ECC Load register. - * Write each parity value one at a time starting from 4bit_ecc_val8 - * to 4bit_ecc_val1. - */ - for (i = 7; i >= 0; i--) - emif_regs->NAND4BITECCLOAD = ecc_10bit[i]; + /* Take 10 bits from 0th and 1st bytes */ + writel((ecc16[0]) & 0x3FF, &emif_regs->NAND4BITECCLOAD); /* * Perform a dummy read to the EMIF Revision Code and Status register. @@ -362,8 +460,7 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat, */ nand_davinci_4bit_readecc(mtd, hw_4ecc); - if (hw_4ecc[0] == ECC_STATE_NO_ERR && hw_4ecc[1] == ECC_STATE_NO_ERR && - hw_4ecc[2] == ECC_STATE_NO_ERR && hw_4ecc[3] == ECC_STATE_NO_ERR) + if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3])) return 0; /* @@ -510,6 +607,9 @@ void davinci_nand_init(struct nand_chip *nand) /* Set address of hardware control function */ nand->cmd_ctrl = nand_davinci_hwcontrol; + nand->read_buf = nand_davinci_read_buf; + nand->write_buf = nand_davinci_write_buf; + nand->dev_ready = nand_davinci_dev_ready; nand_flash_init(); diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index 50cb4aa..146e9bf 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -766,9 +766,6 @@ int board_nand_init(struct nand_chip *nand) nand->waitfunc = fsl_elbc_wait; /* set up nand options */ - /* redirect the pointer of bbt pattern to RAM */ - bbt_main_descr.pattern = bbt_pattern; - bbt_mirror_descr.pattern = mirror_pattern; nand->bbt_td = &bbt_main_descr; nand->bbt_md = &bbt_mirror_descr; @@ -815,7 +812,6 @@ int board_nand_init(struct nand_chip *nand) /* Large-page-specific setup */ if (or & OR_FCM_PGS) { priv->page_size = 1; - largepage_memorybased.pattern = scan_ff_pattern; nand->badblock_pattern = &largepage_memorybased; /* adjust ecc setup if needed */ diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 426bb95..7171bdd 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -893,6 +893,9 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this) * @mtd: mtd info structure * @chip: nand chip info structure * @buf: buffer to store read data + * @page: page number to read + * + * Not for syndrome calculating ecc controllers, which use a special oob layout */ static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int page) @@ -903,10 +906,53 @@ static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, } /** + * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: buffer to store read data + * @page: page number to read + * + * We need a special oob layout and handling even when OOB isn't used. + */ +static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int page) +{ + int eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + uint8_t *oob = chip->oob_poi; + int steps, size; + + for (steps = chip->ecc.steps; steps > 0; steps--) { + chip->read_buf(mtd, buf, eccsize); + buf += eccsize; + + if (chip->ecc.prepad) { + chip->read_buf(mtd, oob, chip->ecc.prepad); + oob += chip->ecc.prepad; + } + + chip->read_buf(mtd, oob, eccbytes); + oob += eccbytes; + + if (chip->ecc.postpad) { + chip->read_buf(mtd, oob, chip->ecc.postpad); + oob += chip->ecc.postpad; + } + } + + size = mtd->oobsize - (oob - chip->oob_poi); + if (size) + chip->read_buf(mtd, oob, size); + + return 0; +} + +/** * nand_read_page_swecc - [REPLACABLE] software ecc based page read function * @mtd: mtd info structure * @chip: nand chip info structure * @buf: buffer to store read data + * @page: page number to read */ static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int page) @@ -946,9 +992,9 @@ static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function * @mtd: mtd info structure * @chip: nand chip info structure - * @dataofs offset of requested data within the page - * @readlen data length - * @buf: buffer to store read data + * @data_offs: offset of requested data within the page + * @readlen: data length + * @bufpoi: buffer to store read data */ static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi) { @@ -1015,7 +1061,7 @@ static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint3 int stat; stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); - if (stat < 0) + if (stat == -1) mtd->ecc_stats.failed++; else mtd->ecc_stats.corrected += stat; @@ -1028,6 +1074,7 @@ static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint3 * @mtd: mtd info structure * @chip: nand chip info structure * @buf: buffer to store read data + * @page: page number to read * * Not for syndrome calculating ecc controllers which need a special oob layout */ @@ -1059,7 +1106,7 @@ static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, int stat; stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); - if (stat == -1) + if (stat < 0) mtd->ecc_stats.failed++; else mtd->ecc_stats.corrected += stat; @@ -1072,6 +1119,7 @@ static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, * @mtd: mtd info structure * @chip: nand chip info structure * @buf: buffer to store read data + * @page: page number to read * * Hardware ECC for large page chips, require OOB to be read first. * For this ECC mode, the write_page method is re-used from ECC_HW. @@ -1120,6 +1168,7 @@ static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, * @mtd: mtd info structure * @chip: nand chip info structure * @buf: buffer to store read data + * @page: page number to read * * The hw generator calculates the error syndrome automatically. Therefor * we need a special oob layout and handling. @@ -1677,6 +1726,8 @@ static int nand_read_oob(struct mtd_info *mtd, loff_t from, * @mtd: mtd info structure * @chip: nand chip info structure * @buf: data buffer + * + * Not for syndrome calculating ecc controllers, which use a special oob layout */ static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf) @@ -1686,6 +1737,44 @@ static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, } /** + * nand_write_page_raw_syndrome - [Intern] raw page write function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: data buffer + * + * We need a special oob layout and handling even when ECC isn't checked. + */ +static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf) +{ + int eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + uint8_t *oob = chip->oob_poi; + int steps, size; + + for (steps = chip->ecc.steps; steps > 0; steps--) { + chip->write_buf(mtd, buf, eccsize); + buf += eccsize; + + if (chip->ecc.prepad) { + chip->write_buf(mtd, oob, chip->ecc.prepad); + oob += chip->ecc.prepad; + } + + chip->read_buf(mtd, oob, eccbytes); + oob += eccbytes; + + if (chip->ecc.postpad) { + chip->write_buf(mtd, oob, chip->ecc.postpad); + oob += chip->ecc.postpad; + } + } + + size = mtd->oobsize - (oob - chip->oob_poi); + if (size) + chip->write_buf(mtd, oob, size); +} +/** * nand_write_page_swecc - [REPLACABLE] software ecc based page write function * @mtd: mtd info structure * @chip: nand chip info structure @@ -2211,13 +2300,15 @@ static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, int allowbbt) { - int page, len, status, pages_per_block, ret, chipnr; + int page, status, pages_per_block, ret, chipnr; struct nand_chip *chip = mtd->priv; - int rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS]={0}; + loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0}; unsigned int bbt_masked_page = 0xffffffff; + loff_t len; - MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n", - (unsigned int) instr->addr, (unsigned int) instr->len); + MTDDEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%012llx, " + "len = %llu\n", (unsigned long long) instr->addr, + (unsigned long long) instr->len); /* Start address must align on block boundary */ if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) { @@ -2313,7 +2404,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: " "Failed erase, page 0x%08x\n", page); instr->state = MTD_ERASE_FAILED; - instr->fail_addr = (page << chip->page_shift); + instr->fail_addr = ((loff_t)page << chip->page_shift); goto erase_exit; } @@ -2323,7 +2414,8 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, */ if (bbt_masked_page != 0xffffffff && (page & BBT_PAGE_MASK) == bbt_masked_page) - rewrite_bbt[chipnr] = (page << chip->page_shift); + rewrite_bbt[chipnr] = + ((loff_t)page << chip->page_shift); /* Increment page address and decrement length */ len -= (1 << chip->phys_erase_shift); @@ -2370,8 +2462,8 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, continue; /* update the BBT for chip */ MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt " - "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr], - chip->bbt_td->pages[chipnr]); + "(%d:0x%0llx 0x%0x)\n", chipnr, rewrite_bbt[chipnr], + chip->bbt_td->pages[chipnr]); nand_update_bbt(mtd, rewrite_bbt[chipnr]); } @@ -2566,7 +2658,7 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, if (!mtd->name) mtd->name = type->name; - chip->chipsize = type->chipsize << 20; + chip->chipsize = (uint64_t)type->chipsize << 20; /* Newer devices have all the information in additional id bytes */ if (!type->pagesize) { @@ -2624,7 +2716,10 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->bbt_erase_shift = chip->phys_erase_shift = ffs(mtd->erasesize) - 1; - chip->chip_shift = ffs(chip->chipsize) - 1; + if (chip->chipsize & 0xffffffff) + chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; + else + chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 31; /* Set the bad block position */ chip->badblockpos = mtd->writesize > 512 ? @@ -2722,7 +2817,6 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips) /** * nand_scan_tail - [NAND Interface] Scan for the NAND device * @mtd: MTD device structure - * @maxchips: Number of chips to scan for * * This is the second phase of the normal nand_scan() function. It * fills out all the uninitialized function pointers with the defaults @@ -2761,7 +2855,6 @@ int nand_scan_tail(struct mtd_info *mtd) default: printk(KERN_WARNING "No oob scheme defined for " "oobsize %d\n", mtd->oobsize); -/* BUG(); */ } } @@ -2772,10 +2865,6 @@ int nand_scan_tail(struct mtd_info *mtd) * check ECC mode, default to software if 3byte/512byte hardware ECC is * selected and we have 256 byte pagesize fallback to software ECC */ - if (!chip->ecc.read_page_raw) - chip->ecc.read_page_raw = nand_read_page_raw; - if (!chip->ecc.write_page_raw) - chip->ecc.write_page_raw = nand_write_page_raw; switch (chip->ecc.mode) { case NAND_ECC_HW_OOB_FIRST: @@ -2795,6 +2884,10 @@ int nand_scan_tail(struct mtd_info *mtd) chip->ecc.read_page = nand_read_page_hwecc; if (!chip->ecc.write_page) chip->ecc.write_page = nand_write_page_hwecc; + if (!chip->ecc.read_page_raw) + chip->ecc.read_page_raw = nand_read_page_raw; + if (!chip->ecc.write_page_raw) + chip->ecc.write_page_raw = nand_write_page_raw; if (!chip->ecc.read_oob) chip->ecc.read_oob = nand_read_oob_std; if (!chip->ecc.write_oob) @@ -2816,6 +2909,10 @@ int nand_scan_tail(struct mtd_info *mtd) chip->ecc.read_page = nand_read_page_syndrome; if (!chip->ecc.write_page) chip->ecc.write_page = nand_write_page_syndrome; + if (!chip->ecc.read_page_raw) + chip->ecc.read_page_raw = nand_read_page_raw_syndrome; + if (!chip->ecc.write_page_raw) + chip->ecc.write_page_raw = nand_write_page_raw_syndrome; if (!chip->ecc.read_oob) chip->ecc.read_oob = nand_read_oob_syndrome; if (!chip->ecc.write_oob) @@ -2834,6 +2931,8 @@ int nand_scan_tail(struct mtd_info *mtd) chip->ecc.read_page = nand_read_page_swecc; chip->ecc.read_subpage = nand_read_subpage; chip->ecc.write_page = nand_write_page_swecc; + chip->ecc.read_page_raw = nand_read_page_raw; + chip->ecc.write_page_raw = nand_write_page_raw; chip->ecc.read_oob = nand_read_oob_std; chip->ecc.write_oob = nand_write_oob_std; chip->ecc.size = 256; @@ -2846,6 +2945,8 @@ int nand_scan_tail(struct mtd_info *mtd) chip->ecc.read_page = nand_read_page_raw; chip->ecc.write_page = nand_write_page_raw; chip->ecc.read_oob = nand_read_oob_std; + chip->ecc.read_page_raw = nand_read_page_raw; + chip->ecc.write_page_raw = nand_write_page_raw; chip->ecc.write_oob = nand_write_oob_std; chip->ecc.size = mtd->writesize; chip->ecc.bytes = 0; @@ -2862,7 +2963,8 @@ int nand_scan_tail(struct mtd_info *mtd) * the out of band area */ chip->ecc.layout->oobavail = 0; - for (i = 0; chip->ecc.layout->oobfree[i].length; i++) + for (i = 0; chip->ecc.layout->oobfree[i].length + && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++) chip->ecc.layout->oobavail += chip->ecc.layout->oobfree[i].length; mtd->oobavail = chip->ecc.layout->oobavail; @@ -2890,6 +2992,7 @@ int nand_scan_tail(struct mtd_info *mtd) break; case 4: case 8: + case 16: mtd->subpage_sft = 2; break; } diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index d68a315f..2fe68ab 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -182,16 +182,19 @@ static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num, if (tmp == msk) continue; if (reserved_block_code && (tmp == reserved_block_code)) { - printk(KERN_DEBUG "nand_read_bbt: Reserved block at 0x%08x\n", - ((offs << 2) + (act >> 1)) << this->bbt_erase_shift); + printk(KERN_DEBUG "nand_read_bbt: Reserved block at 0x%012llx\n", + (loff_t)((offs << 2) + + (act >> 1)) << + this->bbt_erase_shift); this->bbt[offs + (act >> 3)] |= 0x2 << (act & 0x06); mtd->ecc_stats.bbtblocks++; continue; } /* Leave it for now, if its matured we can move this * message to MTD_DEBUG_LEVEL0 */ - printk(KERN_DEBUG "nand_read_bbt: Bad block at 0x%08x\n", - ((offs << 2) + (act >> 1)) << this->bbt_erase_shift); + printk(KERN_DEBUG "nand_read_bbt: Bad block at 0x%012llx\n", + (loff_t)((offs << 2) + (act >> 1)) << + this->bbt_erase_shift); /* Factory marked bad or worn out ? */ if (tmp == 0) this->bbt[offs + (act >> 3)] |= 0x3 << (act & 0x06); @@ -295,8 +298,8 @@ static int read_abs_bbts(struct mtd_info *mtd, uint8_t *buf, /* Read the primary version, if available */ if (td->options & NAND_BBT_VERSION) { - scan_read_raw(mtd, buf, td->pages[0] << this->page_shift, - mtd->writesize); + scan_read_raw(mtd, buf, (loff_t)td->pages[0] << + this->page_shift, mtd->writesize); td->version[0] = buf[mtd->writesize + td->veroffs]; printk(KERN_DEBUG "Bad block table at page %d, version 0x%02X\n", td->pages[0], td->version[0]); @@ -304,8 +307,8 @@ static int read_abs_bbts(struct mtd_info *mtd, uint8_t *buf, /* Read the mirror version, if available */ if (md && (md->options & NAND_BBT_VERSION)) { - scan_read_raw(mtd, buf, md->pages[0] << this->page_shift, - mtd->writesize); + scan_read_raw(mtd, buf, (loff_t)md->pages[0] << + this->page_shift, mtd->writesize); md->version[0] = buf[mtd->writesize + md->veroffs]; printk(KERN_DEBUG "Bad block table at page %d, version 0x%02X\n", md->pages[0], md->version[0]); @@ -422,7 +425,7 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf, numblocks = this->chipsize >> (this->bbt_erase_shift - 1); startblock = chip * numblocks; numblocks += startblock; - from = startblock << (this->bbt_erase_shift - 1); + from = (loff_t)startblock << (this->bbt_erase_shift - 1); } for (i = startblock; i < numblocks;) { @@ -440,8 +443,8 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf, if (ret) { this->bbt[i >> 3] |= 0x03 << (i & 0x6); MTDDEBUG (MTD_DEBUG_LEVEL0, - "Bad eraseblock %d at 0x%08x\n", - i >> 1, (unsigned int)from); + "Bad eraseblock %d at 0x%012llx\n", + i >> 1, (unsigned long long)from); mtd->ecc_stats.badblocks++; } @@ -507,7 +510,7 @@ static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr for (block = 0; block < td->maxblocks; block++) { int actblock = startblock + dir * block; - loff_t offs = actblock << this->bbt_erase_shift; + loff_t offs = (loff_t)actblock << this->bbt_erase_shift; /* Read first page */ scan_read_raw(mtd, buf, offs, mtd->writesize); @@ -731,7 +734,7 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf, memset(&einfo, 0, sizeof(einfo)); einfo.mtd = mtd; - einfo.addr = (unsigned long)to; + einfo.addr = to; einfo.len = 1 << this->bbt_erase_shift; res = nand_erase_nand(mtd, &einfo, 1); if (res < 0) @@ -741,8 +744,9 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf, if (res < 0) goto outerr; - printk(KERN_DEBUG "Bad block table written to 0x%08x, version " - "0x%02X\n", (unsigned int)to, td->version[chip]); + printk(KERN_DEBUG "Bad block table written to 0x%012llx, " + "version 0x%02X\n", (unsigned long long)to, + td->version[chip]); /* Mark it as used */ td->pages[chip] = page; @@ -922,7 +926,8 @@ static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td) newval = oldval | (0x2 << (block & 0x06)); this->bbt[(block >> 3)] = newval; if ((oldval != newval) && td->reserved_block_code) - nand_update_bbt(mtd, block << (this->bbt_erase_shift - 1)); + nand_update_bbt(mtd, (loff_t)block << + (this->bbt_erase_shift - 1)); continue; } update = 0; @@ -943,7 +948,8 @@ static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td) new ones have been marked, then we need to update the stored bbts. This should only happen once. */ if (update && td->reserved_block_code) - nand_update_bbt(mtd, (block - 2) << (this->bbt_erase_shift - 1)); + nand_update_bbt(mtd, (loff_t)(block - 2) << + (this->bbt_erase_shift - 1)); } } @@ -1039,7 +1045,6 @@ int nand_update_bbt(struct mtd_info *mtd, loff_t offs) if (!this->bbt || !td) return -EINVAL; - len = mtd->size >> (this->bbt_erase_shift + 2); /* Allocate a temporary buffer for one eraseblock incl. oob */ len = (1 << this->bbt_erase_shift); len += (len >> this->page_shift) * mtd->oobsize; diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index bec9277..29c42f7 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -41,10 +41,6 @@ #include <nand.h> #include <jffs2/jffs2.h> -#if !defined(CONFIG_SYS_64BIT_VSPRINTF) -#warning Please define CONFIG_SYS_64BIT_VSPRINTF for correct output! -#endif - typedef struct erase_info erase_info_t; typedef struct mtd_info mtd_info_t; @@ -452,7 +448,7 @@ static size_t get_len_incl_bad (nand_info_t *nand, loff_t offset, len_incl_bad += block_len; offset += block_len; - if ((offset + len_incl_bad) >= nand->size) + if (offset >= nand->size) break; } @@ -490,7 +486,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, len_incl_bad = get_len_incl_bad (nand, offset, *length); - if ((offset + len_incl_bad) >= nand->size) { + if ((offset + len_incl_bad) > nand->size) { printf ("Attempt to write outside the flash area\n"); return -EINVAL; } @@ -562,7 +558,7 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, len_incl_bad = get_len_incl_bad (nand, offset, *length); - if ((offset + len_incl_bad) >= nand->size) { + if ((offset + len_incl_bad) > nand->size) { printf ("Attempt to read outside the flash area\n"); return -EINVAL; } diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c index 3f15d2d..a27d47e 100644 --- a/drivers/mtd/nand/s3c2410_nand.c +++ b/drivers/mtd/nand/s3c2410_nand.c @@ -36,6 +36,21 @@ #define S3C2410_ADDR_NALE 4 #define S3C2410_ADDR_NCLE 8 +#ifdef CONFIG_NAND_SPL + +/* in the early stage of NAND flash booting, printf() is not available */ +#define printf(fmt, args...) + +static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + + for (i = 0; i < len; i++) + buf[i] = readb(this->IO_ADDR_R); +} +#endif + static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct nand_chip *chip = mtd->priv; @@ -83,9 +98,10 @@ void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) { - ecc_code[0] = NFECC0; - ecc_code[1] = NFECC1; - ecc_code[2] = NFECC2; + struct s3c2410_nand *nand = s3c2410_get_base_nand(); + ecc_code[0] = readb(&nand->NFECC); + ecc_code[1] = readb(&nand->NFECC + 1); + ecc_code[2] = readb(&nand->NFECC + 2); debugX(1, "s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", mtd , ecc_code[0], ecc_code[1], ecc_code[2]); @@ -130,8 +146,13 @@ int board_nand_init(struct nand_chip *nand) /* initialize nand_chip data structure */ nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA; + nand->select_chip = NULL; + /* read_buf and write_buf are default */ /* read_byte and write_byte are default */ +#ifdef CONFIG_NAND_SPL + nand->read_buf = nand_read_buf; +#endif /* hwcontrol always must be implemented */ nand->cmd_ctrl = s3c2410_hwcontrol; @@ -142,7 +163,9 @@ int board_nand_init(struct nand_chip *nand) nand->ecc.hwctl = s3c2410_nand_enable_hwecc; nand->ecc.calculate = s3c2410_nand_calculate_ecc; nand->ecc.correct = s3c2410_nand_correct_data; - nand->ecc.mode = NAND_ECC_HW3_512; + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; + nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; #else nand->ecc.mode = NAND_ECC_SOFT; #endif diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index 368fa6e..f9273ab 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -9,6 +9,11 @@ * auto-placement support, read-while load support, various fixes * Copyright (C) Nokia Corporation, 2007 * + * Rohit Hagargundgi <h.rohit at samsung.com>, + * Amul Kumar Saha <amul.saha@samsung.com>: + * Flex-OneNAND support + * Copyright (C) Samsung Electronics, 2009 + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -24,7 +29,7 @@ #include <malloc.h> /* It should access 16-bit instead of 8-bit */ -static inline void *memcpy_16(void *dst, const void *src, unsigned int len) +static void *memcpy_16(void *dst, const void *src, unsigned int len) { void *ret = dst; short *d = dst; @@ -37,6 +42,27 @@ static inline void *memcpy_16(void *dst, const void *src, unsigned int len) } /** + * onenand_oob_128 - oob info for Flex-Onenand with 4KB page + * For now, we expose only 64 out of 80 ecc bytes + */ +static struct nand_ecclayout onenand_oob_128 = { + .eccbytes = 64, + .eccpos = { + 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, + 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, + 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, + 102, 103, 104, 105 + }, + .oobfree = { + {2, 4}, {18, 4}, {34, 4}, {50, 4}, + {66, 4}, {82, 4}, {98, 4}, {114, 4} + } +}; + +/** * onenand_oob_64 - oob info for large (2KB) page */ static struct nand_ecclayout onenand_oob_64 = { @@ -74,6 +100,14 @@ static const unsigned char ffchars[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 48 */ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 64 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 80 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 96 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 112 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 128 */ }; /** @@ -180,6 +214,85 @@ static int onenand_buffer_address(int dataram1, int sectors, int count) } /** + * flexonenand_block - Return block number for flash address + * @param this - OneNAND device structure + * @param addr - Address for which block number is needed + */ +static unsigned int flexonenand_block(struct onenand_chip *this, loff_t addr) +{ + unsigned int boundary, blk, die = 0; + + if (ONENAND_IS_DDP(this) && addr >= this->diesize[0]) { + die = 1; + addr -= this->diesize[0]; + } + + boundary = this->boundary[die]; + + blk = addr >> (this->erase_shift - 1); + if (blk > boundary) + blk = (blk + boundary + 1) >> 1; + + blk += die ? this->density_mask : 0; + return blk; +} + +unsigned int onenand_block(struct onenand_chip *this, loff_t addr) +{ + if (!FLEXONENAND(this)) + return addr >> this->erase_shift; + return flexonenand_block(this, addr); +} + +/** + * flexonenand_addr - Return address of the block + * @this: OneNAND device structure + * @block: Block number on Flex-OneNAND + * + * Return address of the block + */ +static loff_t flexonenand_addr(struct onenand_chip *this, int block) +{ + loff_t ofs = 0; + int die = 0, boundary; + + if (ONENAND_IS_DDP(this) && block >= this->density_mask) { + block -= this->density_mask; + die = 1; + ofs = this->diesize[0]; + } + + boundary = this->boundary[die]; + ofs += (loff_t) block << (this->erase_shift - 1); + if (block > (boundary + 1)) + ofs += (loff_t) (block - boundary - 1) + << (this->erase_shift - 1); + return ofs; +} + +loff_t onenand_addr(struct onenand_chip *this, int block) +{ + if (!FLEXONENAND(this)) + return (loff_t) block << this->erase_shift; + return flexonenand_addr(this, block); +} + +/** + * flexonenand_region - [Flex-OneNAND] Return erase region of addr + * @param mtd MTD device structure + * @param addr address whose erase region needs to be identified + */ +int flexonenand_region(struct mtd_info *mtd, loff_t addr) +{ + int i; + + for (i = 0; i < mtd->numeraseregions; i++) + if (addr < mtd->eraseregions[i].offset) + break; + return i - 1; +} + +/** * onenand_get_density - [DEFAULT] Get OneNAND density * @param dev_id OneNAND device ID * @@ -205,10 +318,11 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t len) { struct onenand_chip *this = mtd->priv; - int value, readcmd = 0; + int value; int block, page; + /* Now we use page size operation */ - int sectors = 4, count = 4; + int sectors = 0, count = 0; /* Address translation */ switch (cmd) { @@ -220,15 +334,28 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, page = -1; break; + case FLEXONENAND_CMD_PI_ACCESS: + /* addr contains die index */ + block = addr * this->density_mask; + page = -1; + break; + case ONENAND_CMD_ERASE: case ONENAND_CMD_BUFFERRAM: - block = (int)(addr >> this->erase_shift); + block = onenand_block(this, addr); page = -1; break; + case FLEXONENAND_CMD_READ_PI: + cmd = ONENAND_CMD_READ; + block = addr * this->density_mask; + page = 0; + break; + default: - block = (int)(addr >> this->erase_shift); - page = (int)(addr >> this->page_shift); + block = onenand_block(this, addr); + page = (int) (addr + - onenand_addr(this, block)) >> this->page_shift; page &= this->page_mask; break; } @@ -240,8 +367,11 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); - /* Switch to the next data buffer */ - ONENAND_SET_NEXT_BUFFERRAM(this); + if (ONENAND_IS_MLC(this)) + ONENAND_SET_BUFFERRAM0(this); + else + /* Switch to the next data buffer */ + ONENAND_SET_NEXT_BUFFERRAM(this); return 0; } @@ -252,7 +382,7 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); - /* Write 'DFS, FBA' of Flash */ + /* Select DataRAM for DDP */ value = onenand_bufferram_address(this, block); this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); @@ -262,10 +392,14 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, int dataram; switch (cmd) { + case FLEXONENAND_CMD_RECOVER_LSB: case ONENAND_CMD_READ: case ONENAND_CMD_READOOB: - dataram = ONENAND_SET_NEXT_BUFFERRAM(this); - readcmd = 1; + if (ONENAND_IS_MLC(this)) + dataram = ONENAND_SET_BUFFERRAM0(this); + else + dataram = ONENAND_SET_NEXT_BUFFERRAM(this); + break; default: @@ -292,6 +426,29 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, } /** + * onenand_read_ecc - return ecc status + * @param this onenand chip structure + */ +static int onenand_read_ecc(struct onenand_chip *this) +{ + int ecc, i; + + if (!FLEXONENAND(this)) + return this->read_word(this->base + ONENAND_REG_ECC_STATUS); + + for (i = 0; i < 4; i++) { + ecc = this->read_word(this->base + + ((ONENAND_REG_ECC_STATUS + i) << 1)); + if (likely(!ecc)) + continue; + if (ecc & FLEXONENAND_UNCORRECTABLE_ERROR) + return ONENAND_ECC_2BIT_ALL; + } + + return 0; +} + +/** * onenand_wait - [DEFAULT] wait until the command is done * @param mtd MTD device structure * @param state state to select the max. timeout value @@ -305,7 +462,7 @@ static int onenand_wait(struct mtd_info *mtd, int state) struct onenand_chip *this = mtd->priv; unsigned int flags = ONENAND_INT_MASTER; unsigned int interrupt = 0; - unsigned int ctrl, ecc; + unsigned int ctrl; while (1) { interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); @@ -315,6 +472,14 @@ static int onenand_wait(struct mtd_info *mtd, int state) ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); + if (interrupt & ONENAND_INT_READ) { + int ecc = onenand_read_ecc(this); + if (ecc & ONENAND_ECC_2BIT_ALL) { + printk("onenand_wait: ECC error = 0x%04x\n", ecc); + return -EBADMSG; + } + } + if (ctrl & ONENAND_CTRL_ERROR) { printk("onenand_wait: controller error = 0x%04x\n", ctrl); if (ctrl & ONENAND_CTRL_LOCK) @@ -324,14 +489,6 @@ static int onenand_wait(struct mtd_info *mtd, int state) return -EIO; } - if (interrupt & ONENAND_INT_READ) { - ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS); - if (ecc & ONENAND_ECC_2BIT_ALL) { - MTDDEBUG (MTD_DEBUG_LEVEL0, - "onenand_wait: ECC error = 0x%04x\n", ecc); - return -EBADMSG; - } - } return 0; } @@ -499,7 +656,7 @@ static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr) if (found && ONENAND_IS_DDP(this)) { /* Select DataRAM for DDP */ - int block = (int) (addr >> this->erase_shift); + int block = onenand_block(this, addr); int value = onenand_bufferram_address(this, block); this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); } @@ -632,6 +789,45 @@ static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf, } /** + * onenand_recover_lsb - [Flex-OneNAND] Recover LSB page data + * @param mtd MTD device structure + * @param addr address to recover + * @param status return value from onenand_wait + * + * MLC NAND Flash cell has paired pages - LSB page and MSB page. LSB page has + * lower page address and MSB page has higher page address in paired pages. + * If power off occurs during MSB page program, the paired LSB page data can + * become corrupt. LSB page recovery read is a way to read LSB page though page + * data are corrupted. When uncorrectable error occurs as a result of LSB page + * read after power up, issue LSB page recovery read. + */ +static int onenand_recover_lsb(struct mtd_info *mtd, loff_t addr, int status) +{ + struct onenand_chip *this = mtd->priv; + int i; + + /* Recovery is only for Flex-OneNAND */ + if (!FLEXONENAND(this)) + return status; + + /* check if we failed due to uncorrectable error */ + if (status != -EBADMSG && status != ONENAND_BBT_READ_ECC_ERROR) + return status; + + /* check if address lies in MLC region */ + i = flexonenand_region(mtd, addr); + if (mtd->eraseregions[i].erasesize < (1 << this->erase_shift)) + return status; + + printk("onenand_recover_lsb:" + "Attempting to recover from uncorrectable read\n"); + + /* Issue the LSB page recovery command */ + this->command(mtd, FLEXONENAND_CMD_RECOVER_LSB, addr, this->writesize); + return this->wait(mtd, FL_READING); +} + +/** * onenand_read_ops_nolock - [OneNAND Interface] OneNAND read main and/or out-of-band * @param mtd MTD device structure * @param from offset to read from @@ -673,6 +869,7 @@ static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from, stats = mtd->ecc_stats; /* Read-while-load method */ + /* Note: We can't use this feature in MLC */ /* Do first load to bufferRAM */ if (read < len) { @@ -680,6 +877,8 @@ static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from, this->main_buf = buf; this->command(mtd, ONENAND_CMD_READ, from, writesize); ret = this->wait(mtd, FL_READING); + if (unlikely(ret)) + ret = onenand_recover_lsb(mtd, from, ret); onenand_update_bufferram(mtd, from, !ret); if (ret == -EBADMSG) ret = 0; @@ -694,7 +893,7 @@ static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from, while (!ret) { /* If there is more to load then start next load */ from += thislen; - if (read + thislen < len) { + if (!ONENAND_IS_MLC(this) && read + thislen < len) { this->main_buf = buf + thislen; this->command(mtd, ONENAND_CMD_READ, from, writesize); /* @@ -728,6 +927,16 @@ static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from, oobcolumn = 0; } + if (ONENAND_IS_MLC(this) && (read + thislen < len)) { + this->command(mtd, ONENAND_CMD_READ, from, writesize); + ret = this->wait(mtd, FL_READING); + if (unlikely(ret)) + ret = onenand_recover_lsb(mtd, from, ret); + onenand_update_bufferram(mtd, from, !ret); + if (ret == -EBADMSG) + ret = 0; + } + /* See if we are done */ read += thislen; if (read == len) @@ -735,16 +944,19 @@ static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from, /* Set up for next read from bufferRAM */ if (unlikely(boundary)) this->write_word(ONENAND_DDP_CHIP1, this->base + ONENAND_REG_START_ADDRESS2); - ONENAND_SET_NEXT_BUFFERRAM(this); + if (!ONENAND_IS_MLC(this)) + ONENAND_SET_NEXT_BUFFERRAM(this); buf += thislen; thislen = min_t(int, writesize, len - read); column = 0; - /* Now wait for load */ - ret = this->wait(mtd, FL_READING); - onenand_update_bufferram(mtd, from, !ret); - if (ret == -EBADMSG) - ret = 0; + if (!ONENAND_IS_MLC(this)) { + /* Now wait for load */ + ret = this->wait(mtd, FL_READING); + onenand_update_bufferram(mtd, from, !ret); + if (ret == -EBADMSG) + ret = 0; + } } /* @@ -781,7 +993,7 @@ static int onenand_read_oob_nolock(struct mtd_info *mtd, loff_t from, size_t len = ops->ooblen; mtd_oob_mode_t mode = ops->mode; u_char *buf = ops->oobbuf; - int ret = 0; + int ret = 0, readcmd; from += ops->ooboffs; @@ -812,16 +1024,21 @@ static int onenand_read_oob_nolock(struct mtd_info *mtd, loff_t from, stats = mtd->ecc_stats; + readcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_READ : ONENAND_CMD_READOOB; + while (read < len) { thislen = oobsize - column; thislen = min_t(int, thislen, len); this->spare_buf = buf; - this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize); + this->command(mtd, readcmd, from, mtd->oobsize); onenand_update_bufferram(mtd, from, 0); ret = this->wait(mtd, FL_READING); + if (unlikely(ret)) + ret = onenand_recover_lsb(mtd, from, ret); + if (ret && ret != -EBADMSG) { printk(KERN_ERR "onenand_read_oob_nolock: read failed = 0x%x\n", ret); break; @@ -945,9 +1162,12 @@ static int onenand_bbt_wait(struct mtd_info *mtd, int state) ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); if (interrupt & ONENAND_INT_READ) { - int ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS); - if (ecc & ONENAND_ECC_2BIT_ALL) + int ecc = onenand_read_ecc(this); + if (ecc & ONENAND_ECC_2BIT_ALL) { + printk(KERN_INFO "onenand_bbt_wait: ecc error = 0x%04x" + ", controller = 0x%04x\n", ecc, ctrl); return ONENAND_BBT_READ_ERROR; + } } else { printk(KERN_ERR "onenand_bbt_wait: read timeout!" "ctrl=0x%04x intr=0x%04x\n", ctrl, interrupt); @@ -976,12 +1196,14 @@ int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from, { struct onenand_chip *this = mtd->priv; int read = 0, thislen, column; - int ret = 0; + int ret = 0, readcmd; size_t len = ops->ooblen; u_char *buf = ops->oobbuf; MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_bbt_read_oob: from = 0x%08x, len = %zi\n", (unsigned int) from, len); + readcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_READ : ONENAND_CMD_READOOB; + /* Initialize return value */ ops->oobretlen = 0; @@ -1002,11 +1224,14 @@ int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from, thislen = min_t(int, thislen, len); this->spare_buf = buf; - this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize); + this->command(mtd, readcmd, from, mtd->oobsize); onenand_update_bufferram(mtd, from, 0); ret = this->bbt_wait(mtd, FL_READING); + if (unlikely(ret)) + ret = onenand_recover_lsb(mtd, from, ret); + if (ret) break; @@ -1044,9 +1269,11 @@ static int onenand_verify_oob(struct mtd_info *mtd, const u_char *buf, loff_t to { struct onenand_chip *this = mtd->priv; u_char *oob_buf = this->oob_buf; - int status, i; + int status, i, readcmd; - this->command(mtd, ONENAND_CMD_READOOB, to, mtd->oobsize); + readcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_READ : ONENAND_CMD_READOOB; + + this->command(mtd, readcmd, to, mtd->oobsize); onenand_update_bufferram(mtd, to, 0); status = this->wait(mtd, FL_READING); if (status) @@ -1291,7 +1518,7 @@ static int onenand_write_oob_nolock(struct mtd_info *mtd, loff_t to, { struct onenand_chip *this = mtd->priv; int column, ret = 0, oobsize; - int written = 0; + int written = 0, oobcmd; u_char *oobbuf; size_t len = ops->ooblen; const u_char *buf = ops->oobbuf; @@ -1333,6 +1560,8 @@ static int onenand_write_oob_nolock(struct mtd_info *mtd, loff_t to, oobbuf = this->oob_buf; + oobcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_PROG : ONENAND_CMD_PROGOOB; + /* Loop until all data write */ while (written < len) { int thislen = min_t(int, oobsize, len - written); @@ -1348,7 +1577,14 @@ static int onenand_write_oob_nolock(struct mtd_info *mtd, loff_t to, memcpy(oobbuf + column, buf, thislen); this->write_bufferram(mtd, 0, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize); - this->command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize); + if (ONENAND_IS_MLC(this)) { + /* Set main area of DataRAM to 0xff*/ + memset(this->page_buf, 0xff, mtd->writesize); + this->write_bufferram(mtd, 0, ONENAND_DATARAM, + this->page_buf, 0, mtd->writesize); + } + + this->command(mtd, oobcmd, to, mtd->oobsize); onenand_update_bufferram(mtd, to, 0); if (ONENAND_IS_2PLANE(this)) { @@ -1475,34 +1711,54 @@ int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) { struct onenand_chip *this = mtd->priv; unsigned int block_size; - loff_t addr; - int len; - int ret = 0; - - MTDDEBUG (MTD_DEBUG_LEVEL3, - "onenand_erase: start = 0x%08x, len = %i\n", - (unsigned int)instr->addr, (unsigned int)instr->len); + loff_t addr = instr->addr; + unsigned int len = instr->len; + int ret = 0, i; + struct mtd_erase_region_info *region = NULL; + unsigned int region_end = 0; - block_size = (1 << this->erase_shift); + MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n", + (unsigned int) addr, len); - /* Start address must align on block boundary */ - if (unlikely(instr->addr & (block_size - 1))) { - MTDDEBUG (MTD_DEBUG_LEVEL0, - "onenand_erase: Unaligned address\n"); + /* Do not allow erase past end of device */ + if (unlikely((len + addr) > mtd->size)) { + MTDDEBUG(MTD_DEBUG_LEVEL0, "onenand_erase:" + "Erase past end of device\n"); return -EINVAL; } - /* Length must align on block boundary */ - if (unlikely(instr->len & (block_size - 1))) { - MTDDEBUG (MTD_DEBUG_LEVEL0, - "onenand_erase: Length not block aligned\n"); - return -EINVAL; + if (FLEXONENAND(this)) { + /* Find the eraseregion of this address */ + i = flexonenand_region(mtd, addr); + region = &mtd->eraseregions[i]; + + block_size = region->erasesize; + region_end = region->offset + + region->erasesize * region->numblocks; + + /* Start address within region must align on block boundary. + * Erase region's start offset is always block start address. + */ + if (unlikely((addr - region->offset) & (block_size - 1))) { + MTDDEBUG(MTD_DEBUG_LEVEL0, "onenand_erase:" + " Unaligned address\n"); + return -EINVAL; + } + } else { + block_size = 1 << this->erase_shift; + + /* Start address must align on block boundary */ + if (unlikely(addr & (block_size - 1))) { + MTDDEBUG(MTD_DEBUG_LEVEL0, "onenand_erase:" + "Unaligned address\n"); + return -EINVAL; + } } - /* Do not allow erase past end of device */ - if (unlikely((instr->len + instr->addr) > mtd->size)) { + /* Length must align on block boundary */ + if (unlikely(len & (block_size - 1))) { MTDDEBUG (MTD_DEBUG_LEVEL0, - "onenand_erase: Erase past end of device\n"); + "onenand_erase: Length not block aligned\n"); return -EINVAL; } @@ -1512,9 +1768,6 @@ int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) onenand_get_device(mtd, FL_ERASING); /* Loop throught the pages */ - len = instr->len; - addr = instr->addr; - instr->state = MTD_ERASING; while (len) { @@ -1541,14 +1794,7 @@ int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) else MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_erase: " "Failed erase, block %d\n", - (unsigned)(addr >> this->erase_shift)); - if (ret == -EPERM) - printk("onenand_erase: " - "Device is write protected!!!\n"); - else - printk("onenand_erase: " - "Failed erase, block %d\n", - (unsigned)(addr >> this->erase_shift)); + onenand_block(this, addr)); instr->state = MTD_ERASE_FAILED; instr->fail_addr = addr; @@ -1557,6 +1803,23 @@ int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) len -= block_size; addr += block_size; + + if (addr == region_end) { + if (!len) + break; + region++; + + block_size = region->erasesize; + region_end = region->offset + + region->erasesize * region->numblocks; + + if (len & (block_size - 1)) { + /* This has been checked at MTD + * partitioning level. */ + printk("onenand_erase: Unaligned address\n"); + goto erase_exit; + } + } } instr->state = MTD_ERASE_DONE; @@ -1634,7 +1897,7 @@ static int onenand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) int block; /* Get block number */ - block = ((int) ofs) >> bbm->bbt_erase_shift; + block = onenand_block(this, ofs); if (bbm->bbt) bbm->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); @@ -1682,8 +1945,8 @@ static int onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs, size_t len, int int start, end, block, value, status; int wp_status_mask; - start = ofs >> this->erase_shift; - end = len >> this->erase_shift; + start = onenand_block(this, ofs); + end = onenand_block(this, ofs + len); if (cmd == ONENAND_CMD_LOCK) wp_status_mask = ONENAND_WP_LS; @@ -1718,7 +1981,7 @@ static int onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs, size_t len, int } /* Block lock scheme */ - for (block = start; block < start + end; block++) { + for (block = start; block < end; block++) { /* Set block address */ value = onenand_block_address(this, block); this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); @@ -1831,7 +2094,7 @@ static void onenand_unlock_all(struct mtd_info *mtd) { struct onenand_chip *this = mtd->priv; loff_t ofs = 0; - size_t len = this->chipsize; + size_t len = mtd->size; if (this->options & ONENAND_HAS_UNLOCK_ALL) { /* Set start block address */ @@ -1847,14 +2110,12 @@ static void onenand_unlock_all(struct mtd_info *mtd) & ONENAND_CTRL_ONGO) continue; - return; - /* Check lock status */ if (onenand_check_lock_status(this)) return; /* Workaround for all block unlock in DDP */ - if (ONENAND_IS_DDP(this)) { + if (ONENAND_IS_DDP(this) && !FLEXONENAND(this)) { /* All blocks on another chip */ ofs = this->chipsize >> 1; len = this->chipsize >> 1; @@ -1906,6 +2167,14 @@ static void onenand_check_features(struct mtd_info *mtd) break; } + if (ONENAND_IS_MLC(this)) + this->options &= ~ONENAND_HAS_2PLANE; + + if (FLEXONENAND(this)) { + this->options &= ~ONENAND_HAS_CONT_LOCK; + this->options |= ONENAND_HAS_UNLOCK_ALL; + } + if (this->options & ONENAND_HAS_CONT_LOCK) printk(KERN_DEBUG "Lock scheme is Continuous Lock\n"); if (this->options & ONENAND_HAS_UNLOCK_ALL) @@ -1922,16 +2191,18 @@ static void onenand_check_features(struct mtd_info *mtd) */ char *onenand_print_device_info(int device, int version) { - int vcc, demuxed, ddp, density; + int vcc, demuxed, ddp, density, flexonenand; char *dev_info = malloc(80); char *p = dev_info; vcc = device & ONENAND_DEVICE_VCC_MASK; demuxed = device & ONENAND_DEVICE_IS_DEMUX; ddp = device & ONENAND_DEVICE_IS_DDP; - density = device >> ONENAND_DEVICE_DENSITY_SHIFT; - p += sprintf(dev_info, "%sOneNAND%s %dMB %sV 16-bit (0x%02x)", + density = onenand_get_density(device); + flexonenand = device & DEVICE_IS_FLEXONENAND; + p += sprintf(dev_info, "%s%sOneNAND%s %dMB %sV 16-bit (0x%02x)", demuxed ? "" : "Muxed ", + flexonenand ? "Flex-" : "", ddp ? "(DDP)" : "", (16 << density), vcc ? "2.65/3.3" : "1.8", device); @@ -1957,7 +2228,7 @@ static int onenand_check_maf(int manuf) char *name; int i; - for (i = 0; size; i++) + for (i = 0; i < size; i++) if (manuf == onenand_manuf_ids[i].id) break; @@ -1974,6 +2245,265 @@ static int onenand_check_maf(int manuf) } /** +* flexonenand_get_boundary - Reads the SLC boundary +* @param onenand_info - onenand info structure +* +* Fill up boundary[] field in onenand_chip +**/ +static int flexonenand_get_boundary(struct mtd_info *mtd) +{ + struct onenand_chip *this = mtd->priv; + unsigned int die, bdry; + int ret, syscfg, locked; + + /* Disable ECC */ + syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1); + this->write_word((syscfg | 0x0100), this->base + ONENAND_REG_SYS_CFG1); + + for (die = 0; die < this->dies; die++) { + this->command(mtd, FLEXONENAND_CMD_PI_ACCESS, die, 0); + this->wait(mtd, FL_SYNCING); + + this->command(mtd, FLEXONENAND_CMD_READ_PI, die, 0); + ret = this->wait(mtd, FL_READING); + + bdry = this->read_word(this->base + ONENAND_DATARAM); + if ((bdry >> FLEXONENAND_PI_UNLOCK_SHIFT) == 3) + locked = 0; + else + locked = 1; + this->boundary[die] = bdry & FLEXONENAND_PI_MASK; + + this->command(mtd, ONENAND_CMD_RESET, 0, 0); + ret = this->wait(mtd, FL_RESETING); + + printk(KERN_INFO "Die %d boundary: %d%s\n", die, + this->boundary[die], locked ? "(Locked)" : "(Unlocked)"); + } + + /* Enable ECC */ + this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1); + return 0; +} + +/** + * flexonenand_get_size - Fill up fields in onenand_chip and mtd_info + * boundary[], diesize[], mtd->size, mtd->erasesize, + * mtd->eraseregions + * @param mtd - MTD device structure + */ +static void flexonenand_get_size(struct mtd_info *mtd) +{ + struct onenand_chip *this = mtd->priv; + int die, i, eraseshift, density; + int blksperdie, maxbdry; + loff_t ofs; + + density = onenand_get_density(this->device_id); + blksperdie = ((loff_t)(16 << density) << 20) >> (this->erase_shift); + blksperdie >>= ONENAND_IS_DDP(this) ? 1 : 0; + maxbdry = blksperdie - 1; + eraseshift = this->erase_shift - 1; + + mtd->numeraseregions = this->dies << 1; + + /* This fills up the device boundary */ + flexonenand_get_boundary(mtd); + die = 0; + ofs = 0; + i = -1; + for (; die < this->dies; die++) { + if (!die || this->boundary[die-1] != maxbdry) { + i++; + mtd->eraseregions[i].offset = ofs; + mtd->eraseregions[i].erasesize = 1 << eraseshift; + mtd->eraseregions[i].numblocks = + this->boundary[die] + 1; + ofs += mtd->eraseregions[i].numblocks << eraseshift; + eraseshift++; + } else { + mtd->numeraseregions -= 1; + mtd->eraseregions[i].numblocks += + this->boundary[die] + 1; + ofs += (this->boundary[die] + 1) << (eraseshift - 1); + } + if (this->boundary[die] != maxbdry) { + i++; + mtd->eraseregions[i].offset = ofs; + mtd->eraseregions[i].erasesize = 1 << eraseshift; + mtd->eraseregions[i].numblocks = maxbdry ^ + this->boundary[die]; + ofs += mtd->eraseregions[i].numblocks << eraseshift; + eraseshift--; + } else + mtd->numeraseregions -= 1; + } + + /* Expose MLC erase size except when all blocks are SLC */ + mtd->erasesize = 1 << this->erase_shift; + if (mtd->numeraseregions == 1) + mtd->erasesize >>= 1; + + printk(KERN_INFO "Device has %d eraseregions\n", mtd->numeraseregions); + for (i = 0; i < mtd->numeraseregions; i++) + printk(KERN_INFO "[offset: 0x%08llx, erasesize: 0x%05x," + " numblocks: %04u]\n", mtd->eraseregions[i].offset, + mtd->eraseregions[i].erasesize, + mtd->eraseregions[i].numblocks); + + for (die = 0, mtd->size = 0; die < this->dies; die++) { + this->diesize[die] = (loff_t) (blksperdie << this->erase_shift); + this->diesize[die] -= (loff_t) (this->boundary[die] + 1) + << (this->erase_shift - 1); + mtd->size += this->diesize[die]; + } +} + +/** + * flexonenand_check_blocks_erased - Check if blocks are erased + * @param mtd_info - mtd info structure + * @param start - first erase block to check + * @param end - last erase block to check + * + * Converting an unerased block from MLC to SLC + * causes byte values to change. Since both data and its ECC + * have changed, reads on the block give uncorrectable error. + * This might lead to the block being detected as bad. + * + * Avoid this by ensuring that the block to be converted is + * erased. + */ +static int flexonenand_check_blocks_erased(struct mtd_info *mtd, + int start, int end) +{ + struct onenand_chip *this = mtd->priv; + int i, ret; + int block; + struct mtd_oob_ops ops = { + .mode = MTD_OOB_PLACE, + .ooboffs = 0, + .ooblen = mtd->oobsize, + .datbuf = NULL, + .oobbuf = this->oob_buf, + }; + loff_t addr; + + printk(KERN_DEBUG "Check blocks from %d to %d\n", start, end); + + for (block = start; block <= end; block++) { + addr = flexonenand_addr(this, block); + if (onenand_block_isbad_nolock(mtd, addr, 0)) + continue; + + /* + * Since main area write results in ECC write to spare, + * it is sufficient to check only ECC bytes for change. + */ + ret = onenand_read_oob_nolock(mtd, addr, &ops); + if (ret) + return ret; + + for (i = 0; i < mtd->oobsize; i++) + if (this->oob_buf[i] != 0xff) + break; + + if (i != mtd->oobsize) { + printk(KERN_WARNING "Block %d not erased.\n", block); + return 1; + } + } + + return 0; +} + +/** + * flexonenand_set_boundary - Writes the SLC boundary + * @param mtd - mtd info structure + */ +int flexonenand_set_boundary(struct mtd_info *mtd, int die, + int boundary, int lock) +{ + struct onenand_chip *this = mtd->priv; + int ret, density, blksperdie, old, new, thisboundary; + loff_t addr; + + if (die >= this->dies) + return -EINVAL; + + if (boundary == this->boundary[die]) + return 0; + + density = onenand_get_density(this->device_id); + blksperdie = ((16 << density) << 20) >> this->erase_shift; + blksperdie >>= ONENAND_IS_DDP(this) ? 1 : 0; + + if (boundary >= blksperdie) { + printk("flexonenand_set_boundary:" + "Invalid boundary value. " + "Boundary not changed.\n"); + return -EINVAL; + } + + /* Check if converting blocks are erased */ + old = this->boundary[die] + (die * this->density_mask); + new = boundary + (die * this->density_mask); + ret = flexonenand_check_blocks_erased(mtd, min(old, new) + + 1, max(old, new)); + if (ret) { + printk(KERN_ERR "flexonenand_set_boundary: Please erase blocks before boundary change\n"); + return ret; + } + + this->command(mtd, FLEXONENAND_CMD_PI_ACCESS, die, 0); + this->wait(mtd, FL_SYNCING); + + /* Check is boundary is locked */ + this->command(mtd, FLEXONENAND_CMD_READ_PI, die, 0); + ret = this->wait(mtd, FL_READING); + + thisboundary = this->read_word(this->base + ONENAND_DATARAM); + if ((thisboundary >> FLEXONENAND_PI_UNLOCK_SHIFT) != 3) { + printk(KERN_ERR "flexonenand_set_boundary: boundary locked\n"); + goto out; + } + + printk(KERN_INFO "flexonenand_set_boundary: Changing die %d boundary: %d%s\n", + die, boundary, lock ? "(Locked)" : "(Unlocked)"); + + boundary &= FLEXONENAND_PI_MASK; + boundary |= lock ? 0 : (3 << FLEXONENAND_PI_UNLOCK_SHIFT); + + addr = die ? this->diesize[0] : 0; + this->command(mtd, ONENAND_CMD_ERASE, addr, 0); + ret = this->wait(mtd, FL_ERASING); + if (ret) { + printk("flexonenand_set_boundary:" + "Failed PI erase for Die %d\n", die); + goto out; + } + + this->write_word(boundary, this->base + ONENAND_DATARAM); + this->command(mtd, ONENAND_CMD_PROG, addr, 0); + ret = this->wait(mtd, FL_WRITING); + if (ret) { + printk("flexonenand_set_boundary:" + "Failed PI write for Die %d\n", die); + goto out; + } + + this->command(mtd, FLEXONENAND_CMD_PI_UPDATE, die, 0); + ret = this->wait(mtd, FL_WRITING); +out: + this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_REG_COMMAND); + this->wait(mtd, FL_RESETING); + if (!ret) + /* Recalculate device size on boundary change*/ + flexonenand_get_size(mtd); + + return ret; +} + +/** * onenand_probe - [OneNAND Interface] Probe the OneNAND device * @param mtd MTD device structure * @@ -2016,48 +2546,69 @@ static int onenand_probe(struct mtd_info *mtd) maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID); dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID); ver_id = this->read_word(this->base + ONENAND_REG_VERSION_ID); + this->technology = this->read_word(this->base + ONENAND_REG_TECHNOLOGY); /* Check OneNAND device */ if (maf_id != bram_maf_id || dev_id != bram_dev_id) return -ENXIO; - /* FIXME : Current OneNAND MTD doesn't support Flex-OneNAND */ - if (dev_id & (1 << 9)) { - printk("Not yet support Flex-OneNAND\n"); - return -ENXIO; - } - /* Flash device information */ mtd->name = onenand_print_device_info(dev_id, ver_id); this->device_id = dev_id; this->version_id = ver_id; density = onenand_get_density(dev_id); + if (FLEXONENAND(this)) { + this->dies = ONENAND_IS_DDP(this) ? 2 : 1; + /* Maximum possible erase regions */ + mtd->numeraseregions = this->dies << 1; + mtd->eraseregions = malloc(sizeof(struct mtd_erase_region_info) + * (this->dies << 1)); + if (!mtd->eraseregions) + return -ENOMEM; + } + + /* + * For Flex-OneNAND, chipsize represents maximum possible device size. + * mtd->size represents the actual device size. + */ this->chipsize = (16 << density) << 20; - /* Set density mask. it is used for DDP */ - if (ONENAND_IS_DDP(this)) - this->density_mask = (1 << (density + 6)); - else - this->density_mask = 0; /* OneNAND page size & block size */ /* The data buffer size is equal to page size */ mtd->writesize = this->read_word(this->base + ONENAND_REG_DATA_BUFFER_SIZE); + /* We use the full BufferRAM */ + if (ONENAND_IS_MLC(this)) + mtd->writesize <<= 1; + mtd->oobsize = mtd->writesize >> 5; /* Pagers per block is always 64 in OneNAND */ mtd->erasesize = mtd->writesize << 6; + /* + * Flex-OneNAND SLC area has 64 pages per block. + * Flex-OneNAND MLC area has 128 pages per block. + * Expose MLC erase size to find erase_shift and page_mask. + */ + if (FLEXONENAND(this)) + mtd->erasesize <<= 1; this->erase_shift = ffs(mtd->erasesize) - 1; this->page_shift = ffs(mtd->writesize) - 1; this->ppb_shift = (this->erase_shift - this->page_shift); this->page_mask = (mtd->erasesize / mtd->writesize) - 1; + /* Set density mask. it is used for DDP */ + if (ONENAND_IS_DDP(this)) + this->density_mask = this->chipsize >> (this->erase_shift + 1); /* It's real page size */ this->writesize = mtd->writesize; /* REVIST: Multichip handling */ - mtd->size = this->chipsize; + if (FLEXONENAND(this)) + flexonenand_get_size(mtd); + else + mtd->size = this->chipsize; /* Check OneNAND features */ onenand_check_features(mtd); @@ -2149,6 +2700,11 @@ int onenand_scan(struct mtd_info *mtd, int maxchips) * Allow subpage writes up to oobsize. */ switch (mtd->oobsize) { + case 128: + this->ecclayout = &onenand_oob_128; + mtd->subpage_sft = 0; + break; + case 64: this->ecclayout = &onenand_oob_64; mtd->subpage_sft = 2; diff --git a/drivers/mtd/onenand/onenand_bbt.c b/drivers/mtd/onenand/onenand_bbt.c index d538f95..1354877 100644 --- a/drivers/mtd/onenand/onenand_bbt.c +++ b/drivers/mtd/onenand/onenand_bbt.c @@ -69,6 +69,7 @@ static int create_bbt(struct mtd_info *mtd, uint8_t * buf, loff_t from; size_t readlen, ooblen; struct mtd_oob_ops ops; + int rgn; printk(KERN_INFO "Scanning device for bad blocks\n"); @@ -82,7 +83,7 @@ static int create_bbt(struct mtd_info *mtd, uint8_t * buf, /* Note that numblocks is 2 * (real numblocks) here; * see i += 2 below as it makses shifting and masking less painful */ - numblocks = mtd->size >> (bbm->bbt_erase_shift - 1); + numblocks = this->chipsize >> (bbm->bbt_erase_shift - 1); startblock = 0; from = 0; @@ -115,7 +116,12 @@ static int create_bbt(struct mtd_info *mtd, uint8_t * buf, } } i += 2; - from += (1 << bbm->bbt_erase_shift); + + if (FLEXONENAND(this)) { + rgn = flexonenand_region(mtd, from); + from += mtd->eraseregions[rgn].erasesize; + } else + from += (1 << bbm->bbt_erase_shift); } return 0; @@ -152,7 +158,7 @@ static int onenand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt) uint8_t res; /* Get block number * 2 */ - block = (int)(offs >> (bbm->bbt_erase_shift - 1)); + block = (int) (onenand_block(this, offs) << 1); res = (bbm->bbt[block >> 3] >> (block & 0x06)) & 0x03; MTDDEBUG (MTD_DEBUG_LEVEL2, @@ -191,7 +197,7 @@ int onenand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) struct bbm_info *bbm = this->bbm; int len, ret = 0; - len = mtd->size >> (this->erase_shift + 2); + len = this->chipsize >> (this->erase_shift + 2); /* Allocate memory (2bit per block) */ bbm->bbt = malloc(len); if (!bbm->bbt) { diff --git a/drivers/mtd/onenand/onenand_uboot.c b/drivers/mtd/onenand/onenand_uboot.c index 9823b5b..c642016 100644 --- a/drivers/mtd/onenand/onenand_uboot.c +++ b/drivers/mtd/onenand/onenand_uboot.c @@ -40,8 +40,10 @@ void onenand_init(void) onenand_scan(&onenand_mtd, 1); + if (onenand_chip.device_id & DEVICE_IS_FLEXONENAND) + puts("Flex-"); puts("OneNAND: "); - print_size(onenand_mtd.size, "\n"); + print_size(onenand_chip.chipsize, "\n"); #ifdef CONFIG_MTD_DEVICE /* diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index e3e0292..4f11b36 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -31,6 +31,7 @@ COBJS-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.o COBJS-$(CONFIG_SPI_FLASH_SPANSION) += spansion.o COBJS-$(CONFIG_SPI_FLASH_SST) += sst.o COBJS-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.o +COBJS-$(CONFIG_SPI_FLASH_WINBOND) += winbond.o COBJS-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o COBJS := $(COBJS-y) diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 25346a4..612f819 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -140,6 +140,11 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, flash = spi_flash_probe_macronix(spi, idcode); break; #endif +#ifdef CONFIG_SPI_FLASH_WINBOND + case 0xef: + flash = spi_flash_probe_winbond(spi, idcode); + break; +#endif #ifdef CONFIG_SPI_FLASH_STMICRO case 0x20: flash = spi_flash_probe_stmicro(spi, idcode); diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h index 0612383..08546fb 100644 --- a/drivers/mtd/spi/spi_flash_internal.h +++ b/drivers/mtd/spi/spi_flash_internal.h @@ -49,3 +49,4 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode); diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c index 9b910c1..ae0d047 100644 --- a/drivers/mtd/spi/stmicro.c +++ b/drivers/mtd/spi/stmicro.c @@ -281,7 +281,8 @@ int stmicro_erase(struct spi_flash *flash, u32 offset, size_t len) ret = 0; for (actual = 0; actual < len; actual++) { - cmd[1] = (offset / sector_size) + actual; + cmd[1] = offset >> 16; + offset += sector_size; ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0); if (ret < 0) { diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c new file mode 100644 index 0000000..b8da923 --- /dev/null +++ b/drivers/mtd/spi/winbond.c @@ -0,0 +1,332 @@ +/* + * Copyright 2008, Network Appliance Inc. + * Author: Jason McMullan <mcmullan <at> netapp.com> + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <malloc.h> +#include <spi_flash.h> + +#include "spi_flash_internal.h" + +/* M25Pxx-specific commands */ +#define CMD_W25_WREN 0x06 /* Write Enable */ +#define CMD_W25_WRDI 0x04 /* Write Disable */ +#define CMD_W25_RDSR 0x05 /* Read Status Register */ +#define CMD_W25_WRSR 0x01 /* Write Status Register */ +#define CMD_W25_READ 0x03 /* Read Data Bytes */ +#define CMD_W25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_W25_PP 0x02 /* Page Program */ +#define CMD_W25_SE 0x20 /* Sector (4K) Erase */ +#define CMD_W25_BE 0xd8 /* Block (64K) Erase */ +#define CMD_W25_CE 0xc7 /* Chip Erase */ +#define CMD_W25_DP 0xb9 /* Deep Power-down */ +#define CMD_W25_RES 0xab /* Release from DP, and Read Signature */ + +#define WINBOND_ID_W25X16 0x3015 +#define WINBOND_ID_W25X32 0x3016 +#define WINBOND_ID_W25X64 0x3017 + +#define WINBOND_SR_WIP (1 << 0) /* Write-in-Progress */ + +struct winbond_spi_flash_params { + uint16_t id; + /* Log2 of page size in power-of-two mode */ + uint8_t l2_page_size; + uint16_t pages_per_sector; + uint16_t sectors_per_block; + uint8_t nr_blocks; + const char *name; +}; + +/* spi_flash needs to be first so upper layers can free() it */ +struct winbond_spi_flash { + struct spi_flash flash; + const struct winbond_spi_flash_params *params; +}; + +static inline struct winbond_spi_flash * +to_winbond_spi_flash(struct spi_flash *flash) +{ + return container_of(flash, struct winbond_spi_flash, flash); +} + +static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { + { + .id = WINBOND_ID_W25X16, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "W25X16", + }, + { + .id = WINBOND_ID_W25X32, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 64, + .name = "W25X32", + }, + { + .id = WINBOND_ID_W25X64, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 128, + .name = "W25X64", + }, +}; + +static int winbond_wait_ready(struct spi_flash *flash, unsigned long timeout) +{ + struct spi_slave *spi = flash->spi; + unsigned long timebase; + int ret; + u8 status; + u8 cmd[4] = { CMD_W25_RDSR, 0xff, 0xff, 0xff }; + + ret = spi_xfer(spi, 32, &cmd[0], NULL, SPI_XFER_BEGIN); + if (ret) { + debug("SF: Failed to send command %02x: %d\n", cmd, ret); + return ret; + } + + timebase = get_timer(0); + do { + ret = spi_xfer(spi, 8, NULL, &status, 0); + if (ret) { + debug("SF: Failed to get status for cmd %02x: %d\n", cmd, ret); + return -1; + } + + if ((status & WINBOND_SR_WIP) == 0) + break; + + } while (get_timer(timebase) < timeout); + + spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); + + if ((status & WINBOND_SR_WIP) == 0) + return 0; + + debug("SF: Timed out on command %02x: %d\n", cmd, ret); + /* Timed out */ + return -1; +} + +/* + * Assemble the address part of a command for Winbond devices in + * non-power-of-two page size mode. + */ +static void winbond_build_address(struct winbond_spi_flash *stm, u8 *cmd, u32 offset) +{ + unsigned long page_addr; + unsigned long byte_addr; + unsigned long page_size; + unsigned int page_shift; + + /* + * The "extra" space per page is the power-of-two page size + * divided by 32. + */ + page_shift = stm->params->l2_page_size; + page_size = (1 << page_shift); + page_addr = offset / page_size; + byte_addr = offset % page_size; + + cmd[0] = page_addr >> (16 - page_shift); + cmd[1] = page_addr << (page_shift - 8) | (byte_addr >> 8); + cmd[2] = byte_addr; +} + +static int winbond_read_fast(struct spi_flash *flash, + u32 offset, size_t len, void *buf) +{ + struct winbond_spi_flash *stm = to_winbond_spi_flash(flash); + u8 cmd[5]; + + cmd[0] = CMD_READ_ARRAY_FAST; + winbond_build_address(stm, cmd + 1, offset); + cmd[4] = 0x00; + + return spi_flash_read_common(flash, cmd, sizeof(cmd), buf, len); +} + +static int winbond_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct winbond_spi_flash *stm = to_winbond_spi_flash(flash); + unsigned long page_addr; + unsigned long byte_addr; + unsigned long page_size; + unsigned int page_shift; + size_t chunk_len; + size_t actual; + int ret; + u8 cmd[4]; + + page_shift = stm->params->l2_page_size; + page_size = (1 << page_shift); + page_addr = offset / page_size; + byte_addr = offset % page_size; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: Unable to claim SPI bus\n"); + return ret; + } + + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[0] = CMD_W25_PP; + cmd[1] = page_addr >> (16 - page_shift); + cmd[2] = page_addr << (page_shift - 8) | (byte_addr >> 8); + cmd[3] = byte_addr; + debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n", + buf + actual, + cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); + + ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0); + if (ret < 0) { + debug("SF: Enabling Write failed\n"); + goto out; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + debug("SF: Winbond Page Program failed\n"); + goto out; + } + + ret = winbond_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret < 0) { + debug("SF: Winbond page programming timed out\n"); + goto out; + } + + page_addr++; + byte_addr = 0; + } + + debug("SF: Winbond: Successfully programmed %u bytes @ 0x%x\n", + len, offset); + ret = 0; + +out: + spi_release_bus(flash->spi); + return ret; +} + +int winbond_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + struct winbond_spi_flash *stm = to_winbond_spi_flash(flash); + unsigned long sector_size; + unsigned int page_shift; + size_t actual; + int ret; + u8 cmd[4]; + + /* + * This function currently uses sector erase only. + * probably speed things up by using bulk erase + * when possible. + */ + + page_shift = stm->params->l2_page_size; + sector_size = (1 << page_shift) * stm->params->pages_per_sector; + + if (offset % sector_size || len % sector_size) { + debug("SF: Erase offset/length not multiple of sector size\n"); + return -1; + } + + len /= sector_size; + cmd[0] = CMD_W25_SE; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: Unable to claim SPI bus\n"); + return ret; + } + + for (actual = 0; actual < len; actual++) { + winbond_build_address(stm, &cmd[1], offset + actual * sector_size); + printf("Erase: %02x %02x %02x %02x\n", + cmd[0], cmd[1], cmd[2], cmd[3]); + + ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0); + if (ret < 0) { + debug("SF: Enabling Write failed\n"); + goto out; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, NULL, 0); + if (ret < 0) { + debug("SF: Winbond sector erase failed\n"); + goto out; + } + + ret = winbond_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT); + if (ret < 0) { + debug("SF: Winbond sector erase timed out\n"); + goto out; + } + } + + debug("SF: Winbond: Successfully erased %u bytes @ 0x%x\n", + len * sector_size, offset); + ret = 0; + +out: + spi_release_bus(flash->spi); + return ret; +} + +struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode) +{ + const struct winbond_spi_flash_params *params; + unsigned long page_size; + struct winbond_spi_flash *stm; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(winbond_spi_flash_table); i++) { + params = &winbond_spi_flash_table[i]; + if (params->id == ((idcode[1] << 8) | idcode[2])) + break; + } + + if (i == ARRAY_SIZE(winbond_spi_flash_table)) { + debug("SF: Unsupported Winbond ID %02x%02x\n", + idcode[1], idcode[2]); + return NULL; + } + + stm = malloc(sizeof(struct winbond_spi_flash)); + if (!stm) { + debug("SF: Failed to allocate memory\n"); + return NULL; + } + + stm->params = params; + stm->flash.spi = spi; + stm->flash.name = params->name; + + /* Assuming power-of-two page size initially. */ + page_size = 1 << params->l2_page_size; + + stm->flash.write = winbond_write; + stm->flash.erase = winbond_erase; + stm->flash.read = winbond_read_fast; + stm->flash.size = page_size * params->pages_per_sector + * params->sectors_per_block + * params->nr_blocks; + + debug("SF: Detected %s with page size %u, total %u bytes\n", + params->name, page_size, stm->flash.size); + + return &stm->flash; +} diff --git a/drivers/net/Makefile b/drivers/net/Makefile index fc9887b..904727e 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -44,7 +44,7 @@ COBJS-$(CONFIG_GRETH) += greth.o COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o COBJS-$(CONFIG_KIRKWOOD_EGIGA) += kirkwood_egiga.o COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o -COBJS-$(CONFIG_DRIVER_LAN91C96) += lan91c96.o +COBJS-$(CONFIG_LAN91C96) += lan91c96.o COBJS-$(CONFIG_MACB) += macb.o COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o diff --git a/drivers/net/cs8900.c b/drivers/net/cs8900.c index 587f7f6..df36004 100644 --- a/drivers/net/cs8900.c +++ b/drivers/net/cs8900.c @@ -56,7 +56,7 @@ #define REG_READ(a) readl((a)) /* we don't need 16 bit initialisation on 32 bit bus */ -#define get_reg_init_bus(x) get_reg((x)) +#define get_reg_init_bus(r,d) get_reg((r),(d)) #else @@ -321,15 +321,16 @@ int cs8900_initialize(u8 dev_num, int base_addr) memset(priv, 0, sizeof(*priv)); priv->regs = (struct cs8900_regs *)base_addr; - /* Load MAC address from EEPROM */ - cs8900_get_enetaddr(dev); - dev->iobase = base_addr; dev->priv = priv; dev->init = cs8900_init; dev->halt = cs8900_halt; dev->send = cs8900_send; dev->recv = cs8900_recv; + + /* Load MAC address from EEPROM */ + cs8900_get_enetaddr(dev); + sprintf(dev->name, "%s-%hu", CS8900_DRIVERNAME, dev_num); eth_register(dev); diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index efe9135..a7fef56 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -75,7 +75,7 @@ TODO: external MII is not functional, only internal at the moment. #define DM9000_DMP_PACKET(func,packet,length) \ do { \ int i; \ - printf(func ": length: %d\n", length); \ + printf("%s: length: %d\n", func, length); \ for (i = 0; i < length; i++) { \ if (i % 8 == 0) \ printf("\n%s: %02x: ", func, i); \ @@ -284,7 +284,6 @@ static int dm9000_init(struct eth_device *dev, bd_t *bd) int i, oft, lnk; u8 io_mode; struct board_info *db = &dm9000_info; - uchar enetaddr[6]; DM9000_DBG("%s\n", __func__); @@ -342,20 +341,11 @@ static int dm9000_init(struct eth_device *dev, bd_t *bd) /* Clear interrupt status */ DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS); - /* Set Node address */ - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { -#if !defined(CONFIG_DM9000_NO_SROM) - for (i = 0; i < 3; i++) - dm9000_read_srom_word(i, enetaddr + 2 * i); - eth_setenv_enetaddr("ethaddr", enetaddr); -#endif - } - - printf("MAC: %pM\n", enetaddr); + printf("MAC: %pM\n", dev->enetaddr); /* fill device MAC address registers */ for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) - DM9000_iow(oft, enetaddr[i]); + DM9000_iow(oft, dev->enetaddr[i]); for (i = 0, oft = 0x16; i < 8; i++, oft++) DM9000_iow(oft, 0xff); @@ -558,6 +548,15 @@ void dm9000_write_srom_word(int offset, u16 val) } #endif +static void dm9000_get_enetaddr(struct eth_device *dev) +{ +#if !defined(CONFIG_DM9000_NO_SROM) + int i; + for (i = 0; i < 3; i++) + dm9000_read_srom_word(i, dev->enetaddr + (2 * i)); +#endif +} + /* Read a byte from I/O port */ @@ -621,6 +620,9 @@ int dm9000_initialize(bd_t *bis) { struct eth_device *dev = &(dm9000_info.netdev); + /* Load MAC address from EEPROM */ + dm9000_get_enetaddr(dev); + dev->init = dm9000_init; dev->halt = dm9000_halt; dev->send = dm9000_send; diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 7f9f783..2825342 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -79,6 +79,7 @@ static struct pci_device_id supported[] = { {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF}, diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index bd83a24..19116f2 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -55,6 +55,8 @@ struct fec_priv gfec = { .tbd_base = NULL, .tbd_index = 0, .bd = NULL, + .rdb_ptr = NULL, + .base_ptr = NULL, }; /* @@ -157,7 +159,9 @@ static int miiphy_restart_aneg(struct eth_device *dev) /* * Set the auto-negotiation advertisement register bits */ - miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_ANAR, 0x1e0); + miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_ANAR, + PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD | + PHY_ANLPAR_10 | PHY_ANLPAR_PSB_802_3); miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); @@ -228,7 +232,8 @@ static int fec_rbd_init(struct fec_priv *fec, int count, int size) uint32_t p = 0; /* reserve data memory and consider alignment */ - fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT); + if (fec->rdb_ptr == NULL) + fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT); p = (uint32_t)fec->rdb_ptr; if (!p) { puts("fec_imx27: not enough malloc memory!\n"); @@ -341,8 +346,8 @@ static int fec_open(struct eth_device *edev) writel(FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl); miiphy_wait_aneg(edev); - miiphy_speed(edev->name, 0); - miiphy_duplex(edev->name, 0); + miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR); + miiphy_duplex(edev->name, CONFIG_FEC_MXC_PHYADDR); /* * Enable SmartDMA receive task @@ -363,8 +368,9 @@ static int fec_init(struct eth_device *dev, bd_t* bd) * Datasheet forces the startaddress of each chain is 16 byte * aligned */ - fec->base_ptr = malloc((2 + FEC_RBD_NUM) * - sizeof(struct fec_bd) + DB_ALIGNMENT); + if (fec->base_ptr == NULL) + fec->base_ptr = malloc((2 + FEC_RBD_NUM) * + sizeof(struct fec_bd) + DB_ALIGNMENT); base = (uint32_t)fec->base_ptr; if (!base) { puts("fec_imx27: not enough malloc memory!\n"); @@ -444,6 +450,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd) */ if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { free(fec->base_ptr); + fec->base_ptr = NULL; return -ENOMEM; } fec_tbd_init(fec); @@ -491,8 +498,6 @@ static void fec_halt(struct eth_device *dev) writel(0, &fec->eth->ecntrl); fec->rbd_index = 0; fec->tbd_index = 0; - free(fec->rdb_ptr); - free(fec->base_ptr); debug("eth_halt: done\n"); } diff --git a/drivers/net/lan91c96.c b/drivers/net/lan91c96.c index 65565bc..90e4002 100644 --- a/drivers/net/lan91c96.c +++ b/drivers/net/lan91c96.c @@ -60,6 +60,7 @@ #include <common.h> #include <command.h> +#include <malloc.h> #include "lan91c96.h" #include <net.h> @@ -108,11 +109,7 @@ * *------------------------------------------------------------------------ */ -#define CARDNAME "LAN91C96" - -#define SMC_BASE_ADDRESS CONFIG_LAN91C96_BASE - -#define SMC_DEV_NAME "LAN91C96" +#define DRIVER_NAME "LAN91C96" #define SMC_ALLOC_MAX_TRY 5 #define SMC_TX_TIMEOUT 30 @@ -124,64 +121,12 @@ #undef USE_32_BIT #endif -/*----------------------------------------------------------------- - * - * The driver can be entered at any of the following entry points. - * - *----------------------------------------------------------------- - */ - -extern int eth_init (bd_t * bd); -extern void eth_halt (void); -extern int eth_rx (void); -extern int eth_send (volatile void *packet, int length); -#if 0 -static int smc_hw_init (void); -#endif - -/* - * This is called by register_netdev(). It is responsible for - * checking the portlist for the SMC9000 series chipset. If it finds - * one, then it will initialize the device, find the hardware information, - * and sets up the appropriate device parameters. - * NOTE: Interrupts are *OFF* when this procedure is called. - * - * NB:This shouldn't be static since it is referred to externally. - */ -int smc_init (void); - -/* - * This is called by unregister_netdev(). It is responsible for - * cleaning up before the driver is finally unregistered and discarded. - */ -void smc_destructor (void); - -/* - * The kernel calls this function when someone wants to use the device, - * typically 'ifconfig ethX up'. - */ -static int smc_open (bd_t *bd); - - -/* - * This is called by the kernel in response to 'ifconfig ethX down'. It - * is responsible for cleaning up everything that the open routine - * does, and maybe putting the card into a powerdown state. - */ -static int smc_close (void); - -/* - * This is a separate procedure to handle the receipt of a packet, to - * leave the interrupt code looking slightly cleaner - */ -static int smc_rcv (void); - /* See if a MAC address is defined in the current environment. If so use it. If not . print a warning and set the environment and other globals with the default. . If an EEPROM is present it really should be consulted. */ -int smc_get_ethaddr(bd_t *bd); -int get_rom_mac(unsigned char *v_rom_mac); +static int smc_get_ethaddr(bd_t *bd, struct eth_device *dev); +static int get_rom_mac(struct eth_device *dev, unsigned char *v_rom_mac); /* ------------------------------------------------------------ * Internal routines @@ -195,7 +140,7 @@ static unsigned char smc_mac_addr[] = { 0xc0, 0x00, 0x00, 0x1b, 0x62, 0x9c }; * the default mac address. */ -void smc_set_mac_addr (const unsigned char *addr) +static void smc_set_mac_addr(const unsigned char *addr) { int i; @@ -204,45 +149,21 @@ void smc_set_mac_addr (const unsigned char *addr) } } -/* - * smc_get_macaddr is no longer used. If you want to override the default - * mac address, call smc_get_mac_addr as a part of the board initialisation. - */ - -#if 0 -void smc_get_macaddr (byte * addr) -{ - /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */ - unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010); - int i; - - - for (i = 0; i < 6; i++) { - addr[0] = *(dnp1110_mac + 0); - addr[1] = *(dnp1110_mac + 1); - addr[2] = *(dnp1110_mac + 2); - addr[3] = *(dnp1110_mac + 3); - addr[4] = *(dnp1110_mac + 4); - addr[5] = *(dnp1110_mac + 5); - } -} -#endif /* 0 */ - /*********************************************** * Show available memory * ***********************************************/ -void dump_memory_info (void) +void dump_memory_info(struct eth_device *dev) { word mem_info; word old_bank; - old_bank = SMC_inw (LAN91C96_BANK_SELECT) & 0xF; + old_bank = SMC_inw(dev, LAN91C96_BANK_SELECT) & 0xF; - SMC_SELECT_BANK (0); - mem_info = SMC_inw (LAN91C96_MIR); + SMC_SELECT_BANK(dev, 0); + mem_info = SMC_inw(dev, LAN91C96_MIR); PRINTK2 ("Memory: %4d available\n", (mem_info >> 8) * 2048); - SMC_SELECT_BANK (old_bank); + SMC_SELECT_BANK(dev, old_bank); } /* @@ -252,28 +173,15 @@ void dump_memory_info (void) static void print_packet (byte *, int); #endif -/* #define tx_done(dev) 1 */ - - -/* this does a soft reset on the device */ -static void smc_reset (void); - -/* Enable Interrupts, Receive, and Transmit */ -static void smc_enable (void); - -/* this puts the device in an inactive state */ -static void smc_shutdown (void); - - -static int poll4int (byte mask, int timeout) +static int poll4int (struct eth_device *dev, byte mask, int timeout) { int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ; int is_timeout = 0; - word old_bank = SMC_inw (LAN91C96_BANK_SELECT); + word old_bank = SMC_inw(dev, LAN91C96_BANK_SELECT); PRINTK2 ("Polling...\n"); - SMC_SELECT_BANK (2); - while ((SMC_inw (LAN91C96_INT_STATS) & mask) == 0) { + SMC_SELECT_BANK(dev, 2); + while ((SMC_inw(dev, LAN91C96_INT_STATS) & mask) == 0) { if (get_timer (0) >= tmo) { is_timeout = 1; break; @@ -281,7 +189,7 @@ static int poll4int (byte mask, int timeout) } /* restore old bank selection */ - SMC_SELECT_BANK (old_bank); + SMC_SELECT_BANK(dev, old_bank); if (is_timeout) return 1; @@ -290,7 +198,7 @@ static int poll4int (byte mask, int timeout) } /* - * Function: smc_reset( void ) + * Function: smc_reset * Purpose: * This sets the SMC91111 chip to its normal state, hopefully from whatever * mess that any other DOS driver has put it in. @@ -306,28 +214,28 @@ static int poll4int (byte mask, int timeout) * 5. clear all interrupts * */ -static void smc_reset (void) +static void smc_reset(struct eth_device *dev) { - PRINTK2 ("%s:smc_reset\n", SMC_DEV_NAME); + PRINTK2("%s:smc_reset\n", dev->name); /* This resets the registers mostly to defaults, but doesn't affect EEPROM. That seems unnecessary */ - SMC_SELECT_BANK (0); - SMC_outw (LAN91C96_RCR_SOFT_RST, LAN91C96_RCR); + SMC_SELECT_BANK(dev, 0); + SMC_outw(dev, LAN91C96_RCR_SOFT_RST, LAN91C96_RCR); udelay (10); /* Disable transmit and receive functionality */ - SMC_outw (0, LAN91C96_RCR); - SMC_outw (0, LAN91C96_TCR); + SMC_outw(dev, 0, LAN91C96_RCR); + SMC_outw(dev, 0, LAN91C96_TCR); /* set the control register */ - SMC_SELECT_BANK (1); - SMC_outw (SMC_inw (LAN91C96_CONTROL) | LAN91C96_CTR_BIT_8, + SMC_SELECT_BANK(dev, 1); + SMC_outw(dev, SMC_inw(dev, LAN91C96_CONTROL) | LAN91C96_CTR_BIT_8, LAN91C96_CONTROL); /* Disable all interrupts */ - SMC_outb (0, LAN91C96_INT_MASK); + SMC_outb(dev, 0, LAN91C96_INT_MASK); } /* @@ -338,24 +246,24 @@ static void smc_reset (void) * 2. Enable the transmitter * 3. Enable the receiver */ -static void smc_enable () +static void smc_enable(struct eth_device *dev) { - PRINTK2 ("%s:smc_enable\n", SMC_DEV_NAME); - SMC_SELECT_BANK (0); + PRINTK2("%s:smc_enable\n", dev->name); + SMC_SELECT_BANK(dev, 0); /* Initialize the Memory Configuration Register. See page 49 of the LAN91C96 data sheet for details. */ - SMC_outw (LAN91C96_MCR_TRANSMIT_PAGES, LAN91C96_MCR); + SMC_outw(dev, LAN91C96_MCR_TRANSMIT_PAGES, LAN91C96_MCR); /* Initialize the Transmit Control Register */ - SMC_outw (LAN91C96_TCR_TXENA, LAN91C96_TCR); + SMC_outw(dev, LAN91C96_TCR_TXENA, LAN91C96_TCR); /* Initialize the Receive Control Register * FIXME: * The promiscuous bit set because I could not receive ARP reply * packets from the server when I send a ARP request. It only works * when I set the promiscuous bit */ - SMC_outw (LAN91C96_RCR_RXEN | LAN91C96_RCR_PRMS, LAN91C96_RCR); + SMC_outw(dev, LAN91C96_RCR_RXEN | LAN91C96_RCR_PRMS, LAN91C96_RCR); } /* @@ -372,18 +280,18 @@ static void smc_enable () * the manual says that it will wake up in response to any I/O requests * in the register space. Empirical results do not show this working. */ -static void smc_shutdown () +static void smc_shutdown(struct eth_device *dev) { - PRINTK2 (CARDNAME ":smc_shutdown\n"); + PRINTK2("%s:smc_shutdown\n", dev->name); /* no more interrupts for me */ - SMC_SELECT_BANK (2); - SMC_outb (0, LAN91C96_INT_MASK); + SMC_SELECT_BANK(dev, 2); + SMC_outb(dev, 0, LAN91C96_INT_MASK); /* and tell the card to stay away from that nasty outside world */ - SMC_SELECT_BANK (0); - SMC_outb (0, LAN91C96_RCR); - SMC_outb (0, LAN91C96_TCR); + SMC_SELECT_BANK(dev, 0); + SMC_outb(dev, 0, LAN91C96_RCR); + SMC_outb(dev, 0, LAN91C96_TCR); } @@ -405,7 +313,8 @@ static void smc_shutdown () * Enable the transmit interrupt, so I know if it failed * Free the kernel data if I actually sent it. */ -static int smc_send_packet (volatile void *packet, int packet_length) +static int smc_send_packet(struct eth_device *dev, volatile void *packet, + int packet_length) { byte packet_no; unsigned long ioaddr; @@ -417,7 +326,7 @@ static int smc_send_packet (volatile void *packet, int packet_length) byte status; - PRINTK3 ("%s:smc_hardware_send_packet\n", SMC_DEV_NAME); + PRINTK3("%s:smc_hardware_send_packet\n", dev->name); length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN; @@ -437,30 +346,31 @@ static int smc_send_packet (volatile void *packet, int packet_length) numPages >>= 8; /* Divide by 256 */ if (numPages > 7) { - printf ("%s: Far too big packet error. \n", SMC_DEV_NAME); + printf("%s: Far too big packet error. \n", dev->name); return 0; } /* now, try to allocate the memory */ - SMC_SELECT_BANK (2); - SMC_outw (LAN91C96_MMUCR_ALLOC_TX | numPages, LAN91C96_MMU); + SMC_SELECT_BANK(dev, 2); + SMC_outw(dev, LAN91C96_MMUCR_ALLOC_TX | numPages, LAN91C96_MMU); again: try++; time_out = MEMORY_WAIT_TIME; do { - status = SMC_inb (LAN91C96_INT_STATS); + status = SMC_inb(dev, LAN91C96_INT_STATS); if (status & LAN91C96_IST_ALLOC_INT) { - SMC_outb (LAN91C96_IST_ALLOC_INT, LAN91C96_INT_STATS); + SMC_outb(dev, LAN91C96_IST_ALLOC_INT, + LAN91C96_INT_STATS); break; } } while (--time_out); if (!time_out) { PRINTK2 ("%s: memory allocation, try %d failed ...\n", - SMC_DEV_NAME, try); + dev->name, try); if (try < SMC_ALLOC_MAX_TRY) goto again; else @@ -468,30 +378,30 @@ static int smc_send_packet (volatile void *packet, int packet_length) } PRINTK2 ("%s: memory allocation, try %d succeeded ...\n", - SMC_DEV_NAME, try); + dev->name, try); /* I can send the packet now.. */ - ioaddr = SMC_BASE_ADDRESS; + ioaddr = dev->iobase; buf = (byte *) packet; /* If I get here, I _know_ there is a packet slot waiting for me */ - packet_no = SMC_inb (LAN91C96_ARR); + packet_no = SMC_inb(dev, LAN91C96_ARR); if (packet_no & LAN91C96_ARR_FAILED) { /* or isn't there? BAD CHIP! */ - printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME); + printf("%s: Memory allocation failed. \n", dev->name); return 0; } /* we have a packet address, so tell the card to use it */ - SMC_outb (packet_no, LAN91C96_PNR); + SMC_outb(dev, packet_no, LAN91C96_PNR); /* point to the beginning of the packet */ - SMC_outw (LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER); + SMC_outw(dev, LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER); - PRINTK3 ("%s: Trying to xmit packet of length %x\n", - SMC_DEV_NAME, length); + PRINTK3("%s: Trying to xmit packet of length %x\n", + dev->name, length); #if SMC_DEBUG > 2 printf ("Transmitting Packet\n"); @@ -501,11 +411,11 @@ static int smc_send_packet (volatile void *packet, int packet_length) /* send the packet length ( +6 for status, length and ctl byte ) and the status word ( set to zeros ) */ #ifdef USE_32_BIT - SMC_outl ((length + 6) << 16, LAN91C96_DATA_HIGH); + SMC_outl(dev, (length + 6) << 16, LAN91C96_DATA_HIGH); #else - SMC_outw (0, LAN91C96_DATA_HIGH); + SMC_outw(dev, 0, LAN91C96_DATA_HIGH); /* send the packet length ( +6 for status words, length, and ctl */ - SMC_outw ((length + 6), LAN91C96_DATA_HIGH); + SMC_outw(dev, (length + 6), LAN91C96_DATA_HIGH); #endif /* USE_32_BIT */ /* send the actual data @@ -516,54 +426,52 @@ static int smc_send_packet (volatile void *packet, int packet_length) * almost as much time as is saved? */ #ifdef USE_32_BIT - SMC_outsl (LAN91C96_DATA_HIGH, buf, length >> 2); + SMC_outsl(dev, LAN91C96_DATA_HIGH, buf, length >> 2); if (length & 0x2) - SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))), + SMC_outw(dev, *((word *) (buf + (length & 0xFFFFFFFC))), LAN91C96_DATA_HIGH); #else - SMC_outsw (LAN91C96_DATA_HIGH, buf, (length) >> 1); + SMC_outsw(dev, LAN91C96_DATA_HIGH, buf, (length) >> 1); #endif /* USE_32_BIT */ /* Send the last byte, if there is one. */ if ((length & 1) == 0) { - SMC_outw (0, LAN91C96_DATA_HIGH); + SMC_outw(dev, 0, LAN91C96_DATA_HIGH); } else { - SMC_outw (buf[length - 1] | 0x2000, LAN91C96_DATA_HIGH); + SMC_outw(dev, buf[length - 1] | 0x2000, LAN91C96_DATA_HIGH); } /* and let the chipset deal with it */ - SMC_outw (LAN91C96_MMUCR_ENQUEUE, LAN91C96_MMU); + SMC_outw(dev, LAN91C96_MMUCR_ENQUEUE, LAN91C96_MMU); /* poll for TX INT */ - if (poll4int (LAN91C96_MSK_TX_INT, SMC_TX_TIMEOUT)) { + if (poll4int (dev, LAN91C96_MSK_TX_INT, SMC_TX_TIMEOUT)) { /* sending failed */ - PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME); + PRINTK2("%s: TX timeout, sending failed...\n", dev->name); /* release packet */ - SMC_outw (LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU); + SMC_outw(dev, LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU); /* wait for MMU getting ready (low) */ - while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) { + while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) udelay (10); - } - PRINTK2 ("MMU ready\n"); + PRINTK2("MMU ready\n"); return 0; } else { /* ack. int */ - SMC_outw (LAN91C96_IST_TX_INT, LAN91C96_INT_STATS); + SMC_outw(dev, LAN91C96_IST_TX_INT, LAN91C96_INT_STATS); - PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME, length); + PRINTK2("%s: Sent packet of length %d \n", dev->name, length); /* release packet */ - SMC_outw (LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU); + SMC_outw(dev, LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU); /* wait for MMU getting ready (low) */ - while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) { + while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) udelay (10); - } PRINTK2 ("MMU ready\n"); } @@ -571,20 +479,6 @@ static int smc_send_packet (volatile void *packet, int packet_length) return length; } -/*------------------------------------------------------------------------- - * smc_destructor( struct net_device * dev ) - * Input parameters: - * dev, pointer to the device structure - * - * Output: - * None. - *-------------------------------------------------------------------------- - */ -void smc_destructor () -{ - PRINTK2 (CARDNAME ":smc_destructor\n"); -} - /* * Open and Initialize the board @@ -592,20 +486,20 @@ void smc_destructor () * Set up everything, reset the card, etc .. * */ -static int smc_open (bd_t *bd) +static int smc_open(bd_t *bd, struct eth_device *dev) { int i, err; /* used to set hw ethernet address */ - PRINTK2 ("%s:smc_open\n", SMC_DEV_NAME); + PRINTK2("%s:smc_open\n", dev->name); /* reset the hardware */ - smc_reset (); - smc_enable (); - - SMC_SELECT_BANK (1); + smc_reset(dev); + smc_enable(dev); - err = smc_get_ethaddr (bd); /* set smc_mac_addr, and sync it with u-boot globals */ + SMC_SELECT_BANK(dev, 1); + /* set smc_mac_addr, and sync it with u-boot globals */ + err = smc_get_ethaddr(bd, dev); if (err < 0) return -1; #ifdef USE_32_BIT @@ -614,11 +508,11 @@ static int smc_open (bd_t *bd) address = smc_mac_addr[i + 1] << 8; address |= smc_mac_addr[i]; - SMC_outw (address, LAN91C96_IA0 + i); + SMC_outw(dev, address, LAN91C96_IA0 + i); } #else for (i = 0; i < 6; i++) - SMC_outb (smc_mac_addr[i], LAN91C96_IA0 + i); + SMC_outb(dev, smc_mac_addr[i], LAN91C96_IA0 + i); #endif return 0; } @@ -635,7 +529,7 @@ static int smc_open (bd_t *bd) * o otherwise, read in the packet *------------------------------------------------------------- */ -static int smc_rcv () +static int smc_rcv(struct eth_device *dev) { int packet_number; word status; @@ -647,26 +541,26 @@ static int smc_rcv () #endif - SMC_SELECT_BANK (2); - packet_number = SMC_inw (LAN91C96_FIFO); + SMC_SELECT_BANK(dev, 2); + packet_number = SMC_inw(dev, LAN91C96_FIFO); if (packet_number & LAN91C96_FIFO_RXEMPTY) { return 0; } - PRINTK3 ("%s:smc_rcv\n", SMC_DEV_NAME); + PRINTK3("%s:smc_rcv\n", dev->name); /* start reading from the start of the packet */ - SMC_outw (LAN91C96_PTR_READ | LAN91C96_PTR_RCV | + SMC_outw(dev, LAN91C96_PTR_READ | LAN91C96_PTR_RCV | LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER); /* First two words are status and packet_length */ #ifdef USE_32_BIT - stat_len = SMC_inl (LAN91C96_DATA_HIGH); + stat_len = SMC_inl(dev, LAN91C96_DATA_HIGH); status = stat_len & 0xffff; packet_length = stat_len >> 16; #else - status = SMC_inw (LAN91C96_DATA_HIGH); - packet_length = SMC_inw (LAN91C96_DATA_HIGH); + status = SMC_inw(dev, LAN91C96_DATA_HIGH); + packet_length = SMC_inw(dev, LAN91C96_DATA_HIGH); #endif packet_length &= 0x07ff; /* mask off top bits */ @@ -690,13 +584,14 @@ static int smc_rcv () to send the DWORDs or the bytes first, or some mixture. A mixture might improve already slow PIO performance */ - SMC_insl (LAN91C96_DATA_HIGH, NetRxPackets[0], packet_length >> 2); + SMC_insl(dev, LAN91C96_DATA_HIGH, NetRxPackets[0], + packet_length >> 2); /* read the left over bytes */ if (packet_length & 3) { int i; byte *tail = (byte *) (NetRxPackets[0] + (packet_length & ~3)); - dword leftover = SMC_inl (LAN91C96_DATA_HIGH); + dword leftover = SMC_inl(dev, LAN91C96_DATA_HIGH); for (i = 0; i < (packet_length & 3); i++) *tail++ = (byte) (leftover >> (8 * i)) & 0xff; @@ -704,13 +599,14 @@ static int smc_rcv () #else PRINTK3 (" Reading %d words and %d byte(s) \n", (packet_length >> 1), packet_length & 1); - SMC_insw (LAN91C96_DATA_HIGH, NetRxPackets[0], packet_length >> 1); + SMC_insw(dev, LAN91C96_DATA_HIGH, NetRxPackets[0], + packet_length >> 1); #endif /* USE_32_BIT */ #if SMC_DEBUG > 2 printf ("Receiving Packet\n"); - print_packet (NetRxPackets[0], packet_length); + print_packet((byte *)NetRxPackets[0], packet_length); #endif } else { /* error ... */ @@ -718,13 +614,13 @@ static int smc_rcv () is_error = 1; } - while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) + while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) udelay (1); /* Wait until not busy */ /* error or good, tell the card to get rid of this packet */ - SMC_outw (LAN91C96_MMUCR_RELEASE_RX, LAN91C96_MMU); + SMC_outw(dev, LAN91C96_MMUCR_RELEASE_RX, LAN91C96_MMU); - while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) + while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) udelay (1); /* Wait until not busy */ if (!is_error) { @@ -745,18 +641,18 @@ static int smc_rcv () * an 'ifconfig ethX down' * -----------------------------------------------------*/ -static int smc_close () +static int smc_close(struct eth_device *dev) { - PRINTK2 ("%s:smc_close\n", SMC_DEV_NAME); + PRINTK2("%s:smc_close\n", dev->name); /* clear everything */ - smc_shutdown (); + smc_shutdown(dev); return 0; } #if SMC_DEBUG > 2 -static void print_packet (byte * buf, int length) +static void print_packet(byte *buf, int length) { #if 0 int i; @@ -792,86 +688,40 @@ static void print_packet (byte * buf, int length) } #endif /* SMC_DEBUG > 2 */ -int eth_init (bd_t * bd) -{ - return (smc_open(bd)); -} - -void eth_halt () +static int lan91c96_init(struct eth_device *dev, bd_t *bd) { - smc_close (); + return smc_open(bd, dev); } -int eth_rx () +static void lan91c96_halt(struct eth_device *dev) { - return smc_rcv (); + smc_close(dev); } -int eth_send (volatile void *packet, int length) +static int lan91c96_recv(struct eth_device *dev) { - return smc_send_packet (packet, length); + return smc_rcv(dev); } - -#if 0 -/*------------------------------------------------------------------------- - * smc_hw_init() - * - * Function: - * Reset and enable the device, check if the I/O space location - * is correct - * - * Input parameters: - * None - * - * Output: - * 0 --> success - * 1 --> error - *-------------------------------------------------------------------------- - */ -static int smc_hw_init () +static int lan91c96_send(struct eth_device *dev, volatile void *packet, + int length) { - unsigned short status_test; - - /* The attribute register of the LAN91C96 is located at address - 0x0e000000 on the lubbock platform */ - volatile unsigned *attaddr = (unsigned *) (0x0e000000); - - /* first reset, then enable the device. Sequence is critical */ - attaddr[LAN91C96_ECOR] |= LAN91C96_ECOR_SRESET; - udelay (100); - attaddr[LAN91C96_ECOR] &= ~LAN91C96_ECOR_SRESET; - attaddr[LAN91C96_ECOR] |= LAN91C96_ECOR_ENABLE; - - /* force 16-bit mode */ - attaddr[LAN91C96_ECSR] &= ~LAN91C96_ECSR_IOIS8; - udelay (100); - - /* check if the I/O address is correct, the upper byte of the - bank select register should read 0x33 */ - - status_test = SMC_inw (LAN91C96_BANK_SELECT); - if ((status_test & 0xFF00) != 0x3300) { - printf ("Failed to initialize ethernetchip\n"); - return 1; - } - return 0; + return smc_send_packet(dev, packet, length); } -#endif /* 0 */ -/* smc_get_ethaddr (bd_t * bd) +/* smc_get_ethaddr * * This checks both the environment and the ROM for an ethernet address. If * found, the environment takes precedence. */ -int smc_get_ethaddr (bd_t * bd) +static int smc_get_ethaddr(bd_t *bd, struct eth_device *dev) { uchar v_mac[6]; if (!eth_getenv_enetaddr("ethaddr", v_mac)) { /* get ROM mac value if any */ - if (!get_rom_mac(v_mac)) { + if (!get_rom_mac(dev, v_mac)) { printf("\n*** ERROR: ethaddr is NOT set !!\n"); return -1; } @@ -888,7 +738,7 @@ int smc_get_ethaddr (bd_t * bd) * Note, this has omly been tested for the OMAP730 P2. */ -int get_rom_mac (unsigned char *v_rom_mac) +static int get_rom_mac(struct eth_device *dev, unsigned char *v_rom_mac) { #ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */ char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 }; @@ -897,11 +747,75 @@ int get_rom_mac (unsigned char *v_rom_mac) return (1); #else int i; - SMC_SELECT_BANK (1); + SMC_SELECT_BANK(dev, 1); for (i=0; i<6; i++) { - v_rom_mac[i] = SMC_inb (LAN91C96_IA0 + i); + v_rom_mac[i] = SMC_inb(dev, LAN91C96_IA0 + i); } return (1); #endif } + +/* Structure to detect the device IDs */ +struct id_type { + u8 id; + char *name; +}; +static struct id_type supported_chips[] = { + {0, ""}, /* Dummy entry to prevent id check failure */ + {9, "LAN91C110"}, + {8, "LAN91C100FD"}, + {7, "LAN91C100"}, + {5, "LAN91C95"}, + {4, "LAN91C94/LAN91C96"}, + {3, "LAN91C90/LAN91C92"}, +}; +/* lan91c96_detect_chip + * See: + * http://www.embeddedsys.com/subpages/resources/images/documents/LAN91C96_datasheet.pdf + * page 71 - that is the closest we get to detect this device + */ +static int lan91c96_detect_chip(struct eth_device *dev) +{ + u8 chip_id; + int r; + SMC_SELECT_BANK(dev, 3); + chip_id = SMC_inw(dev, 0xA) & LAN91C96_REV_REVID; + SMC_SELECT_BANK(dev, 0); + for (r = 0; r < sizeof(supported_chips) / sizeof(struct id_type); r++) + if (chip_id == supported_chips[r].id) + return r; + return 0; +} + +int lan91c96_initialize(u8 dev_num, int base_addr) +{ + struct eth_device *dev; + int r = 0; + + dev = malloc(sizeof(*dev)); + if (!dev) { + free(dev); + return 0; + } + memset(dev, 0, sizeof(*dev)); + + dev->iobase = base_addr; + + /* Try to detect chip. Will fail if not present. */ + r = lan91c96_detect_chip(dev); + if (!r) { + free(dev); + return 0; + } + get_rom_mac(dev, dev->enetaddr); + + dev->init = lan91c96_init; + dev->halt = lan91c96_halt; + dev->send = lan91c96_send; + dev->recv = lan91c96_recv; + sprintf(dev->name, "%s-%hu", supported_chips[r].name, dev_num); + + eth_register(dev); + return 0; +} diff --git a/drivers/net/lan91c96.h b/drivers/net/lan91c96.h index 5beddda..6fbb0e3 100644 --- a/drivers/net/lan91c96.h +++ b/drivers/net/lan91c96.h @@ -46,14 +46,6 @@ #include <asm/io.h> #include <config.h> -/* - * This function may be called by the board specific initialisation code - * in order to override the default mac address. - */ - -void smc_set_mac_addr(const unsigned char *addr); - - /* I want some simple types */ typedef unsigned char byte; @@ -86,66 +78,71 @@ typedef unsigned long int dword; #define SMC_IO_SHIFT 0 #endif -#define SMCREG(r) (SMC_BASE_ADDRESS+((r)<<SMC_IO_SHIFT)) +#define SMCREG(edev, r) ((edev)->iobase+((r)<<SMC_IO_SHIFT)) -#define SMC_inl(r) (*((volatile dword *)SMCREG(r))) -#define SMC_inw(r) (*((volatile word *)SMCREG(r))) -#define SMC_inb(p) ({ \ +#define SMC_inl(edev, r) (*((volatile dword *)SMCREG(edev, r))) +#define SMC_inw(edev, r) (*((volatile word *)SMCREG(edev, r))) +#define SMC_inb(edev, p) ({ \ unsigned int __p = p; \ - unsigned int __v = SMC_inw(__p & ~1); \ + unsigned int __v = SMC_inw(edev, __p & ~1); \ if (__p & 1) __v >>= 8; \ else __v &= 0xff; \ __v; }) -#define SMC_outl(d,r) (*((volatile dword *)SMCREG(r)) = d) -#define SMC_outw(d,r) (*((volatile word *)SMCREG(r)) = d) -#define SMC_outb(d,r) ({ word __d = (byte)(d); \ - word __w = SMC_inw((r)&~1); \ +#define SMC_outl(edev, d, r) (*((volatile dword *)SMCREG(edev, r)) = d) +#define SMC_outw(edev, d, r) (*((volatile word *)SMCREG(edev, r)) = d) +#define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \ + word __w = SMC_inw(edev, (r)&~1); \ __w &= ((r)&1) ? 0x00FF : 0xFF00; \ __w |= ((r)&1) ? __d<<8 : __d; \ - SMC_outw(__w,(r)&~1); \ + SMC_outw(edev, __w, (r)&~1); \ }) -#define SMC_outsl(r,b,l) ({ int __i; \ +#define SMC_outsl(edev, r, b, l) ({ int __i; \ dword *__b2; \ __b2 = (dword *) b; \ for (__i = 0; __i < l; __i++) { \ - SMC_outl( *(__b2 + __i), r ); \ + SMC_outl(edev, *(__b2 + __i),\ + r); \ } \ }) -#define SMC_outsw(r,b,l) ({ int __i; \ +#define SMC_outsw(edev, r, b, l) ({ int __i; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ - SMC_outw( *(__b2 + __i), r ); \ + SMC_outw(edev, *(__b2 + __i),\ + r); \ } \ }) -#define SMC_insl(r,b,l) ({ int __i ; \ +#define SMC_insl(edev, r, b, l) ({ int __i ; \ dword *__b2; \ __b2 = (dword *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inl(r); \ - SMC_inl(0); \ + *(__b2 + __i) = SMC_inl(edev,\ + r); \ + SMC_inl(edev, 0); \ }; \ }) -#define SMC_insw(r,b,l) ({ int __i ; \ +#define SMC_insw(edev, r, b, l) ({ int __i ; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inw(r); \ - SMC_inw(0); \ + *(__b2 + __i) = SMC_inw(edev,\ + r); \ + SMC_inw(edev, 0); \ }; \ }) -#define SMC_insb(r,b,l) ({ int __i ; \ +#define SMC_insb(edev, r, b, l) ({ int __i ; \ byte *__b2; \ __b2 = (byte *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inb(r); \ - SMC_inb(0); \ + *(__b2 + __i) = SMC_inb(edev,\ + r); \ + SMC_inb(edev, 0); \ }; \ }) @@ -155,40 +152,35 @@ typedef unsigned long int dword; * We have only 16 Bit PCMCIA access on Socket 0 */ -#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) -#define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF) +#define SMC_inw(edev, r) (*((volatile word *)((edev)->iobase+(r)))) +#define SMC_inb(edev, r) (((r)&1) ? SMC_inw(edev, (r)&~1)>>8 :\ + SMC_inw(edev, r)&0xFF) -#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) -#define SMC_outb(d,r) ({ word __d = (byte)(d); \ - word __w = SMC_inw((r)&~1); \ +#define SMC_outw(edev, d, r) (*((volatile word *)((edev)->iobase+(r))) = d) +#define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \ + word __w = SMC_inw(edev, (r)&~1); \ __w &= ((r)&1) ? 0x00FF : 0xFF00; \ __w |= ((r)&1) ? __d<<8 : __d; \ - SMC_outw(__w,(r)&~1); \ + SMC_outw(edev, __w, (r)&~1); \ }) -#if 0 -#define SMC_outsw(r,b,l) outsw(SMC_BASE_ADDRESS+(r), (b), (l)) -#else -#define SMC_outsw(r,b,l) ({ int __i; \ +#define SMC_outsw(edev, r, b, l) ({ int __i; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ - SMC_outw( *(__b2 + __i), r); \ + SMC_outw(edev, *(__b2 + __i),\ + r); \ } \ }) -#endif -#if 0 -#define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l)) -#else -#define SMC_insw(r,b,l) ({ int __i ; \ +#define SMC_insw(edev, r, b, l) ({ int __i ; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inw(r); \ - SMC_inw(0); \ + *(__b2 + __i) = SMC_inw(edev,\ + r); \ + SMC_inw(edev, 0); \ }; \ }) -#endif #endif @@ -608,25 +600,25 @@ typedef unsigned long int dword; /* select a register bank, 0 to 3 */ -#define SMC_SELECT_BANK(x) { SMC_outw( x, LAN91C96_BANK_SELECT ); } +#define SMC_SELECT_BANK(edev, x) { SMC_outw(edev, x, LAN91C96_BANK_SELECT); } /* this enables an interrupt in the interrupt mask register */ -#define SMC_ENABLE_INT(x) {\ +#define SMC_ENABLE_INT(edev, x) {\ unsigned char mask;\ - SMC_SELECT_BANK(2);\ - mask = SMC_inb( LAN91C96_INT_MASK );\ + SMC_SELECT_BANK(edev, 2);\ + mask = SMC_inb(edev, LAN91C96_INT_MASK);\ mask |= (x);\ - SMC_outb( mask, LAN91C96_INT_MASK ); \ + SMC_outb(edev, mask, LAN91C96_INT_MASK); \ } /* this disables an interrupt from the interrupt mask register */ -#define SMC_DISABLE_INT(x) {\ +#define SMC_DISABLE_INT(edev, x) {\ unsigned char mask;\ - SMC_SELECT_BANK(2);\ - mask = SMC_inb( LAN91C96_INT_MASK );\ + SMC_SELECT_BANK(edev, 2);\ + mask = SMC_inb(edev, LAN91C96_INT_MASK);\ mask &= ~(x);\ - SMC_outb( mask, LAN91C96_INT_MASK ); \ + SMC_outb(edev, mask, LAN91C96_INT_MASK); \ } /*---------------------------------------------------------------------- diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h index bb45241..895c749 100644 --- a/drivers/net/smc91111.h +++ b/drivers/net/smc91111.h @@ -81,10 +81,10 @@ struct smc91111_priv{ #ifdef CONFIG_PXA250 #ifdef CONFIG_XSENGINE -#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1)))) -#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r<<1)))) +#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+((r)<<1)))) +#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) #define SMC_inb(a,p) ({ \ - unsigned int __p = (unsigned int)((a)->iobase + (p<<1)); \ + unsigned int __p = (unsigned int)((a)->iobase + ((p)<<1)); \ unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \ if (__p & 2) __v >>= 8; \ else __v &= 0xff; \ @@ -99,7 +99,7 @@ struct smc91111_priv{ __v; }) #define SMC_inb(a,p) ({ \ unsigned int ___v = SMC_inw((a),(p) & ~1); \ - if (p & 1) ___v >>= 8; \ + if ((p) & 1) ___v >>= 8; \ else ___v &= 0xff; \ ___v; }) #else diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 613d902..d674ce2 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -37,7 +37,7 @@ void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) \ #define mdelay(n) udelay((n)*1000) -static void smx911x_handle_mac_address(struct eth_device *dev) +static void smc911x_handle_mac_address(struct eth_device *dev) { unsigned long addrh, addrl; uchar *m = dev->enetaddr; @@ -155,7 +155,7 @@ static int smc911x_init(struct eth_device *dev, bd_t * bd) /* Configure the PHY, initialize the link state */ smc911x_phy_configure(dev); - smx911x_handle_mac_address(dev); + smc911x_handle_mac_address(dev); /* Turn on Tx + Rx */ smc911x_enable(dev); @@ -243,7 +243,7 @@ int smc911x_initialize(u8 dev_num, int base_addr) dev = malloc(sizeof(*dev)); if (!dev) { free(dev); - return 0; + return -1; } memset(dev, 0, sizeof(*dev)); @@ -277,5 +277,5 @@ int smc911x_initialize(u8 dev_num, int base_addr) } eth_register(dev); - return 0; + return 1; } diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 3f74118..d8b6619 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -5,7 +5,7 @@ * terms of the GNU Public License, Version 2, incorporated * herein by reference. * - * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. + * Copyright 2004-2009 Freescale Semiconductor, Inc. * (C) Copyright 2003, Motorola, Inc. * author Andy Fleming * @@ -80,7 +80,7 @@ static struct tsec_info_struct tsec_info[] = { #ifdef CONFIG_MPC85XX_FEC { .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000), - .miiregs = (tsec_t *)(TSEC_BASE_ADDR), + .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), .devname = CONFIG_MPC85XX_FEC_NAME, .phyaddr = FEC_PHY_ADDR, .flags = FEC_FLAGS @@ -133,6 +133,7 @@ int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info) privlist[num_tsecs++] = priv; priv->regs = tsec_info->regs; priv->phyregs = tsec_info->miiregs; + priv->phyregs_sgmii = tsec_info->miiregs_sgmii; priv->phyaddr = tsec_info->phyaddr; priv->flags = tsec_info->flags; @@ -219,7 +220,7 @@ int tsec_init(struct eth_device *dev, bd_t * bd) } /* Writes the given phy's reg with value, using the specified MDIO regs */ -static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr, +static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr, uint reg, uint value) { int timeout = 1000000; @@ -242,7 +243,7 @@ static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr, * notvalid bit cleared), and the bus to cease activity (miimind * busy bit cleared), and then returns the value */ -uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum) +uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, uint phyid, uint regnum) { uint value; @@ -287,11 +288,11 @@ static void tsec_configure_serdes(struct tsec_private *priv) { /* Access TBI PHY registers at given TSEC register offset as opposed to the * register offset used for external PHY accesses */ - tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_ANA, + tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_ANA, TBIANA_SETTINGS); - tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_TBICON, + tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON, TBICON_CLK_SELECT); - tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_CR, + tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR, TBICR_SETTINGS); } @@ -303,12 +304,10 @@ static int init_phy(struct eth_device *dev) { struct tsec_private *priv = (struct tsec_private *)dev->priv; struct phy_info *curphy; - volatile tsec_t *phyregs = priv->phyregs; volatile tsec_t *regs = priv->regs; /* Assign a Physical address to the TBI */ regs->tbipa = CONFIG_SYS_TBIPA_VALUE; - phyregs->tbipa = CONFIG_SYS_TBIPA_VALUE; asm("sync"); /* Reset MII (due to new addresses) */ @@ -733,7 +732,7 @@ uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) { uint phyid; - volatile tsec_t *regbase = priv->phyregs; + volatile tsec_mdio_t *regbase = priv->phyregs; int timeout = 1000000; for (phyid = 0; phyid < 4; phyid++) { @@ -1766,7 +1765,7 @@ void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) { int i; uint result; - volatile tsec_t *phyregs = priv->phyregs; + volatile tsec_mdio_t *phyregs = priv->phyregs; phyregs->miimcfg = MIIMCFG_RESET; diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 8fbab68..fe57926 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -42,6 +42,7 @@ DECLARE_GLOBAL_DATA_PTR; #define FSL_PCI_PBFR 0x44 #define FSL_PCIE_CAP_ID 0x4c #define FSL_PCIE_CFG_RDY 0x4b0 +#define FSL_PROG_IF_AGENT 0x1 void pciauto_prescan_setup_bridge(struct pci_controller *hose, pci_dev_t dev, int sub_bus); @@ -85,6 +86,15 @@ static void set_inbound_window(volatile pit_t *pi, out_be32(&pi->piwar, flag | sz); } +int fsl_setup_hose(struct pci_controller *hose, unsigned long addr) +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr; + + pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); + + return fsl_is_pci_agent(hose); +} + static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, u64 out_lo, u8 pcie_cap, volatile pit_t *pi) @@ -412,28 +422,24 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) } } +int fsl_is_pci_agent(struct pci_controller *hose) +{ + u8 prog_if; + pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); + + pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if); + + return (prog_if == FSL_PROG_IF_AGENT); +} + int fsl_pci_init_port(struct fsl_pci_info *pci_info, - struct pci_controller *hose, int busno, int pcie_ep) + struct pci_controller *hose, int busno) { volatile ccsr_fsl_pci_t *pci; struct pci_region *r; pci = (ccsr_fsl_pci_t *) pci_info->regs; - if (pcie_ep) { - volatile pit_t *pi = &pci->pit[2]; - - pci_setup_indirect(hose, (u32)&pci->cfg_addr, - (u32)&pci->cfg_data); - out_be32(&pi->pitar, 0); - out_be32(&pi->piwbar, 0); - out_be32(&pi->piwar, PIWAR_EN | PIWAR_LOCAL | - PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_IWS_4K); - - fsl_pci_config_unlock(hose); - return 0; - } - /* on non-PCIe controllers we don't have pme_msg_det so this code * should do nothing since the read will return 0 */ @@ -464,6 +470,11 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); + if (fsl_is_pci_agent(hose)) { + fsl_pci_config_unlock(hose); + hose->last_busno = hose->first_busno; + } + printf(" PCIE%x on bus %02x - %02x\n", pci_info->pci_num, hose->first_busno, hose->last_busno); diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index ea7d899..772a49a 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -40,6 +40,7 @@ COBJS-$(CONFIG_RTC_DS1556) += ds1556.o COBJS-$(CONFIG_RTC_DS164x) += ds164x.o COBJS-$(CONFIG_RTC_DS174x) += ds174x.o COBJS-$(CONFIG_RTC_DS3231) += ds3231.o +COBJS-$(CONFIG_RTC_FTRTC010) += ftrtc010.o COBJS-$(CONFIG_RTC_ISL1208) += isl1208.o COBJS-$(CONFIG_RTC_M41T11) += m41t11.o COBJS-$(CONFIG_RTC_M41T60) += m41t60.o diff --git a/drivers/rtc/ftrtc010.c b/drivers/rtc/ftrtc010.c new file mode 100644 index 0000000..7738a7a --- /dev/null +++ b/drivers/rtc/ftrtc010.c @@ -0,0 +1,124 @@ +/* + * Faraday FTRTC010 Real Time Clock + * + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert@faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <rtc.h> +#include <asm/io.h> + +struct ftrtc010 { + unsigned int sec; /* 0x00 */ + unsigned int min; /* 0x04 */ + unsigned int hour; /* 0x08 */ + unsigned int day; /* 0x0c */ + unsigned int alarm_sec; /* 0x10 */ + unsigned int alarm_min; /* 0x14 */ + unsigned int alarm_hour; /* 0x18 */ + unsigned int record; /* 0x1c */ + unsigned int cr; /* 0x20 */ +}; + +/* + * RTC Control Register + */ +#define FTRTC010_CR_ENABLE (1 << 0) +#define FTRTC010_CR_INTERRUPT_SEC (1 << 1) /* per second irq */ +#define FTRTC010_CR_INTERRUPT_MIN (1 << 2) /* per minute irq */ +#define FTRTC010_CR_INTERRUPT_HR (1 << 3) /* per hour irq */ +#define FTRTC010_CR_INTERRUPT_DAY (1 << 4) /* per day irq */ + +static struct ftrtc010 *rtc = (struct ftrtc010 *)CONFIG_FTRTC010_BASE; + +static void ftrtc010_enable(void) +{ + writel(FTRTC010_CR_ENABLE, &rtc->cr); +} + +/* + * return current time in seconds + */ +static unsigned long ftrtc010_time(void) +{ + unsigned long day; + unsigned long hour; + unsigned long minute; + unsigned long second; + unsigned long second2; + + do { + second = readl(&rtc->sec); + day = readl(&rtc->day); + hour = readl(&rtc->hour); + minute = readl(&rtc->min); + second2 = readl(&rtc->sec); + } while (second != second2); + + return day * 24 * 60 * 60 + hour * 60 * 60 + minute * 60 + second; +} + +/* + * Get the current time from the RTC + */ + +int rtc_get(struct rtc_time *tmp) +{ + unsigned long now; + + debug("%s(): record register: %x\n", + __func__, readl(&rtc->record)); + + now = ftrtc010_time() + readl(&rtc->record); + + to_tm(now, tmp); + + return 0; +} + +/* + * Set the RTC + */ +int rtc_set(struct rtc_time *tmp) +{ + unsigned long new; + unsigned long now; + + debug("%s(): DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + __func__, + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + new = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_hour, + tmp->tm_min, tmp->tm_sec); + + now = ftrtc010_time(); + + debug("%s(): write %lx to record register\n", __func__, new - now); + + writel(new - now, &rtc->record); + + return 0; +} + +void rtc_reset(void) +{ + debug("%s()\n", __func__); + ftrtc010_enable(); +} diff --git a/drivers/rtc/m41t11.c b/drivers/rtc/m41t11.c index e0c27e1..bb13487 100644 --- a/drivers/rtc/m41t11.c +++ b/drivers/rtc/m41t11.c @@ -181,18 +181,4 @@ void rtc_reset (void) val = val & 0x3F;/*turn off freq test keep calibration*/ i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_CONTROL_ADDR, 1, &val, 1); } - -int rtc_store(int addr, unsigned char* data, int size) -{ - /*don't let things wrap onto the time on a write*/ - if( (addr+size) >= M41T11_STORAGE_SZ ) - return 1; - return i2c_write( CONFIG_SYS_I2C_RTC_ADDR, REG_CNT+addr, 1, data, size ); -} - -int rtc_recall(int addr, unsigned char* data, int size) -{ - return i2c_read( CONFIG_SYS_I2C_RTC_ADDR, REG_CNT+addr, 1, data, size ); -} - #endif diff --git a/drivers/rtc/m41t94.c b/drivers/rtc/m41t94.c index 02b41d9..5b665bb 100644 --- a/drivers/rtc/m41t94.c +++ b/drivers/rtc/m41t94.c @@ -120,5 +120,4 @@ void rtc_reset(void) * Could not be tested as the reset pin is not wired on * the sbc35-ag20 board */ - return 0; } diff --git a/drivers/rtc/mc13783-rtc.c b/drivers/rtc/mc13783-rtc.c index 05db2f1..416f50d 100644 --- a/drivers/rtc/mc13783-rtc.c +++ b/drivers/rtc/mc13783-rtc.c @@ -109,7 +109,7 @@ int rtc_set(struct rtc_time *rtc) spi_release_bus(slave); - return -1; + return 0; } void rtc_reset(void) diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h index f746d63..6b6c4a1 100644 --- a/drivers/serial/usbtty.h +++ b/drivers/serial/usbtty.h @@ -29,6 +29,8 @@ #include <usb/mpc8xx_udc.h> #elif defined(CONFIG_OMAP1510) #include <usb/omap1510_udc.h> +#elif defined(CONFIG_MUSB_UDC) +#include <usb/musb_udc.h> #elif defined(CONFIG_PXA27X) #include <usb/pxa27x_udc.h> #endif diff --git a/drivers/spi/atmel_dataflash_spi.c b/drivers/spi/atmel_dataflash_spi.c index 614965c..3a648e6 100644 --- a/drivers/spi/atmel_dataflash_spi.c +++ b/drivers/spi/atmel_dataflash_spi.c @@ -30,7 +30,8 @@ #include <dataflash.h> #define AT91_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */ -#define AT91_SPI_PCS1_DATAFLASH_CARD 0xD /* Chip Select 0: NPCS0%1101 */ +#define AT91_SPI_PCS1_DATAFLASH_CARD 0xD /* Chip Select 1: NPCS1%1101 */ +#define AT91_SPI_PCS2_DATAFLASH_CARD 0xB /* Chip Select 2: NPCS2%1011 */ #define AT91_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */ void AT91F_SpiInit(void) @@ -57,7 +58,14 @@ void AT91F_SpiInit(void) ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), AT91_BASE_SPI + AT91_SPI_CSR(1)); #endif - +#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2 + /* Configure CS2 */ + writel(AT91_SPI_NCPHA | + (AT91_SPI_DLYBS & DATAFLASH_TCSS) | + (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | + ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), + AT91_BASE_SPI + AT91_SPI_CSR(2)); +#endif #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 /* Configure CS3 */ writel(AT91_SPI_NCPHA | @@ -99,6 +107,12 @@ void AT91F_SpiEnable(int cs) writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS), AT91_BASE_SPI + AT91_SPI_MR); break; + case 2: /* Configure SPI CS2 for Serial DataFlash AT45DBxx */ + mode = readl(AT91_BASE_SPI + AT91_SPI_MR); + mode &= 0xFFF0FFFF; + writel(mode | ((AT91_SPI_PCS2_DATAFLASH_CARD<<16) & AT91_SPI_PCS), + AT91_BASE_SPI + AT91_SPI_MR); + break; case 3: mode = readl(AT91_BASE_SPI + AT91_SPI_MR); mode &= 0xFFF0FFFF; diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 940d4a8..255679a 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -36,6 +36,7 @@ COBJS-$(CONFIG_USB_SL811HS) += sl811-hcd.o # echi COBJS-$(CONFIG_USB_EHCI) += ehci-hcd.o COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o +COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 324c308..9ebeb4f 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -96,7 +96,7 @@ static struct descriptor { * UE_DIR_IN | EHCI_INTR_ENDPT */ 3, /* bmAttributes: UE_INTERRUPT */ - 8, 0, /* wMaxPacketSize */ + 8, /* wMaxPacketSize */ 255 /* bInterval */ }, }; @@ -708,6 +708,9 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, * root */ wait_ms(50); + /* terminate the reset */ + ehci_writel(status_reg, reg & ~EHCI_PS_PR); + wait_ms(2); portreset |= 1 << le16_to_cpu(req->index); } break; diff --git a/drivers/usb/host/ehci-ppc4xx.c b/drivers/usb/host/ehci-ppc4xx.c new file mode 100644 index 0000000..946a0a0 --- /dev/null +++ b/drivers/usb/host/ehci-ppc4xx.c @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2010, Chris Zhang <chris@seamicro.com> + * + * Author: Chris Zhang <chris@seamicro.com> + * This code is based on ehci freescale driver + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <usb.h> + +#include "ehci.h" +#include "ehci-core.h" + +/* + * Create the appropriate control structures to manage + * a new EHCI host controller. + */ +int ehci_hcd_init(void) +{ + hccr = (struct ehci_hccr *)(CONFIG_SYS_PPC4XX_USB_ADDR); + hcor = (struct ehci_hcor *)((uint32_t) hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + usb_dev_init(); + return 0; +} + +/* + * Destroy the appropriate control structures corresponding + * the the EHCI host controller. + */ +int ehci_hcd_stop(void) +{ + return 0; +} diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile index 09e0a5f..397f5fe 100644 --- a/drivers/usb/musb/Makefile +++ b/drivers/usb/musb/Makefile @@ -26,7 +26,11 @@ include $(TOPDIR)/config.mk LIB := $(obj)libusb_musb.a COBJS-$(CONFIG_MUSB_HCD) += musb_hcd.o musb_core.o +COBJS-$(CONFIG_MUSB_UDC) += musb_udc.o musb_core.o +COBJS-$(CONFIG_USB_BLACKFIN) += blackfin_usb.o COBJS-$(CONFIG_USB_DAVINCI) += davinci.o +COBJS-$(CONFIG_USB_OMAP3) += omap3.o +COBJS-$(CONFIG_USB_DA8XX) += da8xx.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/usb/musb/blackfin_usb.c b/drivers/usb/musb/blackfin_usb.c new file mode 100644 index 0000000..38aceb2 --- /dev/null +++ b/drivers/usb/musb/blackfin_usb.c @@ -0,0 +1,143 @@ +/* + * Blackfin MUSB HCD (Host Controller Driver) for u-boot + * + * Copyright (c) 2008-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> + +#include <usb.h> + +#include <asm/blackfin.h> +#include <asm/mach-common/bits/usb.h> + +#include "musb_core.h" + +/* MUSB platform configuration */ +struct musb_config musb_cfg = { + .regs = (struct musb_regs *)USB_FADDR, + .timeout = 0x3FFFFFF, + .musb_speed = 0, +}; + +/* + * This function read or write data to endpoint fifo + * Blackfin use DMA polling method to avoid buffer alignment issues + * + * ep - Endpoint number + * length - Number of bytes to write to FIFO + * fifo_data - Pointer to data buffer to be read/write + * is_write - Flag for read or write + */ +void rw_fifo(u8 ep, u32 length, void *fifo_data, int is_write) +{ + struct bfin_musb_dma_regs *regs; + u32 val = (u32)fifo_data; + + blackfin_dcache_flush_invalidate_range(fifo_data, fifo_data + length); + + regs = (void *)USB_DMA_INTERRUPT; + regs += ep; + + /* Setup DMA address register */ + bfin_write16(®s->addr_low, val); + SSYNC(); + + bfin_write16(®s->addr_high, val >> 16); + SSYNC(); + + /* Setup DMA count register */ + bfin_write16(®s->count_low, length); + bfin_write16(®s->count_high, 0); + SSYNC(); + + /* Enable the DMA */ + val = (ep << 4) | DMA_ENA | INT_ENA; + if (is_write) + val |= DIRECTION; + bfin_write16(®s->control, val); + SSYNC(); + + /* Wait for compelete */ + while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << ep))) + continue; + + /* acknowledge dma interrupt */ + bfin_write_USB_DMA_INTERRUPT(1 << ep); + SSYNC(); + + /* Reset DMA */ + bfin_write16(®s->control, 0); + SSYNC(); +} + +void write_fifo(u8 ep, u32 length, void *fifo_data) +{ + rw_fifo(ep, length, fifo_data, 1); +} + +void read_fifo(u8 ep, u32 length, void *fifo_data) +{ + rw_fifo(ep, length, fifo_data, 0); +} + + +/* + * CPU and board-specific MUSB initializations. Aliased function + * signals caller to move on. + */ +static void __def_musb_init(void) +{ +} +void board_musb_init(void) __attribute__((weak, alias("__def_musb_init"))); + +int musb_platform_init(void) +{ + /* board specific initialization */ + board_musb_init(); + + if (ANOMALY_05000346) { + bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value); + SSYNC(); + } + + if (ANOMALY_05000347) { + bfin_write_USB_APHY_CNTRL(0x0); + SSYNC(); + } + + /* Configure PLL oscillator register */ + bfin_write_USB_PLLOSC_CTRL(0x30a8); + SSYNC(); + + bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1); + SSYNC(); + + bfin_write_USB_EP_NI0_RXMAXP(64); + SSYNC(); + + bfin_write_USB_EP_NI0_TXMAXP(64); + SSYNC(); + + /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/ + bfin_write_USB_GLOBINTR(0x7); + SSYNC(); + + bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA | + EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA | + EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA | + EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA | + EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA); + SSYNC(); + + return 0; +} + +/* + * This function performs Blackfin platform specific deinitialization for usb. +*/ +void musb_platform_deinit(void) +{ +} diff --git a/drivers/usb/musb/blackfin_usb.h b/drivers/usb/musb/blackfin_usb.h new file mode 100644 index 0000000..ab26ca2 --- /dev/null +++ b/drivers/usb/musb/blackfin_usb.h @@ -0,0 +1,99 @@ +/* + * Blackfin MUSB HCD (Host Controller Driver) for u-boot + * + * Copyright (c) 2008-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BLACKFIN_USB_H__ +#define __BLACKFIN_USB_H__ + +#include <linux/types.h> + +/* Every register is 32bit aligned, but only 16bits in size */ +#define ureg(name) u16 name; u16 __pad_##name; + +#define musb_regs musb_regs +struct musb_regs { + /* common registers */ + ureg(faddr) + ureg(power) + ureg(intrtx) + ureg(intrrx) + ureg(intrtxe) + ureg(intrrxe) + ureg(intrusb) + ureg(intrusbe) + ureg(frame) + ureg(index) + ureg(testmode) + ureg(globintr) + ureg(global_ctl) + u32 reserved0[3]; + /* indexed registers */ + ureg(txmaxp) + ureg(txcsr) + ureg(rxmaxp) + ureg(rxcsr) + ureg(rxcount) + ureg(txtype) + ureg(txinterval) + ureg(rxtype) + ureg(rxinterval) + u32 reserved1; + ureg(txcount) + u32 reserved2[5]; + /* fifo */ + u16 fifox[32]; + /* OTG, dynamic FIFO, version & vendor registers */ + u32 reserved3[16]; + ureg(devctl) + ureg(vbus_irq) + ureg(vbus_mask) + u32 reserved4[15]; + ureg(linkinfo) + ureg(vplen) + ureg(hseof1) + ureg(fseof1) + ureg(lseof1) + u32 reserved5[41]; + /* target address registers */ + struct musb_tar_regs { + ureg(txmaxp) + ureg(txcsr) + ureg(rxmaxp) + ureg(rxcsr) + ureg(rxcount) + ureg(txtype) + ureg(txinternal) + ureg(rxtype) + ureg(rxinternal) + u32 reserved6; + ureg(txcount) + u32 reserved7[5]; + } tar[8]; +} __attribute__((packed)); + +struct bfin_musb_dma_regs { + ureg(interrupt); + ureg(control); + ureg(addr_low); + ureg(addr_high); + ureg(count_low); + ureg(count_high); + ureg(pad); +}; + +#undef ureg + +/* EP5-EP7 are the only ones with 1024 byte FIFOs which BULK really needs */ +#define MUSB_BULK_EP 5 + +/* Blackfin FIFO's are static */ +#define MUSB_NO_DYNAMIC_FIFO + +/* No HUB support :( */ +#define MUSB_NO_MULTIPOINT + +#endif diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c new file mode 100644 index 0000000..40bfe44 --- /dev/null +++ b/drivers/usb/musb/da8xx.c @@ -0,0 +1,139 @@ +/* + * da8xx.c - TI's DA8xx platform specific usb wrapper functions. + * + * Author: Ajay Kumar Gupta <ajay.gupta@ti.com> + * + * Based on drivers/usb/musb/davinci.c + * + * Copyright (C) 2009 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include <common.h> + +#include "da8xx.h" + +/* MUSB platform configuration */ +struct musb_config musb_cfg = { + (struct musb_regs *)DA8XX_USB_OTG_CORE_BASE, + DA8XX_USB_OTG_TIMEOUT, + 0 +}; + +/* + * This function enables VBUS by driving the GPIO Bank4 Pin 15 high. + */ +static void enable_vbus(void) +{ + u32 value; + + /* configure GPIO bank4 pin 15 in output direction */ + value = readl(&davinci_gpio_bank45->dir); + writel((value & (~DA8XX_USB_VBUS_GPIO)), &davinci_gpio_bank45->dir); + + /* set GPIO bank4 pin 15 high to drive VBUS */ + value = readl(&davinci_gpio_bank45->set_data); + writel((value | DA8XX_USB_VBUS_GPIO), &davinci_gpio_bank45->set_data); +} + +/* + * Enable the usb0 phy. This initialization procedure is explained in + * the DA8xx USB user guide document. + */ +static u8 phy_on(void) +{ + u32 timeout; + u32 cfgchip2; + + cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2); + + cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN | + CFGCHIP2_OTGMODE | CFGCHIP2_REFFREQ); + cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN | CFGCHIP2_PHY_PLLON | + CFGCHIP2_REFFREQ_24MHZ; + + writel(cfgchip2, &davinci_syscfg_regs->cfgchip2); + + /* wait until the usb phy pll locks */ + timeout = musb_cfg.timeout; + while (timeout--) + if (readl(&davinci_syscfg_regs->cfgchip2) & CFGCHIP2_PHYCLKGD) + return 1; + + /* USB phy was not turned on */ + return 0; +} + +/* + * Disable the usb phy + */ +static void phy_off(void) +{ + u32 cfgchip2; + + /* + * Power down the on-chip PHY. + */ + cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2); + cfgchip2 &= ~CFGCHIP2_PHY_PLLON; + cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN; + writel(cfgchip2, &davinci_syscfg_regs->cfgchip2); +} + +/* + * This function performs DA8xx platform specific initialization for usb0. + */ +int musb_platform_init(void) +{ + u32 revision; + + /* enable psc for usb2.0 */ + lpsc_on(33); + + /* enable usb vbus */ + enable_vbus(); + + /* reset the controller */ + writel(0x1, &da8xx_usb_regs->control); + udelay(5000); + + /* start the on-chip usb phy and its pll */ + if (phy_on() == 0) + return -1; + + /* Returns zero if e.g. not clocked */ + revision = readl(&da8xx_usb_regs->revision); + if (revision == 0) + return -1; + + /* Disable all interrupts */ + writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK | + DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_set); + return 0; +} + +/* + * This function performs DA8xx platform specific deinitialization for usb0. + */ +void musb_platform_deinit(void) +{ + /* Turn of the phy */ + phy_off(); + + /* flush any interrupts */ + writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK | + DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_clr); + writel(0, &da8xx_usb_regs->eoi); +} diff --git a/drivers/usb/musb/da8xx.h b/drivers/usb/musb/da8xx.h new file mode 100644 index 0000000..93234f0 --- /dev/null +++ b/drivers/usb/musb/da8xx.h @@ -0,0 +1,103 @@ +/* + * da8xx.h -- TI's DA8xx platform specific usb wrapper definitions. + * + * Author: Ajay Kumar Gupta <ajay.gupta@ti.com> + * + * Based on drivers/usb/musb/davinci.h + * + * Copyright (C) 2009 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __DA8XX_MUSB_H__ +#define __DA8XX_MUSB_H__ + +#include <asm/arch/hardware.h> +#include <asm/arch/gpio_defs.h> +#include "musb_core.h" + +/* Base address of da8xx usb0 wrapper */ +#define DA8XX_USB_OTG_BASE 0x01E00000 + +/* Base address of da8xx musb core */ +#define DA8XX_USB_OTG_CORE_BASE (DA8XX_USB_OTG_BASE + 0x400) + +/* Timeout for DA8xx usb module */ +#define DA8XX_USB_OTG_TIMEOUT 0x3FFFFFF + +/* + * DA8xx platform USB wrapper register overlay. + */ +struct da8xx_usb_regs { + dv_reg revision; + dv_reg control; + dv_reg status; + dv_reg emulation; + dv_reg mode; + dv_reg autoreq; + dv_reg srpfixtime; + dv_reg teardown; + dv_reg intsrc; + dv_reg intsrc_set; + dv_reg intsrc_clr; + dv_reg intmsk; + dv_reg intmsk_set; + dv_reg intmsk_clr; + dv_reg intsrcmsk; + dv_reg eoi; + dv_reg intvector; + dv_reg grndis_size[4]; +}; + +#define da8xx_usb_regs ((struct da8xx_usb_regs *)DA8XX_USB_OTG_BASE) + +/* DA8XX interrupt bits definitions */ +#define DA8XX_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */ +#define DA8XX_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */ +#define DA8XX_USB_TXINT_SHIFT 0 +#define DA8XX_USB_RXINT_SHIFT 8 + +#define DA8XX_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */ +#define DA8XX_USB_TXINT_MASK \ + (DA8XX_USB_TX_ENDPTS_MASK << DA8XX_USB_TXINT_SHIFT) +#define DA8XX_USB_RXINT_MASK \ + (DA8XX_USB_RX_ENDPTS_MASK << DA8XX_USB_RXINT_SHIFT) + +/* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */ +#define CFGCHIP2_PHYCLKGD (1 << 17) +#define CFGCHIP2_VBUSSENSE (1 << 16) +#define CFGCHIP2_RESET (1 << 15) +#define CFGCHIP2_OTGMODE (3 << 13) +#define CFGCHIP2_NO_OVERRIDE (0 << 13) +#define CFGCHIP2_FORCE_HOST (1 << 13) +#define CFGCHIP2_FORCE_DEVICE (2 << 13) +#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13) +#define CFGCHIP2_USB1PHYCLKMUX (1 << 12) +#define CFGCHIP2_USB2PHYCLKMUX (1 << 11) +#define CFGCHIP2_PHYPWRDN (1 << 10) +#define CFGCHIP2_OTGPWRDN (1 << 9) +#define CFGCHIP2_DATPOL (1 << 8) +#define CFGCHIP2_USB1SUSPENDM (1 << 7) +#define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */ +#define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */ +#define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */ +#define CFGCHIP2_REFFREQ (0xf << 0) +#define CFGCHIP2_REFFREQ_12MHZ (1 << 0) +#define CFGCHIP2_REFFREQ_24MHZ (2 << 0) +#define CFGCHIP2_REFFREQ_48MHZ (3 << 0) + +#define DA8XX_USB_VBUS_GPIO (1 << 15) +#endif /* __DA8XX_MUSB_H__ */ + diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c index ec57fc8..7766069 100644 --- a/drivers/usb/musb/musb_core.c +++ b/drivers/usb/musb/musb_core.c @@ -32,7 +32,9 @@ struct musb_regs *musbr; */ void musb_start(void) { +#if defined(CONFIG_MUSB_HCD) u8 devctl; +#endif /* disable all interrupts */ writew(0, &musbr->intrtxe); @@ -48,6 +50,16 @@ void musb_start(void) #endif } +#ifdef MUSB_NO_DYNAMIC_FIFO +# define config_fifo(dir, idx, addr) +#else +# define config_fifo(dir, idx, addr) \ + do { \ + writeb(idx, &musbr->dir##fifosz); \ + writew(fifoaddr >> 3, &musbr->dir##fifoadd); \ + } while (0) +#endif + /* * This function configures the endpoint configuration. The musb hcd or musb * device implementation can use this function to configure the endpoints @@ -72,11 +84,11 @@ void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt) writeb(epinfo->epnum, &musbr->index); if (epinfo->epdir) { /* Configure fifo size and fifo base address */ - writeb(idx, &musbr->txfifosz); - writew(fifoaddr >> 3, &musbr->txfifoadd); + config_fifo(tx, idx, fifoaddr); + + csr = readw(&musbr->txcsr); #if defined(CONFIG_MUSB_HCD) /* clear the data toggle bit */ - csr = readw(&musbr->txcsr); writew(csr | MUSB_TXCSR_CLRDATATOG, &musbr->txcsr); #endif /* Flush fifo if required */ @@ -85,11 +97,11 @@ void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt) &musbr->txcsr); } else { /* Configure fifo size and fifo base address */ - writeb(idx, &musbr->rxfifosz); - writew(fifoaddr >> 3, &musbr->rxfifoadd); + config_fifo(rx, idx, fifoaddr); + + csr = readw(&musbr->rxcsr); #if defined(CONFIG_MUSB_HCD) /* clear the data toggle bit */ - csr = readw(&musbr->rxcsr); writew(csr | MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr); #endif /* Flush fifo if required */ @@ -109,6 +121,7 @@ void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt) * length - number of bytes to write to FIFO * fifo_data - Pointer to data buffer that contains the data to write */ +__attribute__((weak)) void write_fifo(u8 ep, u32 length, void *fifo_data) { u8 *data = (u8 *)fifo_data; @@ -128,6 +141,7 @@ void write_fifo(u8 ep, u32 length, void *fifo_data) * length - number of bytes to read from FIFO * fifo_data - pointer to data buffer into which data is read */ +__attribute__((weak)) void read_fifo(u8 ep, u32 length, void *fifo_data) { u8 *data = (u8 *)fifo_data; diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h index f9da3f0..f0f0301 100644 --- a/drivers/usb/musb/musb_core.h +++ b/drivers/usb/musb/musb_core.h @@ -38,9 +38,44 @@ #include <usb_defs.h> #include <asm/io.h> +#ifdef CONFIG_USB_BLACKFIN +# include "blackfin_usb.h" +#endif + #define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */ +/* EP0 */ +struct musb_ep0_regs { + u16 reserved4; + u16 csr0; + u16 reserved5; + u16 reserved6; + u16 count0; + u8 host_type0; + u8 host_naklimit0; + u8 reserved7; + u8 reserved8; + u8 reserved9; + u8 configdata; +}; + +/* EP 1-15 */ +struct musb_epN_regs { + u16 txmaxp; + u16 txcsr; + u16 rxmaxp; + u16 rxcsr; + u16 rxcount; + u8 txtype; + u8 txinterval; + u8 rxtype; + u8 rxinterval; + u8 reserved0; + u8 fifosize; +}; + /* Mentor USB core register overlay structure */ +#ifndef musb_regs struct musb_regs { /* common registers */ u8 faddr; @@ -97,7 +132,18 @@ struct musb_regs { u8 rxhubaddr; u8 rxhubport; } tar[16]; -} __attribute__((aligned(32))); + /* + * end point registers + * ep0 elements are valid when array index is 0 + * otherwise epN is valid + */ + union musb_ep_regs { + struct musb_ep0_regs ep0; + struct musb_epN_regs epN; + } ep[16]; + +} __attribute__((packed, aligned(32))); +#endif /* * MUSB Register bits @@ -307,4 +353,14 @@ extern void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt); extern void write_fifo(u8 ep, u32 length, void *fifo_data); extern void read_fifo(u8 ep, u32 length, void *fifo_data); +#if defined(CONFIG_USB_BLACKFIN) +/* Every USB register is accessed as a 16-bit even if the value itself + * is only 8-bits in size. Fun stuff. + */ +# undef readb +# define readb(addr) (u8)bfin_read16(addr) +# undef writeb +# define writeb(b, addr) bfin_write16(addr, b) +#endif + #endif /* __MUSB_HDRC_DEFS_H__ */ diff --git a/drivers/usb/musb/musb_debug.h b/drivers/usb/musb/musb_debug.h new file mode 100644 index 0000000..62380ff --- /dev/null +++ b/drivers/usb/musb/musb_debug.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix <Tom.Rix@windriver.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Define MUSB_DEBUG before including this file to get debug macros */ +#ifdef MUSB_DEBUG + +#define MUSB_FLAGS_PRINT(v, x, y) \ + if (((v) & MUSB_##x##_##y)) \ + serial_printf("\t\t"#y"\n") + +static inline void musb_print_pwr(u8 b) +{ + serial_printf("\tpower 0x%2.2x\n", b); + MUSB_FLAGS_PRINT(b, POWER, ISOUPDATE); + MUSB_FLAGS_PRINT(b, POWER, SOFTCONN); + MUSB_FLAGS_PRINT(b, POWER, HSENAB); + MUSB_FLAGS_PRINT(b, POWER, HSMODE); + MUSB_FLAGS_PRINT(b, POWER, RESET); + MUSB_FLAGS_PRINT(b, POWER, RESUME); + MUSB_FLAGS_PRINT(b, POWER, SUSPENDM); + MUSB_FLAGS_PRINT(b, POWER, ENSUSPEND); +} + +static inline void musb_print_csr0(u16 w) +{ + serial_printf("\tcsr0 0x%4.4x\n", w); + MUSB_FLAGS_PRINT(w, CSR0, FLUSHFIFO); + MUSB_FLAGS_PRINT(w, CSR0_P, SVDSETUPEND); + MUSB_FLAGS_PRINT(w, CSR0_P, SVDRXPKTRDY); + MUSB_FLAGS_PRINT(w, CSR0_P, SENDSTALL); + MUSB_FLAGS_PRINT(w, CSR0_P, SETUPEND); + MUSB_FLAGS_PRINT(w, CSR0_P, DATAEND); + MUSB_FLAGS_PRINT(w, CSR0_P, SENTSTALL); + MUSB_FLAGS_PRINT(w, CSR0, TXPKTRDY); + MUSB_FLAGS_PRINT(w, CSR0, RXPKTRDY); +} + +static inline void musb_print_intrusb(u8 b) +{ + serial_printf("\tintrusb 0x%2.2x\n", b); + MUSB_FLAGS_PRINT(b, INTR, VBUSERROR); + MUSB_FLAGS_PRINT(b, INTR, SESSREQ); + MUSB_FLAGS_PRINT(b, INTR, DISCONNECT); + MUSB_FLAGS_PRINT(b, INTR, CONNECT); + MUSB_FLAGS_PRINT(b, INTR, SOF); + MUSB_FLAGS_PRINT(b, INTR, RESUME); + MUSB_FLAGS_PRINT(b, INTR, SUSPEND); + + if (b & MUSB_INTR_BABBLE) + serial_printf("\t\tMUSB_INTR_RESET or MUSB_INTR_BABBLE\n"); + +} + +static inline void musb_print_intrtx(u16 w) +{ + serial_printf("\tintrtx 0x%4.4x\n", w); +} + +static inline void musb_print_intrrx(u16 w) +{ + serial_printf("\tintrx 0x%4.4x\n", w); +} + +static inline void musb_print_devctl(u8 b) +{ + serial_printf("\tdevctl 0x%2.2x\n", b); + if (b & MUSB_DEVCTL_BDEVICE) + serial_printf("\t\tB device\n"); + else + serial_printf("\t\tA device\n"); + if (b & MUSB_DEVCTL_FSDEV) + serial_printf("\t\tFast Device -(host mode)\n"); + if (b & MUSB_DEVCTL_LSDEV) + serial_printf("\t\tSlow Device -(host mode)\n"); + if (b & MUSB_DEVCTL_HM) + serial_printf("\t\tHost mode\n"); + else + serial_printf("\t\tPeripherial mode\n"); + if (b & MUSB_DEVCTL_HR) + serial_printf("\t\tHost request started(B device)\n"); + else + serial_printf("\t\tHost request finished(B device)\n"); + if (b & MUSB_DEVCTL_BDEVICE) { + if (b & MUSB_DEVCTL_SESSION) + serial_printf("\t\tStart of session(B device)\n"); + else + serial_printf("\t\tEnd of session(B device)\n"); + } else { + if (b & MUSB_DEVCTL_SESSION) + serial_printf("\t\tStart of session(A device)\n"); + else + serial_printf("\t\tEnd of session(A device)\n"); + } +} + +static inline void musb_print_config(u8 b) +{ + serial_printf("\tconfig 0x%2.2x\n", b); + if (b & MUSB_CONFIGDATA_MPRXE) + serial_printf("\t\tAuto combine rx bulk packets\n"); + if (b & MUSB_CONFIGDATA_MPTXE) + serial_printf("\t\tAuto split tx bulk packets\n"); + if (b & MUSB_CONFIGDATA_BIGENDIAN) + serial_printf("\t\tBig Endian ordering\n"); + else + serial_printf("\t\tLittle Endian ordering\n"); + if (b & MUSB_CONFIGDATA_HBRXE) + serial_printf("\t\tHigh speed rx iso endpoint\n"); + if (b & MUSB_CONFIGDATA_HBTXE) + serial_printf("\t\tHigh speed tx iso endpoint\n"); + if (b & MUSB_CONFIGDATA_DYNFIFO) + serial_printf("\t\tDynamic fifo sizing\n"); + if (b & MUSB_CONFIGDATA_SOFTCONE) + serial_printf("\t\tSoft Connect\n"); + if (b & MUSB_CONFIGDATA_UTMIDW) + serial_printf("\t\t16 bit data width\n"); + else + serial_printf("\t\t8 bit data width\n"); +} + +static inline void musb_print_rxmaxp(u16 w) +{ + serial_printf("\trxmaxp 0x%4.4x\n", w); +} + +static inline void musb_print_rxcsr(u16 w) +{ + serial_printf("\trxcsr 0x%4.4x\n", w); + MUSB_FLAGS_PRINT(w, RXCSR, AUTOCLEAR); + MUSB_FLAGS_PRINT(w, RXCSR, DMAENAB); + MUSB_FLAGS_PRINT(w, RXCSR, DISNYET); + MUSB_FLAGS_PRINT(w, RXCSR, PID_ERR); + MUSB_FLAGS_PRINT(w, RXCSR, DMAMODE); + MUSB_FLAGS_PRINT(w, RXCSR, CLRDATATOG); + MUSB_FLAGS_PRINT(w, RXCSR, FLUSHFIFO); + MUSB_FLAGS_PRINT(w, RXCSR, DATAERROR); + MUSB_FLAGS_PRINT(w, RXCSR, FIFOFULL); + MUSB_FLAGS_PRINT(w, RXCSR, RXPKTRDY); + MUSB_FLAGS_PRINT(w, RXCSR_P, SENTSTALL); + MUSB_FLAGS_PRINT(w, RXCSR_P, SENDSTALL); + MUSB_FLAGS_PRINT(w, RXCSR_P, OVERRUN); + + if (w & MUSB_RXCSR_P_ISO) + serial_printf("\t\tiso mode\n"); + else + serial_printf("\t\tbulk mode\n"); + +} + +static inline void musb_print_txmaxp(u16 w) +{ + serial_printf("\ttxmaxp 0x%4.4x\n", w); +} + +static inline void musb_print_txcsr(u16 w) +{ + serial_printf("\ttxcsr 0x%4.4x\n", w); + MUSB_FLAGS_PRINT(w, TXCSR, TXPKTRDY); + MUSB_FLAGS_PRINT(w, TXCSR, FIFONOTEMPTY); + MUSB_FLAGS_PRINT(w, TXCSR, FLUSHFIFO); + MUSB_FLAGS_PRINT(w, TXCSR, CLRDATATOG); + MUSB_FLAGS_PRINT(w, TXCSR_P, UNDERRUN); + MUSB_FLAGS_PRINT(w, TXCSR_P, SENTSTALL); + MUSB_FLAGS_PRINT(w, TXCSR_P, SENDSTALL); + + if (w & MUSB_TXCSR_MODE) + serial_printf("\t\tTX mode\n"); + else + serial_printf("\t\tRX mode\n"); +} + +#else + +/* stubs */ + +#define musb_print_pwr(b) +#define musb_print_csr0(w) +#define musb_print_intrusb(b) +#define musb_print_intrtx(w) +#define musb_print_intrrx(w) +#define musb_print_devctl(b) +#define musb_print_config(b) +#define musb_print_rxmaxp(w) +#define musb_print_rxcsr(w) +#define musb_print_txmaxp(w) +#define musb_print_txcsr(w) + +#endif /* MUSB_DEBUG */ diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c index 4ca94cb..dd2aa7f 100644 --- a/drivers/usb/musb/musb_hcd.c +++ b/drivers/usb/musb/musb_hcd.c @@ -35,6 +35,106 @@ static struct musb_epinfo epinfo[3] = { {MUSB_INTR_EP, 0, 64} /* EP2 - Interrupt IN - 64 Bytes */ }; +/* --- Virtual Root Hub ---------------------------------------------------- */ +#ifdef MUSB_NO_MULTIPOINT +static int rh_devnum; +static u32 port_status; + +/* Device descriptor */ +static u8 root_hub_dev_des[] = { + 0x12, /* __u8 bLength; */ + 0x01, /* __u8 bDescriptorType; Device */ + 0x00, /* __u16 bcdUSB; v1.1 */ + 0x02, + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ + 0x00, /* __u8 bDeviceSubClass; */ + 0x00, /* __u8 bDeviceProtocol; */ + 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ + 0x00, /* __u16 idVendor; */ + 0x00, + 0x00, /* __u16 idProduct; */ + 0x00, + 0x00, /* __u16 bcdDevice; */ + 0x00, + 0x00, /* __u8 iManufacturer; */ + 0x01, /* __u8 iProduct; */ + 0x00, /* __u8 iSerialNumber; */ + 0x01 /* __u8 bNumConfigurations; */ +}; + +/* Configuration descriptor */ +static u8 root_hub_config_des[] = { + 0x09, /* __u8 bLength; */ + 0x02, /* __u8 bDescriptorType; Configuration */ + 0x19, /* __u16 wTotalLength; */ + 0x00, + 0x01, /* __u8 bNumInterfaces; */ + 0x01, /* __u8 bConfigurationValue; */ + 0x00, /* __u8 iConfiguration; */ + 0x40, /* __u8 bmAttributes; + Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ + 0x00, /* __u8 MaxPower; */ + + /* interface */ + 0x09, /* __u8 if_bLength; */ + 0x04, /* __u8 if_bDescriptorType; Interface */ + 0x00, /* __u8 if_bInterfaceNumber; */ + 0x00, /* __u8 if_bAlternateSetting; */ + 0x01, /* __u8 if_bNumEndpoints; */ + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* __u8 if_bInterfaceSubClass; */ + 0x00, /* __u8 if_bInterfaceProtocol; */ + 0x00, /* __u8 if_iInterface; */ + + /* endpoint */ + 0x07, /* __u8 ep_bLength; */ + 0x05, /* __u8 ep_bDescriptorType; Endpoint */ + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* __u8 ep_bmAttributes; Interrupt */ + 0x00, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ + 0x02, + 0xff /* __u8 ep_bInterval; 255 ms */ +}; + +static unsigned char root_hub_str_index0[] = { + 0x04, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 0x09, /* __u8 lang ID */ + 0x04, /* __u8 lang ID */ +}; + +static unsigned char root_hub_str_index1[] = { + 0x1c, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 'M', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'U', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'S', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'B', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'R', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'u', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'b', /* __u8 Unicode */ + 0, /* __u8 Unicode */ +}; +#endif + /* * This function writes the data toggle value. */ @@ -402,14 +502,335 @@ static void config_hub_port(struct usb_device *dev, u8 ep) if (dev->parent->children[chid] == dev) break; +#ifndef MUSB_NO_MULTIPOINT /* configure the hub address and the port address */ writeb(hub, &musbr->tar[ep].txhubaddr); writeb((chid + 1), &musbr->tar[ep].txhubport); writeb(hub, &musbr->tar[ep].rxhubaddr); writeb((chid + 1), &musbr->tar[ep].rxhubport); +#endif +} + +#ifdef MUSB_NO_MULTIPOINT + +static void musb_port_reset(int do_reset) +{ + u8 power = readb(&musbr->power); + + if (do_reset) { + power &= 0xf0; + writeb(power | MUSB_POWER_RESET, &musbr->power); + port_status |= USB_PORT_STAT_RESET; + port_status &= ~USB_PORT_STAT_ENABLE; + udelay(30000); + } else { + writeb(power & ~MUSB_POWER_RESET, &musbr->power); + + power = readb(&musbr->power); + if (power & MUSB_POWER_HSMODE) + port_status |= USB_PORT_STAT_HIGH_SPEED; + + port_status &= ~(USB_PORT_STAT_RESET | (USB_PORT_STAT_C_CONNECTION << 16)); + port_status |= USB_PORT_STAT_ENABLE + | (USB_PORT_STAT_C_RESET << 16) + | (USB_PORT_STAT_C_ENABLE << 16); + } } /* + * root hub control + */ +static int musb_submit_rh_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, + struct devrequest *cmd) +{ + int leni = transfer_len; + int len = 0; + int stat = 0; + u32 datab[4]; + u8 *data_buf = (u8 *) datab; + u16 bmRType_bReq; + u16 wValue; + u16 wIndex; + u16 wLength; + u16 int_usb; + + if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { + debug("Root-Hub submit IRQ: NOT implemented\n"); + return 0; + } + + bmRType_bReq = cmd->requesttype | (cmd->request << 8); + wValue = swap_16(cmd->value); + wIndex = swap_16(cmd->index); + wLength = swap_16(cmd->length); + + debug("--- HUB ----------------------------------------\n"); + debug("submit rh urb, req=%x val=%#x index=%#x len=%d\n", + bmRType_bReq, wValue, wIndex, wLength); + debug("------------------------------------------------\n"); + + switch (bmRType_bReq) { + case RH_GET_STATUS: + debug("RH_GET_STATUS\n"); + + *(__u16 *) data_buf = swap_16(1); + len = 2; + break; + + case RH_GET_STATUS | RH_INTERFACE: + debug("RH_GET_STATUS | RH_INTERFACE\n"); + + *(__u16 *) data_buf = swap_16(0); + len = 2; + break; + + case RH_GET_STATUS | RH_ENDPOINT: + debug("RH_GET_STATUS | RH_ENDPOINT\n"); + + *(__u16 *) data_buf = swap_16(0); + len = 2; + break; + + case RH_GET_STATUS | RH_CLASS: + debug("RH_GET_STATUS | RH_CLASS\n"); + + *(__u32 *) data_buf = swap_32(0); + len = 4; + break; + + case RH_GET_STATUS | RH_OTHER | RH_CLASS: + debug("RH_GET_STATUS | RH_OTHER | RH_CLASS\n"); + + int_usb = readw(&musbr->intrusb); + if (int_usb & MUSB_INTR_CONNECT) { + port_status |= USB_PORT_STAT_CONNECTION + | (USB_PORT_STAT_C_CONNECTION << 16); + port_status |= USB_PORT_STAT_HIGH_SPEED + | USB_PORT_STAT_ENABLE; + } + + if (port_status & USB_PORT_STAT_RESET) + musb_port_reset(0); + + *(__u32 *) data_buf = swap_32(port_status); + len = 4; + break; + + case RH_CLEAR_FEATURE | RH_ENDPOINT: + debug("RH_CLEAR_FEATURE | RH_ENDPOINT\n"); + + switch (wValue) { + case RH_ENDPOINT_STALL: + debug("C_HUB_ENDPOINT_STALL\n"); + len = 0; + break; + } + port_status &= ~(1 << wValue); + break; + + case RH_CLEAR_FEATURE | RH_CLASS: + debug("RH_CLEAR_FEATURE | RH_CLASS\n"); + + switch (wValue) { + case RH_C_HUB_LOCAL_POWER: + debug("C_HUB_LOCAL_POWER\n"); + len = 0; + break; + + case RH_C_HUB_OVER_CURRENT: + debug("C_HUB_OVER_CURRENT\n"); + len = 0; + break; + } + port_status &= ~(1 << wValue); + break; + + case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: + debug("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS\n"); + + switch (wValue) { + case RH_PORT_ENABLE: + len = 0; + break; + + case RH_PORT_SUSPEND: + len = 0; + break; + + case RH_PORT_POWER: + len = 0; + break; + + case RH_C_PORT_CONNECTION: + len = 0; + break; + + case RH_C_PORT_ENABLE: + len = 0; + break; + + case RH_C_PORT_SUSPEND: + len = 0; + break; + + case RH_C_PORT_OVER_CURRENT: + len = 0; + break; + + case RH_C_PORT_RESET: + len = 0; + break; + + default: + debug("invalid wValue\n"); + stat = USB_ST_STALLED; + } + + port_status &= ~(1 << wValue); + break; + + case RH_SET_FEATURE | RH_OTHER | RH_CLASS: + debug("RH_SET_FEATURE | RH_OTHER | RH_CLASS\n"); + + switch (wValue) { + case RH_PORT_SUSPEND: + len = 0; + break; + + case RH_PORT_RESET: + musb_port_reset(1); + len = 0; + break; + + case RH_PORT_POWER: + len = 0; + break; + + case RH_PORT_ENABLE: + len = 0; + break; + + default: + debug("invalid wValue\n"); + stat = USB_ST_STALLED; + } + + port_status |= 1 << wValue; + break; + + case RH_SET_ADDRESS: + debug("RH_SET_ADDRESS\n"); + + rh_devnum = wValue; + len = 0; + break; + + case RH_GET_DESCRIPTOR: + debug("RH_GET_DESCRIPTOR: %x, %d\n", wValue, wLength); + + switch (wValue) { + case (USB_DT_DEVICE << 8): /* device descriptor */ + len = min_t(unsigned int, + leni, min_t(unsigned int, + sizeof(root_hub_dev_des), + wLength)); + data_buf = root_hub_dev_des; + break; + + case (USB_DT_CONFIG << 8): /* configuration descriptor */ + len = min_t(unsigned int, + leni, min_t(unsigned int, + sizeof(root_hub_config_des), + wLength)); + data_buf = root_hub_config_des; + break; + + case ((USB_DT_STRING << 8) | 0x00): /* string 0 descriptors */ + len = min_t(unsigned int, + leni, min_t(unsigned int, + sizeof(root_hub_str_index0), + wLength)); + data_buf = root_hub_str_index0; + break; + + case ((USB_DT_STRING << 8) | 0x01): /* string 1 descriptors */ + len = min_t(unsigned int, + leni, min_t(unsigned int, + sizeof(root_hub_str_index1), + wLength)); + data_buf = root_hub_str_index1; + break; + + default: + debug("invalid wValue\n"); + stat = USB_ST_STALLED; + } + + break; + + case RH_GET_DESCRIPTOR | RH_CLASS: + debug("RH_GET_DESCRIPTOR | RH_CLASS\n"); + + data_buf[0] = 0x09; /* min length; */ + data_buf[1] = 0x29; + data_buf[2] = 0x1; /* 1 port */ + data_buf[3] = 0x01; /* per-port power switching */ + data_buf[3] |= 0x10; /* no overcurrent reporting */ + + /* Corresponds to data_buf[4-7] */ + data_buf[4] = 0; + data_buf[5] = 5; + data_buf[6] = 0; + data_buf[7] = 0x02; + data_buf[8] = 0xff; + + len = min_t(unsigned int, leni, + min_t(unsigned int, data_buf[0], wLength)); + break; + + case RH_GET_CONFIGURATION: + debug("RH_GET_CONFIGURATION\n"); + + *(__u8 *) data_buf = 0x01; + len = 1; + break; + + case RH_SET_CONFIGURATION: + debug("RH_SET_CONFIGURATION\n"); + + len = 0; + break; + + default: + debug("*** *** *** unsupported root hub command *** *** ***\n"); + stat = USB_ST_STALLED; + } + + len = min_t(int, len, leni); + if (buffer != data_buf) + memcpy(buffer, data_buf, len); + + dev->act_len = len; + dev->status = stat; + debug("dev act_len %d, status %d\n", dev->act_len, dev->status); + + return stat; +} + +static void musb_rh_init(void) +{ + rh_devnum = 0; + port_status = 0; +} + +#else + +static void musb_rh_init(void) {} + +#endif + +/* * do a control transfer */ int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, @@ -419,13 +840,21 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, u16 csr; u8 devspeed; +#ifdef MUSB_NO_MULTIPOINT + /* Control message is for the HUB? */ + if (devnum == rh_devnum) + return musb_submit_rh_msg(dev, pipe, buffer, len, setup); +#endif + /* select control endpoint */ writeb(MUSB_CONTROL_EP, &musbr->index); csr = readw(&musbr->txcsr); +#ifndef MUSB_NO_MULTIPOINT /* target addr and (for multipoint) hub addr/port */ writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr); writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr); +#endif /* configure the hub address and the port number as required */ devspeed = get_dev_speed(dev); @@ -435,10 +864,12 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, writeb(devspeed << 6, &musbr->txtype); } else { writeb(musb_cfg.musb_speed << 6, &musbr->txtype); +#ifndef MUSB_NO_MULTIPOINT writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubaddr); writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubport); writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubaddr); writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubport); +#endif } /* Control transfer setup phase */ @@ -497,7 +928,9 @@ int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, { int dir_out = usb_pipeout(pipe); int ep = usb_pipeendpoint(pipe); +#ifndef MUSB_NO_MULTIPOINT int devnum = usb_pipedevice(pipe); +#endif u8 type; u16 csr; u32 txlen = 0; @@ -507,11 +940,13 @@ int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, /* select bulk endpoint */ writeb(MUSB_BULK_EP, &musbr->index); +#ifndef MUSB_NO_MULTIPOINT /* write the address of the device */ if (dir_out) writeb(devnum, &musbr->tar[MUSB_BULK_EP].txfuncaddr); else writeb(devnum, &musbr->tar[MUSB_BULK_EP].rxfuncaddr); +#endif /* configure the hub address and the port number as required */ devspeed = get_dev_speed(dev); @@ -524,6 +959,7 @@ int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, */ config_hub_port(dev, MUSB_BULK_EP); } else { +#ifndef MUSB_NO_MULTIPOINT if (dir_out) { writeb(0, &musbr->tar[MUSB_BULK_EP].txhubaddr); writeb(0, &musbr->tar[MUSB_BULK_EP].txhubport); @@ -531,6 +967,7 @@ int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubaddr); writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubport); } +#endif devspeed = musb_cfg.musb_speed; } @@ -590,7 +1027,8 @@ int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, (len-txlen) : dev->epmaxpacketin[ep]; /* Set the ReqPkt bit */ - writew(MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); + csr = readw(&musbr->rxcsr); + writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); /* Wait until the RxPktRdy bit is set */ if (!wait_until_rxep_ready(dev, MUSB_BULK_EP)) { @@ -634,6 +1072,8 @@ int usb_lowlevel_init(void) u8 power; u32 timeout; + musb_rh_init(); + if (musb_platform_init() == -1) return -1; @@ -696,7 +1136,9 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe, { int dir_out = usb_pipeout(pipe); int ep = usb_pipeendpoint(pipe); +#ifndef MUSB_NO_MULTIPOINT int devnum = usb_pipedevice(pipe); +#endif u8 type; u16 csr; u32 txlen = 0; @@ -706,11 +1148,13 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe, /* select interrupt endpoint */ writeb(MUSB_INTR_EP, &musbr->index); +#ifndef MUSB_NO_MULTIPOINT /* write the address of the device */ if (dir_out) writeb(devnum, &musbr->tar[MUSB_INTR_EP].txfuncaddr); else writeb(devnum, &musbr->tar[MUSB_INTR_EP].rxfuncaddr); +#endif /* configure the hub address and the port number as required */ devspeed = get_dev_speed(dev); @@ -723,6 +1167,7 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe, */ config_hub_port(dev, MUSB_INTR_EP); } else { +#ifndef MUSB_NO_MULTIPOINT if (dir_out) { writeb(0, &musbr->tar[MUSB_INTR_EP].txhubaddr); writeb(0, &musbr->tar[MUSB_INTR_EP].txhubport); @@ -730,6 +1175,7 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe, writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubaddr); writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubport); } +#endif devspeed = musb_cfg.musb_speed; } @@ -755,7 +1201,8 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe, (len-txlen) : dev->epmaxpacketin[ep]; /* Set the ReqPkt bit */ - writew(MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); + csr = readw(&musbr->rxcsr); + writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); /* Wait until the RxPktRdy bit is set */ if (!wait_until_rxep_ready(dev, MUSB_INTR_EP)) { @@ -803,7 +1250,7 @@ void usb_event_poll() { struct stdio_dev *dev; struct usb_device *usb_kbd_dev; - struct usb_interface_descriptor *iface; + struct usb_interface *iface; struct usb_endpoint_descriptor *ep; int pipe; int maxp; diff --git a/drivers/usb/musb/musb_hcd.h b/drivers/usb/musb/musb_hcd.h index 17e9091..dde7d37 100644 --- a/drivers/usb/musb/musb_hcd.h +++ b/drivers/usb/musb/musb_hcd.h @@ -38,7 +38,9 @@ extern unsigned char new[]; #define MUSB_CONTROL_EP 0 /* This defines the endpoint number used for bulk transfer */ -#define MUSB_BULK_EP 1 +#ifndef MUSB_BULK_EP +# define MUSB_BULK_EP 1 +#endif /* This defines the endpoint number used for interrupt transfer */ #define MUSB_INTR_EP 2 @@ -48,6 +50,61 @@ extern unsigned char new[]; ((readb(&musbr->power) & MUSB_POWER_HSMODE) \ >> MUSB_POWER_HSMODE_SHIFT) +#define min_t(type, x, y) \ + ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; }) + +/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ + +/* destination of request */ +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 + +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 + +/* Requests: bRequest << 8 | bmRequestType */ +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 +#define RH_SET_ADDRESS 0x0500 +#define RH_GET_DESCRIPTOR 0x0680 +#define RH_SET_DESCRIPTOR 0x0700 +#define RH_GET_CONFIGURATION 0x0880 +#define RH_SET_CONFIGURATION 0x0900 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 +/* Our Vendor Specific Request */ +#define RH_SET_EP 0x2000 + +/* Hub port features */ +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 + +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 + +/* Hub features */ +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 + +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 + +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 + /* extern functions */ extern int musb_platform_init(void); extern void musb_platform_deinit(void); diff --git a/drivers/usb/musb/musb_udc.c b/drivers/usb/musb/musb_udc.c new file mode 100644 index 0000000..fc43cf4 --- /dev/null +++ b/drivers/usb/musb/musb_udc.c @@ -0,0 +1,963 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix <Tom.Rix@windriver.com> + * + * This file is a rewrite of the usb device part of + * repository git.omapzoom.org/repo/u-boot.git, branch master, + * file cpu/omap3/fastboot.c + * + * This is the unique part of its copyright : + * + * ------------------------------------------------------------------------- + * + * (C) Copyright 2008 - 2009 + * Windriver, <www.windriver.com> + * Tom Rix <Tom.Rix@windriver.com> + * + * ------------------------------------------------------------------------- + * + * The details of connecting the device to the uboot usb device subsystem + * came from the old omap3 repository www.sakoman.net/u-boot-omap3.git, + * branch omap3-dev-usb, file drivers/usb/usbdcore_musb.c + * + * This is the unique part of its copyright : + * + * ------------------------------------------------------------------------- + * + * (C) Copyright 2008 Texas Instruments Incorporated. + * + * Based on + * u-boot OMAP1510 USB drivers (drivers/usbdcore_omap1510.c) + * twl4030 init based on linux (drivers/i2c/chips/twl4030_usb.c) + * + * Author: Diego Dompe (diego.dompe@ridgerun.com) + * Atin Malaviya (atin.malaviya@gmail.com) + * + * ------------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <usb/musb_udc.h> +#include "../gadget/ep0.h" +#include "musb_core.h" +#if defined(CONFIG_USB_OMAP3) +#include "omap3.h" +#elif defined(CONFIG_USB_DAVINCI) +#include "davinci.h" +#endif + +/* Define MUSB_DEBUG for debugging */ +/* #define MUSB_DEBUG */ +#include "musb_debug.h" + +#define MAX_ENDPOINT 15 + +#define GET_ENDPOINT(dev,ep) \ +(((struct usb_device_instance *)(dev))->bus->endpoint_array + ep) + +#define SET_EP0_STATE(s) \ +do { \ + if ((0 <= (s)) && (SET_ADDRESS >= (s))) { \ + if ((s) != ep0_state) { \ + if ((debug_setup) && (debug_level > 1)) \ + serial_printf("INFO : Changing state " \ + "from %s to %s in %s at " \ + "line %d\n", \ + ep0_state_strings[ep0_state],\ + ep0_state_strings[s], \ + __PRETTY_FUNCTION__, \ + __LINE__); \ + ep0_state = s; \ + } \ + } else { \ + if (debug_level > 0) \ + serial_printf("Error at %s %d with setting " \ + "state %d is invalid\n", \ + __PRETTY_FUNCTION__, __LINE__, s); \ + } \ +} while (0) + +/* static implies these initialized to 0 or NULL */ +static int debug_setup; +static int debug_level; +static struct musb_epinfo epinfo[MAX_ENDPOINT * 2]; +static enum ep0_state_enum { + IDLE = 0, + TX, + RX, + SET_ADDRESS +} ep0_state = IDLE; +static char *ep0_state_strings[4] = { + "IDLE", + "TX", + "RX", + "SET_ADDRESS", +}; + +static struct urb *ep0_urb; +struct usb_endpoint_instance *ep0_endpoint; +static struct usb_device_instance *udc_device; +static int enabled; + +#ifdef MUSB_DEBUG +static void musb_db_regs(void) +{ + u8 b; + u16 w; + + b = readb(&musbr->faddr); + serial_printf("\tfaddr 0x%2.2x\n", b); + + b = readb(&musbr->power); + musb_print_pwr(b); + + w = readw(&musbr->ep[0].ep0.csr0); + musb_print_csr0(w); + + b = readb(&musbr->devctl); + musb_print_devctl(b); + + b = readb(&musbr->ep[0].ep0.configdata); + musb_print_config(b); + + w = readw(&musbr->frame); + serial_printf("\tframe 0x%4.4x\n", w); + + b = readb(&musbr->index); + serial_printf("\tindex 0x%2.2x\n", b); + + w = readw(&musbr->ep[1].epN.rxmaxp); + musb_print_rxmaxp(w); + + w = readw(&musbr->ep[1].epN.rxcsr); + musb_print_rxcsr(w); + + w = readw(&musbr->ep[1].epN.txmaxp); + musb_print_txmaxp(w); + + w = readw(&musbr->ep[1].epN.txcsr); + musb_print_txcsr(w); +} +#else +#define musb_db_regs() +#endif /* DEBUG_MUSB */ + +static void musb_peri_softconnect(void) +{ + u8 power, devctl; + u8 intrusb; + u16 intrrx, intrtx; + + /* Power off MUSB */ + power = readb(&musbr->power); + power &= ~MUSB_POWER_SOFTCONN; + writeb(power, &musbr->power); + + /* Read intr to clear */ + intrusb = readb(&musbr->intrusb); + intrrx = readw(&musbr->intrrx); + intrtx = readw(&musbr->intrtx); + + udelay(1000 * 1000); /* 1 sec */ + + /* Power on MUSB */ + power = readb(&musbr->power); + power |= MUSB_POWER_SOFTCONN; + /* + * The usb device interface is usb 1.1 + * Disable 2.0 high speed by clearring the hsenable bit. + */ + power &= ~MUSB_POWER_HSENAB; + writeb(power, &musbr->power); + + /* Check if device is in b-peripheral mode */ + devctl = readb(&musbr->devctl); + if (!(devctl & MUSB_DEVCTL_BDEVICE) || + (devctl & MUSB_DEVCTL_HM)) { + serial_printf("ERROR : Unsupport USB mode\n"); + serial_printf("Check that mini-B USB cable is attached " + "to the device\n"); + } + + if (debug_setup && (debug_level > 1)) + musb_db_regs(); +} + +static void musb_peri_reset(void) +{ + if ((debug_setup) && (debug_level > 1)) + serial_printf("INFO : %s reset\n", __PRETTY_FUNCTION__); + + if (ep0_endpoint) + ep0_endpoint->endpoint_address = 0xff; + + /* Sync sw and hw addresses */ + writeb(udc_device->address, &musbr->faddr); + + SET_EP0_STATE(IDLE); +} + +static void musb_peri_resume(void) +{ + /* noop */ +} + +static void musb_peri_ep0_stall(void) +{ + u16 csr0; + + csr0 = readw(&musbr->ep[0].ep0.csr0); + csr0 |= MUSB_CSR0_P_SENDSTALL; + writew(csr0, &musbr->ep[0].ep0.csr0); + if ((debug_setup) && (debug_level > 1)) + serial_printf("INFO : %s stall\n", __PRETTY_FUNCTION__); +} + +static void musb_peri_ep0_ack_req(void) +{ + u16 csr0; + + csr0 = readw(&musbr->ep[0].ep0.csr0); + csr0 |= MUSB_CSR0_P_SVDRXPKTRDY; + writew(csr0, &musbr->ep[0].ep0.csr0); +} + +static void musb_ep0_tx_ready(void) +{ + u16 csr0; + + csr0 = readw(&musbr->ep[0].ep0.csr0); + csr0 |= MUSB_CSR0_TXPKTRDY; + writew(csr0, &musbr->ep[0].ep0.csr0); +} + +static void musb_ep0_tx_ready_and_last(void) +{ + u16 csr0; + + csr0 = readw(&musbr->ep[0].ep0.csr0); + csr0 |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_P_DATAEND); + writew(csr0, &musbr->ep[0].ep0.csr0); +} + +static void musb_peri_ep0_last(void) +{ + u16 csr0; + + csr0 = readw(&musbr->ep[0].ep0.csr0); + csr0 |= MUSB_CSR0_P_DATAEND; + writew(csr0, &musbr->ep[0].ep0.csr0); +} + +static void musb_peri_ep0_set_address(void) +{ + u8 faddr; + writeb(udc_device->address, &musbr->faddr); + + /* Verify */ + faddr = readb(&musbr->faddr); + if (udc_device->address == faddr) { + SET_EP0_STATE(IDLE); + usbd_device_event_irq(udc_device, DEVICE_ADDRESS_ASSIGNED, 0); + if ((debug_setup) && (debug_level > 1)) + serial_printf("INFO : %s Address set to %d\n", + __PRETTY_FUNCTION__, udc_device->address); + } else { + if (debug_level > 0) + serial_printf("ERROR : %s Address missmatch " + "sw %d vs hw %d\n", + __PRETTY_FUNCTION__, + udc_device->address, faddr); + } +} + +static void musb_peri_rx_ack(unsigned int ep) +{ + u16 peri_rxcsr; + + peri_rxcsr = readw(&musbr->ep[ep].epN.rxcsr); + peri_rxcsr &= ~MUSB_RXCSR_RXPKTRDY; + writew(peri_rxcsr, &musbr->ep[ep].epN.rxcsr); +} + +static void musb_peri_tx_ready(unsigned int ep) +{ + u16 peri_txcsr; + + peri_txcsr = readw(&musbr->ep[ep].epN.txcsr); + peri_txcsr |= MUSB_TXCSR_TXPKTRDY; + writew(peri_txcsr, &musbr->ep[ep].epN.txcsr); +} + +static void musb_peri_ep0_zero_data_request(int err) +{ + musb_peri_ep0_ack_req(); + + if (err) { + musb_peri_ep0_stall(); + SET_EP0_STATE(IDLE); + } else { + + musb_peri_ep0_last(); + + /* USBD state */ + switch (ep0_urb->device_request.bRequest) { + case USB_REQ_SET_ADDRESS: + if ((debug_setup) && (debug_level > 1)) + serial_printf("INFO : %s received set " + "address\n", __PRETTY_FUNCTION__); + break; + + case USB_REQ_SET_CONFIGURATION: + if ((debug_setup) && (debug_level > 1)) + serial_printf("INFO : %s Configured\n", + __PRETTY_FUNCTION__); + usbd_device_event_irq(udc_device, DEVICE_CONFIGURED, 0); + break; + } + + /* EP0 state */ + if (USB_REQ_SET_ADDRESS == ep0_urb->device_request.bRequest) { + SET_EP0_STATE(SET_ADDRESS); + } else { + SET_EP0_STATE(IDLE); + } + } +} + +static void musb_peri_ep0_rx_data_request(void) +{ + /* + * This is the completion of the data OUT / RX + * + * Host is sending data to ep0 that is not + * part of setup. This comes from the cdc_recv_setup + * op that is device specific. + * + */ + musb_peri_ep0_ack_req(); + + ep0_endpoint->rcv_urb = ep0_urb; + ep0_urb->actual_length = 0; + SET_EP0_STATE(RX); +} + +static void musb_peri_ep0_tx_data_request(int err) +{ + if (err) { + musb_peri_ep0_stall(); + SET_EP0_STATE(IDLE); + } else { + musb_peri_ep0_ack_req(); + + ep0_endpoint->tx_urb = ep0_urb; + ep0_endpoint->sent = 0; + SET_EP0_STATE(TX); + } +} + +static void musb_peri_ep0_idle(void) +{ + u16 count0; + int err; + u16 csr0; + + /* + * Verify addresses + * A lot of confusion can be caused if the address + * in software, udc layer, does not agree with the + * hardware. Since the setting of the hardware address + * must be set after the set address request, the + * usb state machine is out of sync for a few frame. + * It is a good idea to run this check when changes + * are made to the state machine. + */ + if ((debug_level > 0) && + (ep0_state != SET_ADDRESS)) { + u8 faddr; + + faddr = readb(&musbr->faddr); + if (udc_device->address != faddr) { + serial_printf("ERROR : %s addresses do not" + "match sw %d vs hw %d\n", + __PRETTY_FUNCTION__, + udc_device->address, faddr); + udelay(1000 * 1000); + hang(); + } + } + + csr0 = readw(&musbr->ep[0].ep0.csr0); + + if (!(MUSB_CSR0_RXPKTRDY & csr0)) + goto end; + + count0 = readw(&musbr->ep[0].ep0.count0); + if (count0 == 0) + goto end; + + if (count0 != 8) { + if ((debug_setup) && (debug_level > 1)) + serial_printf("WARN : %s SETUP incorrect size %d\n", + __PRETTY_FUNCTION__, count0); + musb_peri_ep0_stall(); + goto end; + } + + read_fifo(0, count0, &ep0_urb->device_request); + + if (debug_level > 2) + print_usb_device_request(&ep0_urb->device_request); + + if (ep0_urb->device_request.wLength == 0) { + err = ep0_recv_setup(ep0_urb); + + /* Zero data request */ + musb_peri_ep0_zero_data_request(err); + } else { + /* Is data coming or going ? */ + u8 reqType = ep0_urb->device_request.bmRequestType; + + if (USB_REQ_DEVICE2HOST == (reqType & USB_REQ_DIRECTION_MASK)) { + err = ep0_recv_setup(ep0_urb); + /* Device to host */ + musb_peri_ep0_tx_data_request(err); + } else { + /* + * Host to device + * + * The RX routine will call ep0_recv_setup + * when the data packet has arrived. + */ + musb_peri_ep0_rx_data_request(); + } + } + +end: + return; +} + +static void musb_peri_ep0_rx(void) +{ + /* + * This is the completion of the data OUT / RX + * + * Host is sending data to ep0 that is not + * part of setup. This comes from the cdc_recv_setup + * op that is device specific. + * + * Pass the data back to driver ep0_recv_setup which + * should give the cdc_recv_setup the chance to handle + * the rx + */ + u16 csr0; + u16 count0; + + if (debug_level > 3) { + if (0 != ep0_urb->actual_length) { + serial_printf("%s finished ? %d of %d\n", + __PRETTY_FUNCTION__, + ep0_urb->actual_length, + ep0_urb->device_request.wLength); + } + } + + if (ep0_urb->device_request.wLength == ep0_urb->actual_length) { + musb_peri_ep0_last(); + SET_EP0_STATE(IDLE); + ep0_recv_setup(ep0_urb); + return; + } + + csr0 = readw(&musbr->ep[0].ep0.csr0); + if (!(MUSB_CSR0_RXPKTRDY & csr0)) + return; + + count0 = readw(&musbr->ep[0].ep0.count0); + + if (count0) { + struct usb_endpoint_instance *endpoint; + u32 length; + u8 *data; + + endpoint = ep0_endpoint; + if (endpoint && endpoint->rcv_urb) { + struct urb *urb = endpoint->rcv_urb; + unsigned int remaining_space = urb->buffer_length - + urb->actual_length; + + if (remaining_space) { + int urb_bad = 0; /* urb is good */ + + if (count0 > remaining_space) + length = remaining_space; + else + length = count0; + + data = (u8 *) urb->buffer_data; + data += urb->actual_length; + + /* The common musb fifo reader */ + read_fifo(0, length, data); + + musb_peri_ep0_ack_req(); + + /* + * urb's actual_length is updated in + * usbd_rcv_complete + */ + usbd_rcv_complete(endpoint, length, urb_bad); + + } else { + if (debug_level > 0) + serial_printf("ERROR : %s no space in " + "rcv buffer\n", + __PRETTY_FUNCTION__); + } + } else { + if (debug_level > 0) + serial_printf("ERROR : %s problem with " + "endpoint\n", + __PRETTY_FUNCTION__); + } + } else { + if (debug_level > 0) + serial_printf("ERROR : %s with nothing to do\n", + __PRETTY_FUNCTION__); + } +} + +static void musb_peri_ep0_tx(void) +{ + u16 csr0; + int transfer_size = 0; + unsigned int p, pm; + + csr0 = readw(&musbr->ep[0].ep0.csr0); + + /* Check for pending tx */ + if (csr0 & MUSB_CSR0_TXPKTRDY) + goto end; + + /* Check if this is the last packet sent */ + if (ep0_endpoint->sent >= ep0_urb->actual_length) { + SET_EP0_STATE(IDLE); + goto end; + } + + transfer_size = ep0_urb->actual_length - ep0_endpoint->sent; + /* Is the transfer size negative ? */ + if (transfer_size <= 0) { + if (debug_level > 0) + serial_printf("ERROR : %s problem with the" + " transfer size %d\n", + __PRETTY_FUNCTION__, + transfer_size); + SET_EP0_STATE(IDLE); + goto end; + } + + /* Truncate large transfers to the fifo size */ + if (transfer_size > ep0_endpoint->tx_packetSize) + transfer_size = ep0_endpoint->tx_packetSize; + + write_fifo(0, transfer_size, &ep0_urb->buffer[ep0_endpoint->sent]); + ep0_endpoint->sent += transfer_size; + + /* Done or more to send ? */ + if (ep0_endpoint->sent >= ep0_urb->actual_length) + musb_ep0_tx_ready_and_last(); + else + musb_ep0_tx_ready(); + + /* Wait a bit */ + pm = 10; + for (p = 0; p < pm; p++) { + csr0 = readw(&musbr->ep[0].ep0.csr0); + if (!(csr0 & MUSB_CSR0_TXPKTRDY)) + break; + + /* Double the delay. */ + udelay(1 << pm); + } + + if ((ep0_endpoint->sent >= ep0_urb->actual_length) && (p < pm)) + SET_EP0_STATE(IDLE); + +end: + return; +} + +static void musb_peri_ep0(void) +{ + u16 csr0; + + if (SET_ADDRESS == ep0_state) + return; + + csr0 = readw(&musbr->ep[0].ep0.csr0); + + /* Error conditions */ + if (MUSB_CSR0_P_SENTSTALL & csr0) { + csr0 &= ~MUSB_CSR0_P_SENTSTALL; + writew(csr0, &musbr->ep[0].ep0.csr0); + SET_EP0_STATE(IDLE); + } + if (MUSB_CSR0_P_SETUPEND & csr0) { + csr0 |= MUSB_CSR0_P_SVDSETUPEND; + writew(csr0, &musbr->ep[0].ep0.csr0); + SET_EP0_STATE(IDLE); + if ((debug_setup) && (debug_level > 1)) + serial_printf("WARN: %s SETUPEND\n", + __PRETTY_FUNCTION__); + } + + /* Normal states */ + if (IDLE == ep0_state) + musb_peri_ep0_idle(); + + if (TX == ep0_state) + musb_peri_ep0_tx(); + + if (RX == ep0_state) + musb_peri_ep0_rx(); +} + +static void musb_peri_rx_ep(unsigned int ep) +{ + u16 peri_rxcount = readw(&musbr->ep[ep].epN.rxcount); + + if (peri_rxcount) { + struct usb_endpoint_instance *endpoint; + u32 length; + u8 *data; + + endpoint = GET_ENDPOINT(udc_device, ep); + if (endpoint && endpoint->rcv_urb) { + struct urb *urb = endpoint->rcv_urb; + unsigned int remaining_space = urb->buffer_length - + urb->actual_length; + + if (remaining_space) { + int urb_bad = 0; /* urb is good */ + + if (peri_rxcount > remaining_space) + length = remaining_space; + else + length = peri_rxcount; + + data = (u8 *) urb->buffer_data; + data += urb->actual_length; + + /* The common musb fifo reader */ + read_fifo(ep, length, data); + + musb_peri_rx_ack(ep); + + /* + * urb's actual_length is updated in + * usbd_rcv_complete + */ + usbd_rcv_complete(endpoint, length, urb_bad); + + } else { + if (debug_level > 0) + serial_printf("ERROR : %s %d no space " + "in rcv buffer\n", + __PRETTY_FUNCTION__, ep); + } + } else { + if (debug_level > 0) + serial_printf("ERROR : %s %d problem with " + "endpoint\n", + __PRETTY_FUNCTION__, ep); + } + + } else { + if (debug_level > 0) + serial_printf("ERROR : %s %d with nothing to do\n", + __PRETTY_FUNCTION__, ep); + } +} + +static void musb_peri_rx(u16 intr) +{ + unsigned int ep; + + /* Check for EP0 */ + if (0x01 & intr) + musb_peri_ep0(); + + for (ep = 1; ep < 16; ep++) { + if ((1 << ep) & intr) + musb_peri_rx_ep(ep); + } +} + +static void musb_peri_tx(u16 intr) +{ + /* Check for EP0 */ + if (0x01 & intr) + musb_peri_ep0_tx(); + + /* + * Use this in the future when handling epN tx + * + * u8 ep; + * + * for (ep = 1; ep < 16; ep++) { + * if ((1 << ep) & intr) { + * / * handle tx for this endpoint * / + * } + * } + */ +} + +void udc_irq(void) +{ + /* This is a high freq called function */ + if (enabled) { + u8 intrusb; + + intrusb = readb(&musbr->intrusb); + + /* + * See drivers/usb/gadget/mpc8xx_udc.c for + * state diagram going from detached through + * configuration. + */ + if (MUSB_INTR_RESUME & intrusb) { + usbd_device_event_irq(udc_device, + DEVICE_BUS_ACTIVITY, 0); + musb_peri_resume(); + } + + musb_peri_ep0(); + + if (MUSB_INTR_RESET & intrusb) { + usbd_device_event_irq(udc_device, DEVICE_RESET, 0); + musb_peri_reset(); + } + + if (MUSB_INTR_DISCONNECT & intrusb) { + /* cable unplugged from hub/host */ + usbd_device_event_irq(udc_device, DEVICE_RESET, 0); + musb_peri_reset(); + usbd_device_event_irq(udc_device, DEVICE_HUB_RESET, 0); + } + + if (MUSB_INTR_SOF & intrusb) { + usbd_device_event_irq(udc_device, + DEVICE_BUS_ACTIVITY, 0); + musb_peri_resume(); + } + + if (MUSB_INTR_SUSPEND & intrusb) { + usbd_device_event_irq(udc_device, + DEVICE_BUS_INACTIVE, 0); + } + + if (ep0_state != SET_ADDRESS) { + u16 intrrx, intrtx; + + intrrx = readw(&musbr->intrrx); + intrtx = readw(&musbr->intrtx); + + if (intrrx) + musb_peri_rx(intrrx); + + if (intrtx) + musb_peri_tx(intrtx); + } else { + if (MUSB_INTR_SOF & intrusb) { + u8 faddr; + faddr = readb(&musbr->faddr); + /* + * Setting of the address can fail. + * Normally it succeeds the second time. + */ + if (udc_device->address != faddr) + musb_peri_ep0_set_address(); + } + } + } +} + +void udc_set_nak(int ep_num) +{ + /* noop */ +} + +void udc_unset_nak(int ep_num) +{ + /* noop */ +} + +int udc_endpoint_write(struct usb_endpoint_instance *endpoint) +{ + int ret = 0; + + /* Transmit only if the hardware is available */ + if (endpoint->tx_urb && endpoint->state == 0) { + unsigned int ep = endpoint->endpoint_address & + USB_ENDPOINT_NUMBER_MASK; + + u16 peri_txcsr = readw(&musbr->ep[ep].epN.txcsr); + + /* Error conditions */ + if (peri_txcsr & MUSB_TXCSR_P_UNDERRUN) { + peri_txcsr &= ~MUSB_TXCSR_P_UNDERRUN; + writew(peri_txcsr, &musbr->ep[ep].epN.txcsr); + } + + if (debug_level > 1) + musb_print_txcsr(peri_txcsr); + + /* Check if a packet is waiting to be sent */ + if (!(peri_txcsr & MUSB_TXCSR_TXPKTRDY)) { + u32 length; + u8 *data; + struct urb *urb = endpoint->tx_urb; + unsigned int remaining_packet = urb->actual_length - + endpoint->sent; + + if (endpoint->tx_packetSize < remaining_packet) + length = endpoint->tx_packetSize; + else + length = remaining_packet; + + data = (u8 *) urb->buffer; + data += endpoint->sent; + + /* common musb fifo function */ + write_fifo(ep, length, data); + + musb_peri_tx_ready(ep); + + endpoint->last = length; + /* usbd_tx_complete will take care of updating 'sent' */ + usbd_tx_complete(endpoint); + } + } else { + if (debug_level > 0) + serial_printf("ERROR : %s Problem with urb %p " + "or ep state %d\n", + __PRETTY_FUNCTION__, + endpoint->tx_urb, endpoint->state); + } + + return ret; +} + +void udc_setup_ep(struct usb_device_instance *device, unsigned int id, + struct usb_endpoint_instance *endpoint) +{ + if (0 == id) { + /* EP0 */ + ep0_endpoint = endpoint; + ep0_endpoint->endpoint_address = 0xff; + ep0_urb = usbd_alloc_urb(device, endpoint); + } else if (MAX_ENDPOINT >= id) { + int ep_addr; + + /* Check the direction */ + ep_addr = endpoint->endpoint_address; + if (USB_DIR_IN == (ep_addr & USB_ENDPOINT_DIR_MASK)) { + /* IN */ + epinfo[(id * 2) + 1].epsize = endpoint->tx_packetSize; + } else { + /* OUT */ + epinfo[id * 2].epsize = endpoint->rcv_packetSize; + } + + musb_configure_ep(&epinfo[0], + sizeof(epinfo) / sizeof(struct musb_epinfo)); + } else { + if (debug_level > 0) + serial_printf("ERROR : %s endpoint request %d " + "exceeds maximum %d\n", + __PRETTY_FUNCTION__, id, MAX_ENDPOINT); + } +} + +void udc_connect(void) +{ + /* noop */ +} + +void udc_disconnect(void) +{ + /* noop */ +} + +void udc_enable(struct usb_device_instance *device) +{ + /* Save the device structure pointer */ + udc_device = device; + + enabled = 1; +} + +void udc_disable(void) +{ + enabled = 0; +} + +void udc_startup_events(struct usb_device_instance *device) +{ + /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */ + usbd_device_event_irq(device, DEVICE_INIT, 0); + + /* + * The DEVICE_CREATE event puts the USB device in the state + * STATE_ATTACHED. + */ + usbd_device_event_irq(device, DEVICE_CREATE, 0); + + /* Resets the address to 0 */ + usbd_device_event_irq(device, DEVICE_RESET, 0); + + udc_enable(device); +} + +int udc_init(void) +{ + int ret; + int ep_loop; + + ret = musb_platform_init(); + if (ret < 0) + goto end; + + /* Configure all the endpoint FIFO's and start usb controller */ + musbr = musb_cfg.regs; + + /* Initialize the endpoints */ + for (ep_loop = 0; ep_loop < MAX_ENDPOINT * 2; ep_loop++) { + epinfo[ep_loop].epnum = (ep_loop / 2) + 1; + epinfo[ep_loop].epdir = ep_loop % 2; /* OUT, IN */ + epinfo[ep_loop].epsize = 0; + } + + musb_peri_softconnect(); + + ret = 0; +end: + + return ret; +} diff --git a/drivers/usb/musb/omap3.c b/drivers/usb/musb/omap3.c new file mode 100644 index 0000000..3bfd0a0 --- /dev/null +++ b/drivers/usb/musb/omap3.c @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix <Tom.Rix@windriver.com> + * + * This is file is based on + * repository git.gitorious.org/u-boot-omap3/mainline.git, + * branch omap3-dev-usb, file drivers/usb/host/omap3530_usb.c + * + * This is the unique part of its copyright : + * + * ------------------------------------------------------------------------ + * + * Copyright (c) 2009 Texas Instruments + * + * ------------------------------------------------------------------------ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <twl4030.h> +#include "omap3.h" + +static int platform_needs_initialization = 1; + +struct musb_config musb_cfg = { + (struct musb_regs *)MENTOR_USB0_BASE, + OMAP3_USB_TIMEOUT, + 0 +}; + +/* + * OMAP3 USB OTG registers. + */ +struct omap3_otg_regs { + u32 revision; + u32 sysconfig; + u32 sysstatus; + u32 interfsel; + u32 simenable; + u32 forcestdby; +}; + +static struct omap3_otg_regs *otg; + +#define OMAP3_OTG_SYSCONFIG_SMART_STANDBY_MODE 0x2000 +#define OMAP3_OTG_SYSCONFIG_NO_STANDBY_MODE 0x1000 +#define OMAP3_OTG_SYSCONFIG_SMART_IDLE_MODE 0x0010 +#define OMAP3_OTG_SYSCONFIG_NO_IDLE_MODE 0x0008 +#define OMAP3_OTG_SYSCONFIG_ENABLEWAKEUP 0x0004 +#define OMAP3_OTG_SYSCONFIG_SOFTRESET 0x0002 +#define OMAP3_OTG_SYSCONFIG_AUTOIDLE 0x0001 + +#define OMAP3_OTG_SYSSTATUS_RESETDONE 0x0001 + +#define OMAP3_OTG_INTERFSEL_OMAP 0x0001 + +#define OMAP3_OTG_FORCESTDBY_STANDBY 0x0001 + + +#ifdef DEBUG_MUSB_OMAP3 +static void musb_db_otg_regs(void) +{ + u32 l; + l = readl(&otg->revision); + serial_printf("OTG_REVISION 0x%x\n", l); + l = readl(&otg->sysconfig); + serial_printf("OTG_SYSCONFIG 0x%x\n", l); + l = readl(&otg->sysstatus); + serial_printf("OTG_SYSSTATUS 0x%x\n", l); + l = readl(&otg->interfsel); + serial_printf("OTG_INTERFSEL 0x%x\n", l); + l = readl(&otg->forcestdby); + serial_printf("OTG_FORCESTDBY 0x%x\n", l); +} +#endif + +int musb_platform_init(void) +{ + int ret = -1; + + if (platform_needs_initialization) { + u32 stdby; + + /* + * OMAP3EVM uses ISP1504 phy and so + * twl4030 related init is not required. + */ +#ifdef CONFIG_TWL4030_USB + if (twl4030_usb_ulpi_init()) { + serial_printf("ERROR: %s Could not initialize PHY\n", + __PRETTY_FUNCTION__); + goto end; + } +#endif + otg = (struct omap3_otg_regs *)OMAP3_OTG_BASE; + + /* Set OTG to always be on */ + writel(OMAP3_OTG_SYSCONFIG_NO_STANDBY_MODE | + OMAP3_OTG_SYSCONFIG_NO_IDLE_MODE, &otg->sysconfig); + + /* Set the interface */ + writel(OMAP3_OTG_INTERFSEL_OMAP, &otg->interfsel); + + /* Clear force standby */ + stdby = readl(&otg->forcestdby); + stdby &= ~OMAP3_OTG_FORCESTDBY_STANDBY; + writel(stdby, &otg->forcestdby); + + platform_needs_initialization = 0; + } + + ret = platform_needs_initialization; + +#ifdef CONFIG_TWL4030_USB +end: +#endif + return ret; + +} + +void musb_platform_deinit(void) +{ + /* noop */ +} diff --git a/drivers/usb/musb/omap3.h b/drivers/usb/musb/omap3.h new file mode 100644 index 0000000..20fc9d2 --- /dev/null +++ b/drivers/usb/musb/omap3.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix <Tom.Rix@windriver.com> + * + * This file is based on the file drivers/usb/musb/davinci.h + * + * This is the unique part of its copyright: + * + * -------------------------------------------------------------------- + * + * Copyright (c) 2008 Texas Instruments + * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments + * + * -------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _MUSB_OMAP3_H_ +#define _MUSB_OMAP3_H_ + +#include "musb_core.h" + +/* Base address of MUSB registers */ +#define MENTOR_USB0_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000) + +/* Base address of OTG registers */ +#define OMAP3_OTG_BASE (MENTOR_USB0_BASE + 0x400) + +/* Timeout for USB module */ +#define OMAP3_USB_TIMEOUT 0x3FFFFFF + +int musb_platform_init(void); + +#endif /* _MUSB_OMAP3_H */ + diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile new file mode 100644 index 0000000..200b907 --- /dev/null +++ b/drivers/usb/phy/Makefile @@ -0,0 +1,44 @@ +# +# Copyright (c) 2009 Wind River Systems, Inc. +# Tom Rix <Tom.Rix@windriver.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)libusb_phy.a + +COBJS-$(CONFIG_TWL4030_USB) += twl4030.o +COBJS-y := twl4030.o + +COBJS := $(COBJS-y) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/drivers/usb/phy/twl4030.c b/drivers/usb/phy/twl4030.c new file mode 100644 index 0000000..54d2e61 --- /dev/null +++ b/drivers/usb/phy/twl4030.c @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix <Tom.Rix@windriver.com> + * + * This is file is based on + * repository git.gitorious.org/u-boot-omap3/mainline.git, + * branch omap3-dev-usb, file drivers/usb/gadget/twl4030_usb.c + * + * This is the unique part of its copyright : + * + * ------------------------------------------------------------------------ + * + * * (C) Copyright 2009 Atin Malaviya (atin.malaviya@gmail.com) + * + * Based on: twl4030_usb.c in linux 2.6 (drivers/i2c/chips/twl4030_usb.c) + * Copyright (C) 2004-2007 Texas Instruments + * Copyright (C) 2008 Nokia Corporation + * Contact: Felipe Balbi <felipe.balbi@nokia.com> + * + * Author: Atin Malaviya (atin.malaviya@gmail.com) + * + * ------------------------------------------------------------------------ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <twl4030.h> + +/* Defines for bits in registers */ +#define OPMODE_MASK (3 << 3) +#define XCVRSELECT_MASK (3 << 0) +#define CARKITMODE (1 << 2) +#define OTG_ENAB (1 << 5) +#define PHYPWD (1 << 0) +#define CLOCKGATING_EN (1 << 2) +#define CLK32K_EN (1 << 1) +#define REQ_PHY_DPLL_CLK (1 << 0) +#define PHY_DPLL_CLK (1 << 0) + +static int twl4030_usb_write(u8 address, u8 data) +{ + int ret; + + ret = twl4030_i2c_write_u8(TWL4030_CHIP_USB, data, address); + if (ret != 0) + printf("TWL4030:USB:Write[0x%x] Error %d\n", address, ret); + + return ret; +} + +static int twl4030_usb_read(u8 address) +{ + u8 data; + int ret; + + ret = twl4030_i2c_read_u8(TWL4030_CHIP_USB, &data, address); + if (ret == 0) + ret = data; + else + printf("TWL4030:USB:Read[0x%x] Error %d\n", address, ret); + + return ret; +} + +static void twl4030_usb_ldo_init(void) +{ + /* Enable writing to power configuration registers */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0xC0, + TWL4030_PM_MASTER_PROTECT_KEY); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x0C, + TWL4030_PM_MASTER_PROTECT_KEY); + + /* put VUSB3V1 LDO in active state */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00, + TWL4030_PM_RECEIVER_VUSB_DEDICATED2); + + /* input to VUSB3V1 LDO is from VBAT, not VBUS */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x14, + TWL4030_PM_RECEIVER_VUSB_DEDICATED1); + + /* turn on 3.1V regulator */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20, + TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00, + TWL4030_PM_RECEIVER_VUSB3V1_TYPE); + + /* turn on 1.5V regulator */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20, + TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00, + TWL4030_PM_RECEIVER_VUSB1V5_TYPE); + + /* turn on 1.8V regulator */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20, + TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00, + TWL4030_PM_RECEIVER_VUSB1V8_TYPE); + + /* disable access to power configuration registers */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x00, + TWL4030_PM_MASTER_PROTECT_KEY); +} + +static void twl4030_phy_power(void) +{ + u8 pwr, clk; + + /* Power the PHY */ + pwr = twl4030_usb_read(TWL4030_USB_PHY_PWR_CTRL); + pwr &= ~PHYPWD; + twl4030_usb_write(TWL4030_USB_PHY_PWR_CTRL, pwr); + /* Enable clocks */ + clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL); + clk |= CLOCKGATING_EN | CLK32K_EN; + twl4030_usb_write(TWL4030_USB_PHY_CLK_CTRL, clk); +} + +/* + * Initiaze the ULPI interface + * ULPI : Universal Transceiver Macrocell Low Pin Interface + * An interface between the USB link controller like musb and the + * the PHY or transceiver that drives the actual bus. + */ +int twl4030_usb_ulpi_init(void) +{ + long timeout = 1000 * 1000; /* 1 sec */; + u8 clk, sts, pwr; + + /* twl4030 ldo init */ + twl4030_usb_ldo_init(); + + /* Enable the twl4030 phy */ + twl4030_phy_power(); + + /* Enable DPLL to access PHY registers over I2C */ + clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL); + clk |= REQ_PHY_DPLL_CLK; + twl4030_usb_write(TWL4030_USB_PHY_CLK_CTRL, clk); + + /* Check if the PHY DPLL is locked */ + sts = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL_STS); + while (!(sts & PHY_DPLL_CLK) && 0 < timeout) { + udelay(10); + sts = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL_STS); + timeout -= 10; + } + + /* Final check */ + sts = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL_STS); + if (!(sts & PHY_DPLL_CLK)) { + printf("Error:TWL4030:USB Timeout setting PHY DPLL clock\n"); + return -1; + } + + /* + * There are two circuit blocks attached to the PHY, + * Carkit and USB OTG. Disable Carkit and enable USB OTG + */ + twl4030_usb_write(TWL4030_USB_IFC_CTRL_CLR, CARKITMODE); + pwr = twl4030_usb_read(TWL4030_USB_POWER_CTRL); + pwr |= OTG_ENAB; + twl4030_usb_write(TWL4030_USB_POWER_CTRL_SET, pwr); + + /* Clear the opmode bits to ensure normal encode */ + twl4030_usb_write(TWL4030_USB_FUNC_CTRL_CLR, OPMODE_MASK); + + /* Clear the xcvrselect bits to enable the high speed transeiver */ + twl4030_usb_write(TWL4030_USB_FUNC_CTRL_CLR, XCVRSELECT_MASK); + + /* Let ULPI control the DPLL clock */ + clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL); + clk &= ~REQ_PHY_DPLL_CLK; + twl4030_usb_write(TWL4030_USB_PHY_CLK_CTRL, clk); + + return 0; +} diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index fbc4df9..c07a26e 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -146,9 +146,11 @@ CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability of the #ifdef CONFIG_VIDEO_CORALP #define VIDEO_FB_LITTLE_ENDIAN #endif +#ifdef CONFIG_VIDEO_MB862xx_ACCEL #define VIDEO_HW_RECTFILL #define VIDEO_HW_BITBLT #endif +#endif /*****************************************************************************/ /* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc */ @@ -319,7 +321,7 @@ void console_cursor (int state); #else #define SWAP16(x) (x) #define SWAP32(x) (x) -#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) +#if defined(VIDEO_FB_16BPP_WORD_SWAP) #define SHORTSWAP32(x) ( ((x) >> 16) | ((x) << 16) ) #else #define SHORTSWAP32(x) (x) @@ -401,8 +403,6 @@ static const int video_font_draw_table32[16][4] = { { 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff } }; -int gunzip(void *, int, unsigned char *, unsigned long *); - /******************************************************************************/ static void video_drawchars (int xx, int yy, unsigned char *s, int count) diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c index a8676cc..edf34aa 100644 --- a/drivers/video/mb862xx.c +++ b/drivers/video/mb862xx.c @@ -89,6 +89,7 @@ unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 }; (GC_DISP_BASE | GC_L0PAL0) + \ ((idx) << 2)), (val)) +#if defined(CONFIG_VIDEO_MB862xx_ACCEL) static void gdc_sw_reset (void) { GraphicDevice *dev = &mb862xx; @@ -129,6 +130,7 @@ static void de_wait_slots (int slots) break; } } +#endif #if !defined(CONFIG_VIDEO_CORALP) static void board_disp_init (void) @@ -144,11 +146,13 @@ static void board_disp_init (void) #endif /* - * Init drawing engine + * Init drawing engine if accel enabled. + * Also clears visible framebuffer. */ static void de_init (void) { GraphicDevice *dev = &mb862xx; +#if defined(CONFIG_VIDEO_MB862xx_ACCEL) int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000; dev->dprBase = dev->frameAdrs + GC_DRAW_BASE; @@ -174,6 +178,14 @@ static void de_init (void) DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX); /* sync with SW access to framebuffer */ de_wait (); +#else + unsigned int i, *p; + + i = dev->winSizeX * dev->winSizeY; + p = (unsigned int *)dev->frameAdrs; + while (i--) + *p++ = 0; +#endif } #if defined(CONFIG_VIDEO_CORALP) @@ -340,6 +352,30 @@ unsigned int card_init (void) } #endif + +#if !defined(CONFIG_VIDEO_CORALP) +int mb862xx_probe(unsigned int addr) +{ + GraphicDevice *dev = &mb862xx; + unsigned int reg; + + dev->frameAdrs = addr; + dev->dprBase = dev->frameAdrs + GC_DRAW_BASE; + + /* Try to access GDC ID/Revision registers */ + reg = HOST_RD_REG (GC_CID); + reg = HOST_RD_REG (GC_CID); + if (reg == 0x303) { + reg = DE_RD_REG(GC_REV); + reg = DE_RD_REG(GC_REV); + if ((reg & ~0xff) == 0x20050100) + return MB862XX_TYPE_LIME; + } + + return 0; +} +#endif + void *video_hw_init (void) { GraphicDevice *dev = &mb862xx; @@ -359,8 +395,16 @@ void *video_hw_init (void) if ((dev->frameAdrs = board_video_init ()) == 0) { puts ("Controller not found!\n"); return NULL; - } else + } else { puts ("Lime\n"); + + /* Set Change of Clock Frequency Register */ + HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF); + /* Delay required */ + udelay(300); + /* Set Memory I/F Mode Register) */ + HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR); + } #endif de_init (); @@ -389,6 +433,7 @@ void video_set_lut (unsigned int index, unsigned char r, L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b)); } +#if defined(CONFIG_VIDEO_MB862xx_ACCEL) /* * Drawing engine Fill and BitBlt screen region */ @@ -430,3 +475,4 @@ void video_hw_bitblt (unsigned int bpp, unsigned int src_x, DE_WR_FIFO ((height << 16) | width); de_wait (); /* sync */ } +#endif |