diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/i2c/Makefile | 1 | ||||
| -rw-r--r-- | drivers/i2c/mxc_i2c.c | 207 | ||||
| -rw-r--r-- | drivers/net/Makefile | 3 | ||||
| -rw-r--r-- | drivers/net/smc911x.c | 680 | ||||
| -rw-r--r-- | drivers/net/xilinx_emac.c | 462 | ||||
| -rw-r--r-- | drivers/net/xilinx_emaclite.c | 351 |
6 files changed, 815 insertions, 889 deletions
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 071ef00..29d6c03 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -29,7 +29,6 @@ COBJS-y += fsl_i2c.o COBJS-y += omap1510_i2c.o COBJS-y += omap24xx_i2c.o COBJS-y += tsi108_i2c.o -COBJS-y += mxc_i2c.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c deleted file mode 100644 index 3c2a9cf..0000000 --- a/drivers/i2c/mxc_i2c.c +++ /dev/null @@ -1,207 +0,0 @@ -/* - * i2c driver for Freescale mx31 - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -#if defined(CONFIG_HARD_I2C) && defined(CONFIG_I2C_MXC) - -#include <asm/arch/mx31.h> -#include <asm/arch/mx31-regs.h> - -#define IADR 0x00 -#define IFDR 0x04 -#define I2CR 0x08 -#define I2SR 0x0c -#define I2DR 0x10 - -#define I2CR_IEN (1 << 7) -#define I2CR_IIEN (1 << 6) -#define I2CR_MSTA (1 << 5) -#define I2CR_MTX (1 << 4) -#define I2CR_TX_NO_AK (1 << 3) -#define I2CR_RSTA (1 << 2) - -#define I2SR_ICF (1 << 7) -#define I2SR_IBB (1 << 5) -#define I2SR_IIF (1 << 1) -#define I2SR_RX_NO_AK (1 << 0) - -#ifdef CFG_I2C_MX31_PORT1 -#define I2C_BASE 0x43f80000 -#elif defined(CFG_I2C_MX31_PORT2) -#define I2C_BASE 0x43f98000 -#elif defined(CFG_I2C_MX31_PORT3) -#define I2C_BASE 0x43f84000 -#else -#error "define CFG_I2C_MX31_PORTx to use the mx31 I2C driver" -#endif - -#ifdef DEBUG -#define DPRINTF(args...) printf(args) -#else -#define DPRINTF(args...) -#endif - -static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144, - 160, 192, 240, 288, 320, 384, 480, 576, 640, 768, 960, - 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840}; - -void i2c_init(int speed, int unused) -{ - int freq = mx31_get_ipg_clk(); - int i; - - for (i = 0; i < 0x1f; i++) - if (freq / div[i] <= speed) - break; - - DPRINTF("%s: speed: %d\n", __FUNCTION__, speed); - - __REG16(I2C_BASE + I2CR) = 0; /* Reset module */ - __REG16(I2C_BASE + IFDR) = i; - __REG16(I2C_BASE + I2CR) = I2CR_IEN; - __REG16(I2C_BASE + I2SR) = 0; -} - -static int wait_busy(void) -{ - int timeout = 10000; - - while (!(__REG16(I2C_BASE + I2SR) & I2SR_IIF) && --timeout) - udelay(1); - __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */ - - return timeout; -} - -static int tx_byte(u8 byte) -{ - __REG16(I2C_BASE + I2DR) = byte; - - if (!wait_busy() || __REG16(I2C_BASE + I2SR) & I2SR_RX_NO_AK) - return -1; - return 0; -} - -static int rx_byte(void) -{ - if (!wait_busy()) - return -1; - - return __REG16(I2C_BASE + I2DR); -} - -int i2c_probe(uchar chip) -{ - int ret; - - __REG16(I2C_BASE + I2CR) = 0; /* Reset module */ - __REG16(I2C_BASE + I2CR) = I2CR_IEN; - - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX; - ret = tx_byte(chip << 1); - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MTX; - - return ret; -} - -static int i2c_addr(uchar chip, uint addr, int alen) -{ - __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */ - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX; - - if (tx_byte(chip << 1)) - return -1; - - while (alen--) - if (tx_byte((addr >> (alen * 8)) & 0xff)) - return -1; - return 0; -} - -int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) -{ - int timeout = 10000; - int ret; - - DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: +%d\n", \ - __FUNCTION__, chip, addr, alen, len); - - if (i2c_addr(chip, addr, alen)) { - printf("i2c_addr failed\n"); - return -1; - } - - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | \ - I2CR_MTX | I2CR_RSTA; - - if (tx_byte(chip << 1 | 1)) - return -1; - - __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | ((len == 1) \ - ? I2CR_TX_NO_AK : 0); - - ret = __REG16(I2C_BASE + I2DR); - - while (len--) { - if ((ret = rx_byte()) < 0) - return -1; - *buf++ = ret; - if (len <= 1) - __REG16(I2C_BASE + I2CR) = I2CR_IEN | \ - I2CR_MSTA | I2CR_TX_NO_AK; - } - - wait_busy(); - - __REG16(I2C_BASE + I2CR) = I2CR_IEN; - - while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout) - udelay(1); - - return 0; -} - -int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) -{ - int timeout = 10000; - DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n", \ - __FUNCTION__, chip, addr, alen, len); - - if (i2c_addr(chip, addr, alen)) - return -1; - - while (len--) - if (tx_byte(*buf++)) - return -1; - - __REG16(I2C_BASE + I2CR) = I2CR_IEN; - - while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout) - udelay(1); - - return 0; -} - -#endif /* CONFIG_HARD_I2C */ diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 6f0225b..a4c1768 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -55,12 +55,13 @@ COBJS-y += rtl8139.o COBJS-y += rtl8169.o COBJS-y += s3c4510b_eth.o COBJS-y += smc91111.o -COBJS-y += smc911x.o COBJS-y += tigon3.o COBJS-y += tsec.o COBJS-y += tsi108_eth.o COBJS-y += uli526x.o COBJS-y += vsc7385.o +COBJS-$(CONFIG_XILINX_EMAC) += xilinx_emac.o +COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c deleted file mode 100644 index 2fd5777..0000000 --- a/drivers/net/smc911x.c +++ /dev/null @@ -1,680 +0,0 @@ -/* - * SMSC LAN9[12]1[567] Network driver - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -#ifdef CONFIG_DRIVER_SMC911X - -#include <command.h> -#include <net.h> -#include <miiphy.h> - -#define mdelay(n) udelay((n)*1000) - -#define __REG(x) (*((volatile u32 *)(x))) - -/* Below are the register offsets and bit definitions - * of the Lan911x memory space - */ -#define RX_DATA_FIFO __REG(CONFIG_DRIVER_SMC911X_BASE + 0x00) - -#define TX_DATA_FIFO __REG(CONFIG_DRIVER_SMC911X_BASE + 0x20) -#define TX_CMD_A_INT_ON_COMP (0x80000000) -#define TX_CMD_A_INT_BUF_END_ALGN (0x03000000) -#define TX_CMD_A_INT_4_BYTE_ALGN (0x00000000) -#define TX_CMD_A_INT_16_BYTE_ALGN (0x01000000) -#define TX_CMD_A_INT_32_BYTE_ALGN (0x02000000) -#define TX_CMD_A_INT_DATA_OFFSET (0x001F0000) -#define TX_CMD_A_INT_FIRST_SEG (0x00002000) -#define TX_CMD_A_INT_LAST_SEG (0x00001000) -#define TX_CMD_A_BUF_SIZE (0x000007FF) -#define TX_CMD_B_PKT_TAG (0xFFFF0000) -#define TX_CMD_B_ADD_CRC_DISABLE (0x00002000) -#define TX_CMD_B_DISABLE_PADDING (0x00001000) -#define TX_CMD_B_PKT_BYTE_LENGTH (0x000007FF) - -#define RX_STATUS_FIFO __REG(CONFIG_DRIVER_SMC911X_BASE + 0x40) -#define RX_STS_PKT_LEN (0x3FFF0000) -#define RX_STS_ES (0x00008000) -#define RX_STS_BCST (0x00002000) -#define RX_STS_LEN_ERR (0x00001000) -#define RX_STS_RUNT_ERR (0x00000800) -#define RX_STS_MCAST (0x00000400) -#define RX_STS_TOO_LONG (0x00000080) -#define RX_STS_COLL (0x00000040) -#define RX_STS_ETH_TYPE (0x00000020) -#define RX_STS_WDOG_TMT (0x00000010) -#define RX_STS_MII_ERR (0x00000008) -#define RX_STS_DRIBBLING (0x00000004) -#define RX_STS_CRC_ERR (0x00000002) -#define RX_STATUS_FIFO_PEEK __REG(CONFIG_DRIVER_SMC911X_BASE + 0x44) -#define TX_STATUS_FIFO __REG(CONFIG_DRIVER_SMC911X_BASE + 0x48) -#define TX_STS_TAG (0xFFFF0000) -#define TX_STS_ES (0x00008000) -#define TX_STS_LOC (0x00000800) -#define TX_STS_NO_CARR (0x00000400) -#define TX_STS_LATE_COLL (0x00000200) -#define TX_STS_MANY_COLL (0x00000100) -#define TX_STS_COLL_CNT (0x00000078) -#define TX_STS_MANY_DEFER (0x00000004) -#define TX_STS_UNDERRUN (0x00000002) -#define TX_STS_DEFERRED (0x00000001) -#define TX_STATUS_FIFO_PEEK __REG(CONFIG_DRIVER_SMC911X_BASE + 0x4C) -#define ID_REV __REG(CONFIG_DRIVER_SMC911X_BASE + 0x50) -#define ID_REV_CHIP_ID (0xFFFF0000) /* RO */ -#define ID_REV_REV_ID (0x0000FFFF) /* RO */ - -#define INT_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x54) -#define INT_CFG_INT_DEAS (0xFF000000) /* R/W */ -#define INT_CFG_INT_DEAS_CLR (0x00004000) -#define INT_CFG_INT_DEAS_STS (0x00002000) -#define INT_CFG_IRQ_INT (0x00001000) /* RO */ -#define INT_CFG_IRQ_EN (0x00000100) /* R/W */ -#define INT_CFG_IRQ_POL (0x00000010) /* R/W */ - /* Not Affected by SW Reset */ -#define INT_CFG_IRQ_TYPE (0x00000001) /* R/W */ - /* Not Affected by SW Reset */ - -#define INT_STS __REG(CONFIG_DRIVER_SMC911X_BASE + 0x58) -#define INT_STS_SW_INT (0x80000000) /* R/WC */ -#define INT_STS_TXSTOP_INT (0x02000000) /* R/WC */ -#define INT_STS_RXSTOP_INT (0x01000000) /* R/WC */ -#define INT_STS_RXDFH_INT (0x00800000) /* R/WC */ -#define INT_STS_RXDF_INT (0x00400000) /* R/WC */ -#define INT_STS_TX_IOC (0x00200000) /* R/WC */ -#define INT_STS_RXD_INT (0x00100000) /* R/WC */ -#define INT_STS_GPT_INT (0x00080000) /* R/WC */ -#define INT_STS_PHY_INT (0x00040000) /* RO */ -#define INT_STS_PME_INT (0x00020000) /* R/WC */ -#define INT_STS_TXSO (0x00010000) /* R/WC */ -#define INT_STS_RWT (0x00008000) /* R/WC */ -#define INT_STS_RXE (0x00004000) /* R/WC */ -#define INT_STS_TXE (0x00002000) /* R/WC */ -/*#define INT_STS_ERX (0x00001000)*/ /* R/WC */ -#define INT_STS_TDFU (0x00000800) /* R/WC */ -#define INT_STS_TDFO (0x00000400) /* R/WC */ -#define INT_STS_TDFA (0x00000200) /* R/WC */ -#define INT_STS_TSFF (0x00000100) /* R/WC */ -#define INT_STS_TSFL (0x00000080) /* R/WC */ -/*#define INT_STS_RXDF (0x00000040)*/ /* R/WC */ -#define INT_STS_RDFO (0x00000040) /* R/WC */ -#define INT_STS_RDFL (0x00000020) /* R/WC */ -#define INT_STS_RSFF (0x00000010) /* R/WC */ -#define INT_STS_RSFL (0x00000008) /* R/WC */ -#define INT_STS_GPIO2_INT (0x00000004) /* R/WC */ -#define INT_STS_GPIO1_INT (0x00000002) /* R/WC */ -#define INT_STS_GPIO0_INT (0x00000001) /* R/WC */ -#define INT_EN __REG(CONFIG_DRIVER_SMC911X_BASE + 0x5C) -#define INT_EN_SW_INT_EN (0x80000000) /* R/W */ -#define INT_EN_TXSTOP_INT_EN (0x02000000) /* R/W */ -#define INT_EN_RXSTOP_INT_EN (0x01000000) /* R/W */ -#define INT_EN_RXDFH_INT_EN (0x00800000) /* R/W */ -/*#define INT_EN_RXDF_INT_EN (0x00400000)*/ /* R/W */ -#define INT_EN_TIOC_INT_EN (0x00200000) /* R/W */ -#define INT_EN_RXD_INT_EN (0x00100000) /* R/W */ -#define INT_EN_GPT_INT_EN (0x00080000) /* R/W */ -#define INT_EN_PHY_INT_EN (0x00040000) /* R/W */ -#define INT_EN_PME_INT_EN (0x00020000) /* R/W */ -#define INT_EN_TXSO_EN (0x00010000) /* R/W */ -#define INT_EN_RWT_EN (0x00008000) /* R/W */ -#define INT_EN_RXE_EN (0x00004000) /* R/W */ -#define INT_EN_TXE_EN (0x00002000) /* R/W */ -/*#define INT_EN_ERX_EN (0x00001000)*/ /* R/W */ -#define INT_EN_TDFU_EN (0x00000800) /* R/W */ -#define INT_EN_TDFO_EN (0x00000400) /* R/W */ -#define INT_EN_TDFA_EN (0x00000200) /* R/W */ -#define INT_EN_TSFF_EN (0x00000100) /* R/W */ -#define INT_EN_TSFL_EN (0x00000080) /* R/W */ -/*#define INT_EN_RXDF_EN (0x00000040)*/ /* R/W */ -#define INT_EN_RDFO_EN (0x00000040) /* R/W */ -#define INT_EN_RDFL_EN (0x00000020) /* R/W */ -#define INT_EN_RSFF_EN (0x00000010) /* R/W */ -#define INT_EN_RSFL_EN (0x00000008) /* R/W */ -#define INT_EN_GPIO2_INT (0x00000004) /* R/W */ -#define INT_EN_GPIO1_INT (0x00000002) /* R/W */ -#define INT_EN_GPIO0_INT (0x00000001) /* R/W */ - -#define BYTE_TEST __REG(CONFIG_DRIVER_SMC911X_BASE + 0x64) -#define FIFO_INT __REG(CONFIG_DRIVER_SMC911X_BASE + 0x68) -#define FIFO_INT_TX_AVAIL_LEVEL (0xFF000000) /* R/W */ -#define FIFO_INT_TX_STS_LEVEL (0x00FF0000) /* R/W */ -#define FIFO_INT_RX_AVAIL_LEVEL (0x0000FF00) /* R/W */ -#define FIFO_INT_RX_STS_LEVEL (0x000000FF) /* R/W */ - -#define RX_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x6C) -#define RX_CFG_RX_END_ALGN (0xC0000000) /* R/W */ -#define RX_CFG_RX_END_ALGN4 (0x00000000) /* R/W */ -#define RX_CFG_RX_END_ALGN16 (0x40000000) /* R/W */ -#define RX_CFG_RX_END_ALGN32 (0x80000000) /* R/W */ -#define RX_CFG_RX_DMA_CNT (0x0FFF0000) /* R/W */ -#define RX_CFG_RX_DUMP (0x00008000) /* R/W */ -#define RX_CFG_RXDOFF (0x00001F00) /* R/W */ -/*#define RX_CFG_RXBAD (0x00000001)*/ /* R/W */ - -#define TX_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x70) -/*#define TX_CFG_TX_DMA_LVL (0xE0000000)*/ /* R/W */ -/*#define TX_CFG_TX_DMA_CNT (0x0FFF0000)*/ /* R/W */ - /* Self Clearing */ -#define TX_CFG_TXS_DUMP (0x00008000) - /* Self Clearing */ -#define TX_CFG_TXD_DUMP (0x00004000) - /* Self Clearing */ -#define TX_CFG_TXSAO (0x00000004) /* R/W */ -#define TX_CFG_TX_ON (0x00000002) /* R/W */ -#define TX_CFG_STOP_TX (0x00000001) - /* Self Clearing */ - -#define HW_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x74) -#define HW_CFG_TTM (0x00200000) /* R/W */ -#define HW_CFG_SF (0x00100000) /* R/W */ -#define HW_CFG_TX_FIF_SZ (0x000F0000) /* R/W */ -#define HW_CFG_TR (0x00003000) /* R/W */ -#define HW_CFG_PHY_CLK_SEL (0x00000060) /* R/W */ -#define HW_CFG_PHY_CLK_SEL_INT_PHY (0x00000000) /* R/W */ -#define HW_CFG_PHY_CLK_SEL_EXT_PHY (0x00000020) /* R/W */ -#define HW_CFG_PHY_CLK_SEL_CLK_DIS (0x00000040) /* R/W */ -#define HW_CFG_SMI_SEL (0x00000010) /* R/W */ -#define HW_CFG_EXT_PHY_DET (0x00000008) /* RO */ -#define HW_CFG_EXT_PHY_EN (0x00000004) /* R/W */ -#define HW_CFG_32_16_BIT_MODE (0x00000004) /* RO */ -#define HW_CFG_SRST_TO (0x00000002) /* RO */ -#define HW_CFG_SRST (0x00000001) - /* Self Clearing */ - -#define RX_DP_CTRL __REG(CONFIG_DRIVER_SMC911X_BASE + 0x78) -#define RX_DP_CTRL_RX_FFWD (0x80000000) /* R/W */ -#define RX_DP_CTRL_FFWD_BUSY (0x80000000) /* RO */ - -#define RX_FIFO_INF __REG(CONFIG_DRIVER_SMC911X_BASE + 0x7C) -#define RX_FIFO_INF_RXSUSED (0x00FF0000) /* RO */ -#define RX_FIFO_INF_RXDUSED (0x0000FFFF) /* RO */ - -#define TX_FIFO_INF __REG(CONFIG_DRIVER_SMC911X_BASE + 0x80) -#define TX_FIFO_INF_TSUSED (0x00FF0000) /* RO */ -#define TX_FIFO_INF_TDFREE (0x0000FFFF) /* RO */ - -#define PMT_CTRL __REG(CONFIG_DRIVER_SMC911X_BASE + 0x84) -#define PMT_CTRL_PM_MODE (0x00003000) - /* Self Clearing */ -#define PMT_CTRL_PHY_RST (0x00000400) - /* Self Clearing */ -#define PMT_CTRL_WOL_EN (0x00000200) /* R/W */ -#define PMT_CTRL_ED_EN (0x00000100) /* R/W */ -#define PMT_CTRL_PME_TYPE (0x00000040) /* R/W */ - /* Not Affected by SW Reset */ -#define PMT_CTRL_WUPS (0x00000030) /* R/WC */ -#define PMT_CTRL_WUPS_NOWAKE (0x00000000) /* R/WC */ -#define PMT_CTRL_WUPS_ED (0x00000010) /* R/WC */ -#define PMT_CTRL_WUPS_WOL (0x00000020) /* R/WC */ -#define PMT_CTRL_WUPS_MULTI (0x00000030) /* R/WC */ -#define PMT_CTRL_PME_IND (0x00000008) /* R/W */ -#define PMT_CTRL_PME_POL (0x00000004) /* R/W */ -#define PMT_CTRL_PME_EN (0x00000002) /* R/W */ - /* Not Affected by SW Reset */ -#define PMT_CTRL_READY (0x00000001) /* RO */ - -#define GPIO_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x88) -#define GPIO_CFG_LED3_EN (0x40000000) /* R/W */ -#define GPIO_CFG_LED2_EN (0x20000000) /* R/W */ -#define GPIO_CFG_LED1_EN (0x10000000) /* R/W */ -#define GPIO_CFG_GPIO2_INT_POL (0x04000000) /* R/W */ -#define GPIO_CFG_GPIO1_INT_POL (0x02000000) /* R/W */ -#define GPIO_CFG_GPIO0_INT_POL (0x01000000) /* R/W */ -#define GPIO_CFG_EEPR_EN (0x00700000) /* R/W */ -#define GPIO_CFG_GPIOBUF2 (0x00040000) /* R/W */ -#define GPIO_CFG_GPIOBUF1 (0x00020000) /* R/W */ -#define GPIO_CFG_GPIOBUF0 (0x00010000) /* R/W */ -#define GPIO_CFG_GPIODIR2 (0x00000400) /* R/W */ -#define GPIO_CFG_GPIODIR1 (0x00000200) /* R/W */ -#define GPIO_CFG_GPIODIR0 (0x00000100) /* R/W */ -#define GPIO_CFG_GPIOD4 (0x00000010) /* R/W */ -#define GPIO_CFG_GPIOD3 (0x00000008) /* R/W */ -#define GPIO_CFG_GPIOD2 (0x00000004) /* R/W */ -#define GPIO_CFG_GPIOD1 (0x00000002) /* R/W */ -#define GPIO_CFG_GPIOD0 (0x00000001) /* R/W */ - -#define GPT_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x8C) -#define GPT_CFG_TIMER_EN (0x20000000) /* R/W */ -#define GPT_CFG_GPT_LOAD (0x0000FFFF) /* R/W */ - -#define GPT_CNT __REG(CONFIG_DRIVER_SMC911X_BASE + 0x90) -#define GPT_CNT_GPT_CNT (0x0000FFFF) /* RO */ - -#define ENDIAN __REG(CONFIG_DRIVER_SMC911X_BASE + 0x98) -#define FREE_RUN __REG(CONFIG_DRIVER_SMC911X_BASE + 0x9C) -#define RX_DROP __REG(CONFIG_DRIVER_SMC911X_BASE + 0xA0) -#define MAC_CSR_CMD __REG(CONFIG_DRIVER_SMC911X_BASE + 0xA4) -#define MAC_CSR_CMD_CSR_BUSY (0x80000000) - /* Self Clearing */ -#define MAC_CSR_CMD_R_NOT_W (0x40000000) /* R/W */ -#define MAC_CSR_CMD_CSR_ADDR (0x000000FF) /* R/W */ - -#define MAC_CSR_DATA __REG(CONFIG_DRIVER_SMC911X_BASE + 0xA8) -#define AFC_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0xAC) -#define AFC_CFG_AFC_HI (0x00FF0000) /* R/W */ -#define AFC_CFG_AFC_LO (0x0000FF00) /* R/W */ -#define AFC_CFG_BACK_DUR (0x000000F0) /* R/W */ -#define AFC_CFG_FCMULT (0x00000008) /* R/W */ -#define AFC_CFG_FCBRD (0x00000004) /* R/W */ -#define AFC_CFG_FCADD (0x00000002) /* R/W */ -#define AFC_CFG_FCANY (0x00000001) /* R/W */ - -#define E2P_CMD __REG(CONFIG_DRIVER_SMC911X_BASE + 0xB0) -#define E2P_CMD_EPC_BUSY (0x80000000) - /* Self Clearing */ -#define E2P_CMD_EPC_CMD (0x70000000) /* R/W */ -#define E2P_CMD_EPC_CMD_READ (0x00000000) /* R/W */ -#define E2P_CMD_EPC_CMD_EWDS (0x10000000) /* R/W */ -#define E2P_CMD_EPC_CMD_EWEN (0x20000000) /* R/W */ -#define E2P_CMD_EPC_CMD_WRITE (0x30000000) /* R/W */ -#define E2P_CMD_EPC_CMD_WRAL (0x40000000) /* R/W */ -#define E2P_CMD_EPC_CMD_ERASE (0x50000000) /* R/W */ -#define E2P_CMD_EPC_CMD_ERAL (0x60000000) /* R/W */ -#define E2P_CMD_EPC_CMD_RELOAD (0x70000000) /* R/W */ -#define E2P_CMD_EPC_TIMEOUT (0x00000200) /* RO */ -#define E2P_CMD_MAC_ADDR_LOADED (0x00000100) /* RO */ -#define E2P_CMD_EPC_ADDR (0x000000FF) /* R/W */ - -#define E2P_DATA __REG(CONFIG_DRIVER_SMC911X_BASE + 0xB4) -#define E2P_DATA_EEPROM_DATA (0x000000FF) /* R/W */ -/* end of LAN register offsets and bit definitions */ - -/* MAC Control and Status registers */ -#define MAC_CR (0x01) /* R/W */ - -/* MAC_CR - MAC Control Register */ -#define MAC_CR_RXALL (0x80000000) -/* TODO: delete this bit? It is not described in the data sheet. */ -#define MAC_CR_HBDIS (0x10000000) -#define MAC_CR_RCVOWN (0x00800000) -#define MAC_CR_LOOPBK (0x00200000) -#define MAC_CR_FDPX (0x00100000) -#define MAC_CR_MCPAS (0x00080000) -#define MAC_CR_PRMS (0x00040000) -#define MAC_CR_INVFILT (0x00020000) -#define MAC_CR_PASSBAD (0x00010000) -#define MAC_CR_HFILT (0x00008000) -#define MAC_CR_HPFILT (0x00002000) -#define MAC_CR_LCOLL (0x00001000) -#define MAC_CR_BCAST (0x00000800) -#define MAC_CR_DISRTY (0x00000400) -#define MAC_CR_PADSTR (0x00000100) -#define MAC_CR_BOLMT_MASK (0x000000C0) -#define MAC_CR_DFCHK (0x00000020) -#define MAC_CR_TXEN (0x00000008) -#define MAC_CR_RXEN (0x00000004) - -#define ADDRH (0x02) /* R/W mask 0x0000FFFFUL */ -#define ADDRL (0x03) /* R/W mask 0xFFFFFFFFUL */ -#define HASHH (0x04) /* R/W */ -#define HASHL (0x05) /* R/W */ - -#define MII_ACC (0x06) /* R/W */ -#define MII_ACC_PHY_ADDR (0x0000F800) -#define MII_ACC_MIIRINDA (0x000007C0) -#define MII_ACC_MII_WRITE (0x00000002) -#define MII_ACC_MII_BUSY (0x00000001) - -#define MII_DATA (0x07) /* R/W mask 0x0000FFFFUL */ - -#define FLOW (0x08) /* R/W */ -#define FLOW_FCPT (0xFFFF0000) -#define FLOW_FCPASS (0x00000004) -#define FLOW_FCEN (0x00000002) -#define FLOW_FCBSY (0x00000001) - -#define VLAN1 (0x09) /* R/W mask 0x0000FFFFUL */ -#define VLAN1_VTI1 (0x0000ffff) - -#define VLAN2 (0x0A) /* R/W mask 0x0000FFFFUL */ -#define VLAN2_VTI2 (0x0000ffff) - -#define WUFF (0x0B) /* WO */ - -#define WUCSR (0x0C) /* R/W */ -#define WUCSR_GUE (0x00000200) -#define WUCSR_WUFR (0x00000040) -#define WUCSR_MPR (0x00000020) -#define WUCSR_WAKE_EN (0x00000004) -#define WUCSR_MPEN (0x00000002) - -/* Chip ID values */ -#define CHIP_9115 0x115 -#define CHIP_9116 0x116 -#define CHIP_9117 0x117 -#define CHIP_9118 0x118 -#define CHIP_9215 0x115a -#define CHIP_9216 0x116a -#define CHIP_9217 0x117a -#define CHIP_9218 0x118a - -struct chip_id { - u16 id; - char *name; -}; - -static const struct chip_id chip_ids[] = { - { CHIP_9115, "LAN9115" }, - { CHIP_9116, "LAN9116" }, - { CHIP_9117, "LAN9117" }, - { CHIP_9118, "LAN9118" }, - { CHIP_9215, "LAN9215" }, - { CHIP_9216, "LAN9216" }, - { CHIP_9217, "LAN9217" }, - { CHIP_9218, "LAN9218" }, - { 0, NULL }, -}; - -#define DRIVERNAME "smc911x" - -u32 smc911x_get_mac_csr(u8 reg) -{ - while (MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY); - MAC_CSR_CMD = MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg; - while (MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY); - - return MAC_CSR_DATA; -} - -void smc911x_set_mac_csr(u8 reg, u32 data) -{ - while (MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY); - MAC_CSR_DATA = data; - MAC_CSR_CMD = MAC_CSR_CMD_CSR_BUSY | reg; - while (MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY); } - -static int smx911x_handle_mac_address(bd_t *bd) -{ - unsigned long addrh, addrl; - unsigned char *m = bd->bi_enetaddr; - - /* if the environment has a valid mac address then use it */ - if ((m[0] | m[1] | m[2] | m[3] | m[4] | m[5])) { - addrl = m[0] | m[1] << 8 | m[2] << 16 | m[3] << 24; - addrh = m[4] | m[5] << 8; - smc911x_set_mac_csr(ADDRH, addrh); - smc911x_set_mac_csr(ADDRL, addrl); - } else { - /* if not, try to get one from the eeprom */ - addrh = smc911x_get_mac_csr(ADDRH); - addrl = smc911x_get_mac_csr(ADDRL); - - m[0] = (addrl) & 0xff; - m[1] = (addrl >> 8) & 0xff; - m[2] = (addrl >> 16) & 0xff; - m[3] = (addrl >> 24) & 0xff; - m[4] = (addrh) & 0xff; - m[5] = (addrh >> 8) & 0xff; - - /* we get 0xff when there is no eeprom connected */ - if ((m[0] & m[1] & m[2] & m[3] & m[4] & m[5]) == 0xff) { - printf(DRIVERNAME ": no valid mac address " - "in environment " - "and no eeprom found\n"); - return -1; - } - } - - printf(DRIVERNAME ": MAC %02x:%02x:%02x:%02x:%02x:%02x\n", - m[0], m[1], m[2], m[3], m[4], m[5]); - - return 0; -} - -static int smc911x_miiphy_read(u8 phy, u8 reg, u16 *val) -{ - while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY); - - smc911x_set_mac_csr(MII_ACC, phy << 11 | reg << 6 | MII_ACC_MII_BUSY); - - while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY); - - *val = smc911x_get_mac_csr(MII_DATA); - - return 0; -} - -static int smc911x_miiphy_write(u8 phy, u8 reg, u16 val) -{ - while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY); - - smc911x_set_mac_csr(MII_DATA, val); - smc911x_set_mac_csr(MII_ACC, - phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE); - - while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY); - return 0; -} - -static int smc911x_phy_reset(void) -{ - u32 reg; - - reg = PMT_CTRL; - reg &= ~0xfffff030; - reg |= PMT_CTRL_PHY_RST; - PMT_CTRL = reg; - - mdelay(100); - - return 0; -} - -static void smc911x_phy_configure(void) -{ - int timeout; - u16 status; - - smc911x_phy_reset(); - - smc911x_miiphy_write(1, PHY_BMCR, PHY_BMCR_RESET); - mdelay(1); - smc911x_miiphy_write(1, PHY_ANAR, 0x01e1); - smc911x_miiphy_write(1, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); - - timeout = 5000; - do { - mdelay(1); - if ((timeout--) == 0) - goto err_out; - - if (smc911x_miiphy_read(1, PHY_BMSR, &status) != 0) - goto err_out; - } while (!(status & PHY_BMSR_LS)); - - printf(DRIVERNAME ": phy initialized\n"); - - return; - -err_out: - printf(DRIVERNAME ": autonegotiation timed out\n"); } - -static void smc911x_reset(void) -{ - int timeout; - - /* Take out of PM setting first */ - if (PMT_CTRL & PMT_CTRL_READY) { - /* Write to the bytetest will take out of powerdown */ - BYTE_TEST = 0x0; - - timeout = 10; - - while (timeout-- && !(PMT_CTRL & PMT_CTRL_READY)) - udelay(10); - if (!timeout) { - printf(DRIVERNAME - ": timeout waiting for PM restore\n"); - return; - } - } - - /* Disable interrupts */ - INT_EN = 0; - - HW_CFG = HW_CFG_SRST; - - timeout = 1000; - while (timeout-- && E2P_CMD & E2P_CMD_EPC_BUSY) - udelay(10); - - if (!timeout) { - printf(DRIVERNAME ": reset timeout\n"); - return; - } - - /* Reset the FIFO level and flow control settings */ - smc911x_set_mac_csr(FLOW, FLOW_FCPT | FLOW_FCEN); - AFC_CFG = 0x0050287F; - - /* Set to LED outputs */ - GPIO_CFG = 0x70070000; -} - -static void smc911x_enable(void) -{ - /* Enable TX */ - HW_CFG = 8 << 16 | HW_CFG_SF; - - GPT_CFG = GPT_CFG_TIMER_EN | 10000; - - TX_CFG = TX_CFG_TX_ON; - - /* no padding to start of packets */ - RX_CFG = 0; - - smc911x_set_mac_csr(MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN | MAC_CR_HBDIS); - -} - -int eth_init(bd_t *bd) -{ - unsigned long val, i; - - printf(DRIVERNAME ": initializing\n"); - - val = BYTE_TEST; - if (val != 0x87654321) { - printf(DRIVERNAME ": Invalid chip endian 0x08%x\n", val); - goto err_out; - } - - val = ID_REV >> 16; - for (i = 0; chip_ids[i].id != 0; i++) { - if (chip_ids[i].id == val) - break; - } - if (!chip_ids[i].id) { - printf(DRIVERNAME ": Unknown chip ID %04x\n", val); - goto err_out; - } - - printf(DRIVERNAME ": detected %s controller\n", chip_ids[i].name); - - smc911x_reset(); - - /* Configure the PHY, initialize the link state */ - smc911x_phy_configure(); - - if (smx911x_handle_mac_address(bd)) - goto err_out; - - /* Turn on Tx + Rx */ - smc911x_enable(); - - return 0; - -err_out: - return -1; -} - -int eth_send(volatile void *packet, int length) -{ - u32 *data = (u32 *)packet; - u32 tmplen; - u32 status; - - TX_DATA_FIFO = TX_CMD_A_INT_FIRST_SEG | TX_CMD_A_INT_LAST_SEG | length; - TX_DATA_FIFO = length; - - tmplen = (length + 3) / 4; - - while (tmplen--) - TX_DATA_FIFO = *data++; - - /* wait for transmission */ - while (!((TX_FIFO_INF & TX_FIFO_INF_TSUSED) >> 16)); - - /* get status. Ignore 'no carrier' error, it has no meaning for - * full duplex operation - */ - status = TX_STATUS_FIFO & (TX_STS_LOC | TX_STS_LATE_COLL | - TX_STS_MANY_COLL | TX_STS_MANY_DEFER | TX_STS_UNDERRUN); - - if (!status) - return 0; - - printf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n", - status & TX_STS_LOC ? "TX_STS_LOC " : "", - status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "", - status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "", - status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "", - status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : ""); - - return -1; -} - -void eth_halt(void) -{ - smc911x_reset(); -} - -int eth_rx(void) -{ - u32 *data = (u32 *)NetRxPackets[0]; - u32 pktlen, tmplen; - u32 status; - - if ((RX_FIFO_INF & RX_FIFO_INF_RXSUSED) >> 16) { - status = RX_STATUS_FIFO; - pktlen = (status & RX_STS_PKT_LEN) >> 16; - - RX_CFG = 0; - - tmplen = (pktlen + 2 + 3) / 4; - while (tmplen--) - *data++ = RX_DATA_FIFO; - - if (status & RX_STS_ES) - printf(DRIVERNAME - ": dropped bad packet. Status: 0x%08x\n", - status); - else - NetReceive(NetRxPackets[0], pktlen); - } - - return 0; -} - -#endif /* CONFIG_DRIVER_SMC911X */ diff --git a/drivers/net/xilinx_emac.c b/drivers/net/xilinx_emac.c new file mode 100644 index 0000000..c7f1a2a --- /dev/null +++ b/drivers/net/xilinx_emac.c @@ -0,0 +1,462 @@ +/****************************************************************************** + * + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" + * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND + * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, + * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, + * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION + * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, + * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE + * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY + * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE + * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR + * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF + * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE. + * + * (C) Copyright 2007-2008 Michal Simek + * Michal SIMEK <monstr@monstr.eu> + * + * (c) Copyright 2003 Xilinx Inc. + * All rights reserved. + * + ******************************************************************************/ + +#include <config.h> +#include <common.h> +#include <net.h> +#include <asm/io.h> + +#include <asm/asm.h> + +#undef DEBUG + +typedef struct { + u32 regbaseaddress; /* Base address of registers */ + u32 databaseaddress; /* Base address of data for FIFOs */ +} xpacketfifov100b; + +typedef struct { + u32 baseaddress; /* Base address (of IPIF) */ + u32 isstarted; /* Device is currently started 0-no, 1-yes */ + xpacketfifov100b recvfifo; /* FIFO used to receive frames */ + xpacketfifov100b sendfifo; /* FIFO used to send frames */ +} xemac; + +#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */ +#define XIIF_V123B_RESET_MASK 0xAUL +#define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */ + +/* This constant is used with the Reset Register */ +#define XPF_RESET_FIFO_MASK 0x0000000A +#define XPF_COUNT_STATUS_REG_OFFSET 4UL + +/* These constants are used with the Occupancy/Vacancy Count Register. This + * register also contains FIFO status */ +#define XPF_COUNT_MASK 0x0000FFFF +#define XPF_DEADLOCK_MASK 0x20000000 + +/* Offset of the MAC registers from the IPIF base address */ +#define XEM_REG_OFFSET 0x1100UL + +/* + * Register offsets for the Ethernet MAC. Each register is 32 bits. + */ +#define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4) /* MAC Control */ +#define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC) /* Station addr, high */ +#define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */ +#define XEM_RPLR_OFFSET (XEM_REG_OFFSET + 0x1C) /* Rx packet length */ +#define XEM_TPLR_OFFSET (XEM_REG_OFFSET + 0x20) /* Tx packet length */ +#define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */ + +#define XEM_PFIFO_OFFSET 0x2000UL +/* Tx registers */ +#define XEM_PFIFO_TXREG_OFFSET (XEM_PFIFO_OFFSET + 0x0) +/* Rx registers */ +#define XEM_PFIFO_RXREG_OFFSET (XEM_PFIFO_OFFSET + 0x10) +/* Tx keyhole */ +#define XEM_PFIFO_TXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x100) +/* Rx keyhole */ +#define XEM_PFIFO_RXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x200) + +/* + * EMAC Interrupt Registers (Status and Enable) masks. These registers are + * part of the IPIF IP Interrupt registers + */ +/* A mask for all transmit interrupts, used in polled mode */ +#define XEM_EIR_XMIT_ALL_MASK (XEM_EIR_XMIT_DONE_MASK |\ + XEM_EIR_XMIT_ERROR_MASK | \ + XEM_EIR_XMIT_SFIFO_EMPTY_MASK |\ + XEM_EIR_XMIT_LFIFO_FULL_MASK) + +/* Xmit complete */ +#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL +/* Recv complete */ +#define XEM_EIR_RECV_DONE_MASK 0x00000002UL +/* Xmit error */ +#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL +/* Recv error */ +#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL +/* Xmit status fifo empty */ +#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL +/* Recv length fifo empty */ +#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL +/* Xmit length fifo full */ +#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL +/* Recv length fifo overrun */ +#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL +/* Recv length fifo underrun */ +#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL +/* Xmit status fifo overrun */ +#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL +/* Transmit status fifo underrun */ +#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL +/* Transmit length fifo overrun */ +#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL +/* Transmit length fifo underrun */ +#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL +/* Transmit pause pkt received */ +#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL + +/* + * EMAC Control Register (ECR) + */ +/* Full duplex mode */ +#define XEM_ECR_FULL_DUPLEX_MASK 0x80000000UL +/* Reset transmitter */ +#define XEM_ECR_XMIT_RESET_MASK 0x40000000UL +/* Enable transmitter */ +#define XEM_ECR_XMIT_ENABLE_MASK 0x20000000UL +/* Reset receiver */ +#define XEM_ECR_RECV_RESET_MASK 0x10000000UL +/* Enable receiver */ +#define XEM_ECR_RECV_ENABLE_MASK 0x08000000UL +/* Enable PHY */ +#define XEM_ECR_PHY_ENABLE_MASK 0x04000000UL +/* Enable xmit pad insert */ +#define XEM_ECR_XMIT_PAD_ENABLE_MASK 0x02000000UL +/* Enable xmit FCS insert */ +#define XEM_ECR_XMIT_FCS_ENABLE_MASK 0x01000000UL +/* Enable unicast addr */ +#define XEM_ECR_UNICAST_ENABLE_MASK 0x00020000UL +/* Enable broadcast addr */ +#define XEM_ECR_BROAD_ENABLE_MASK 0x00008000UL + +/* + * Transmit Status Register (TSR) + */ +/* Transmit excess deferral */ +#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL +/* Transmit late collision */ +#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL + +#define ENET_MAX_MTU PKTSIZE +#define ENET_ADDR_LENGTH 6 + +static unsigned int etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ + +static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 }; + +static xemac emac; + +void eth_halt(void) +{ + debug ("eth_halt\n"); +} + +int eth_init(bd_t * bis) +{ + u32 helpreg; + debug ("EMAC Initialization Started\n\r"); + + if (emac.isstarted) { + puts("Emac is started\n"); + return 0; + } + + memset (&emac, 0, sizeof (xemac)); + + emac.baseaddress = XILINX_EMAC_BASEADDR; + + /* Setting up FIFOs */ + emac.recvfifo.regbaseaddress = emac.baseaddress + + XEM_PFIFO_RXREG_OFFSET; + emac.recvfifo.databaseaddress = emac.baseaddress + + XEM_PFIFO_RXDATA_OFFSET; + out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK); + + emac.sendfifo.regbaseaddress = emac.baseaddress + + XEM_PFIFO_TXREG_OFFSET; + emac.sendfifo.databaseaddress = emac.baseaddress + + XEM_PFIFO_TXDATA_OFFSET; + out_be32 (emac.sendfifo.regbaseaddress, XPF_RESET_FIFO_MASK); + + /* Reset the entire IPIF */ + out_be32 (emac.baseaddress + XIIF_V123B_RESETR_OFFSET, + XIIF_V123B_RESET_MASK); + + /* Stopping EMAC for setting up MAC */ + helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET); + helpreg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); + out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg); + + if (!getenv("ethaddr")) { + memcpy(bis->bi_enetaddr, emacaddr, ENET_ADDR_LENGTH); + } + + /* Set the device station address high and low registers */ + helpreg = (bis->bi_enetaddr[0] << 8) | bis->bi_enetaddr[1]; + out_be32 (emac.baseaddress + XEM_SAH_OFFSET, helpreg); + helpreg = (bis->bi_enetaddr[2] << 24) | (bis->bi_enetaddr[3] << 16) | + (bis->bi_enetaddr[4] << 8) | bis->bi_enetaddr[5]; + out_be32 (emac.baseaddress + XEM_SAL_OFFSET, helpreg); + + helpreg = XEM_ECR_UNICAST_ENABLE_MASK | XEM_ECR_BROAD_ENABLE_MASK | + XEM_ECR_FULL_DUPLEX_MASK | XEM_ECR_XMIT_FCS_ENABLE_MASK | + XEM_ECR_XMIT_PAD_ENABLE_MASK | XEM_ECR_PHY_ENABLE_MASK; + out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg); + + emac.isstarted = 1; + + /* Enable the transmitter, and receiver */ + helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET); + helpreg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK); + helpreg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); + out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg); + + printf("EMAC Initialization complete\n\r"); + return 0; +} + +int eth_send(volatile void *ptr, int len) +{ + u32 intrstatus; + u32 xmitstatus; + u32 fifocount; + u32 wordcount; + u32 extrabytecount; + u32 *wordbuffer = (u32 *) ptr; + + if (len > ENET_MAX_MTU) + len = ENET_MAX_MTU; + + /* + * Check for overruns and underruns for the transmit status and length + * FIFOs and make sure the send packet FIFO is not deadlocked. + * Any of these conditions is bad enough that we do not want to + * continue. The upper layer software should reset the device to resolve + * the error. + */ + intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET); + if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | + XEM_EIR_XMIT_LFIFO_OVER_MASK)) { + debug ("Transmitting overrun error\n"); + return 0; + } else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | + XEM_EIR_XMIT_LFIFO_UNDER_MASK)) { + debug ("Transmitting underrun error\n"); + return 0; + } else if (in_be32 (emac.sendfifo.regbaseaddress + + XPF_COUNT_STATUS_REG_OFFSET) & XPF_DEADLOCK_MASK) { + debug ("Transmitting fifo error\n"); + return 0; + } + + /* + * Before writing to the data FIFO, make sure the length FIFO is not + * full. The data FIFO might not be full yet even though the length FIFO + * is. This avoids an overrun condition on the length FIFO and keeps the + * FIFOs in sync. + * + * Clear the latched LFIFO_FULL bit so next time around the most + * current status is represented + */ + if (intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) { + out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, + intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK); + debug ("Fifo is full\n"); + return 0; + } + + /* get the count of how many words may be inserted into the FIFO */ + fifocount = in_be32 (emac.sendfifo.regbaseaddress + + XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK; + wordcount = len >> 2; + extrabytecount = len & 0x3; + + if (fifocount < wordcount) { + debug ("Sending packet is larger then size of FIFO\n"); + return 0; + } + + for (fifocount = 0; fifocount < wordcount; fifocount++) { + out_be32 (emac.sendfifo.databaseaddress, wordbuffer[fifocount]); + } + if (extrabytecount > 0) { + u32 lastword = 0; + u8 *extrabytesbuffer = (u8 *) (wordbuffer + wordcount); + + if (extrabytecount == 1) { + lastword = extrabytesbuffer[0] << 24; + } else if (extrabytecount == 2) { + lastword = extrabytesbuffer[0] << 24 | + extrabytesbuffer[1] << 16; + } else if (extrabytecount == 3) { + lastword = extrabytesbuffer[0] << 24 | + extrabytesbuffer[1] << 16 | + extrabytesbuffer[2] << 8; + } + out_be32 (emac.sendfifo.databaseaddress, lastword); + } + + /* Loop on the MAC's status to wait for any pause to complete */ + intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET); + while ((intrstatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) { + intrstatus = in_be32 ((emac.baseaddress) + + XIIF_V123B_IISR_OFFSET); + /* Clear the pause status from the transmit status register */ + out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, + intrstatus & XEM_EIR_XMIT_PAUSE_MASK); + } + + /* + * Set the MAC's transmit packet length register to tell it to transmit + */ + out_be32 (emac.baseaddress + XEM_TPLR_OFFSET, len); + + /* + * Loop on the MAC's status to wait for the transmit to complete. + * The transmit status is in the FIFO when the XMIT_DONE bit is set. + */ + do { + intrstatus = in_be32 ((emac.baseaddress) + + XIIF_V123B_IISR_OFFSET); + } + while ((intrstatus & XEM_EIR_XMIT_DONE_MASK) == 0); + + xmitstatus = in_be32 (emac.baseaddress + XEM_TSR_OFFSET); + + if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | + XEM_EIR_XMIT_LFIFO_OVER_MASK)) { + debug ("Transmitting overrun error\n"); + return 0; + } else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | + XEM_EIR_XMIT_LFIFO_UNDER_MASK)) { + debug ("Transmitting underrun error\n"); + return 0; + } + + /* Clear the interrupt status register of transmit statuses */ + out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, + intrstatus & XEM_EIR_XMIT_ALL_MASK); + + /* + * Collision errors are stored in the transmit status register + * instead of the interrupt status register + */ + if ((xmitstatus & XEM_TSR_EXCESS_DEFERRAL_MASK) || + (xmitstatus & XEM_TSR_LATE_COLLISION_MASK)) { + debug ("Transmitting collision error\n"); + return 0; + } + return 1; +} + +int eth_rx(void) +{ + u32 pktlength; + u32 intrstatus; + u32 fifocount; + u32 wordcount; + u32 extrabytecount; + u32 lastword; + u8 *extrabytesbuffer; + + if (in_be32 (emac.recvfifo.regbaseaddress + XPF_COUNT_STATUS_REG_OFFSET) + & XPF_DEADLOCK_MASK) { + out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK); + debug ("Receiving FIFO deadlock\n"); + return 0; + } + + /* + * Get the interrupt status to know what happened (whether an error + * occurred and/or whether frames have been received successfully). + * When clearing the intr status register, clear only statuses that + * pertain to receive. + */ + intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET); + /* + * Before reading from the length FIFO, make sure the length FIFO is not + * empty. We could cause an underrun error if we try to read from an + * empty FIFO. + */ + if (!(intrstatus & XEM_EIR_RECV_DONE_MASK)) { + /* debug ("Receiving FIFO is empty\n"); */ + return 0; + } + + /* + * Determine, from the MAC, the length of the next packet available + * in the data FIFO (there should be a non-zero length here) + */ + pktlength = in_be32 (emac.baseaddress + XEM_RPLR_OFFSET); + if (!pktlength) { + return 0; + } + + /* + * Write the RECV_DONE bit in the status register to clear it. This bit + * indicates the RPLR is non-empty, and we know it's set at this point. + * We clear it so that subsequent entry into this routine will reflect + * the current status. This is done because the non-empty bit is latched + * in the IPIF, which means it may indicate a non-empty condition even + * though there is something in the FIFO. + */ + out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, + XEM_EIR_RECV_DONE_MASK); + + fifocount = in_be32 (emac.recvfifo.regbaseaddress + + XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK; + + if ((fifocount * 4) < pktlength) { + debug ("Receiving FIFO is smaller than packet size.\n"); + return 0; + } + + wordcount = pktlength >> 2; + extrabytecount = pktlength & 0x3; + + for (fifocount = 0; fifocount < wordcount; fifocount++) { + etherrxbuff[fifocount] = + in_be32 (emac.recvfifo.databaseaddress); + } + + /* + * if there are extra bytes to handle, read the last word from the FIFO + * and insert the extra bytes into the buffer + */ + if (extrabytecount > 0) { + extrabytesbuffer = (u8 *) (etherrxbuff + wordcount); + + lastword = in_be32 (emac.recvfifo.databaseaddress); + + /* + * one extra byte in the last word, put the byte into the next + * location of the buffer, bytes in a word of the FIFO are + * ordered from most significant byte to least + */ + if (extrabytecount == 1) { + extrabytesbuffer[0] = (u8) (lastword >> 24); + } else if (extrabytecount == 2) { + extrabytesbuffer[0] = (u8) (lastword >> 24); + extrabytesbuffer[1] = (u8) (lastword >> 16); + } else if (extrabytecount == 3) { + extrabytesbuffer[0] = (u8) (lastword >> 24); + extrabytesbuffer[1] = (u8) (lastword >> 16); + extrabytesbuffer[2] = (u8) (lastword >> 8); + } + } + NetReceive((uchar *)etherrxbuff, pktlength); + return 1; +} diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c new file mode 100644 index 0000000..9ba4096 --- /dev/null +++ b/drivers/net/xilinx_emaclite.c @@ -0,0 +1,351 @@ +/****************************************************************************** + * + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" + * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND + * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, + * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, + * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION + * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, + * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE + * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY + * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE + * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR + * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF + * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE. + * + * (C) Copyright 2007-2008 Michal Simek + * Michal SIMEK <monstr@monstr.eu> + * + * (c) Copyright 2003 Xilinx Inc. + * All rights reserved. + * + ******************************************************************************/ + +#include <common.h> +#include <net.h> +#include <config.h> +#include <asm/io.h> + +#undef DEBUG + +#define ENET_MAX_MTU PKTSIZE +#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN +#define ENET_ADDR_LENGTH 6 + +/* EmacLite constants */ +#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */ +#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */ +#define XEL_TSR_OFFSET 0x07FC /* Tx status */ +#define XEL_RSR_OFFSET 0x17FC /* Rx status */ +#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */ + +/* Xmit complete */ +#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL +/* Xmit interrupt enable bit */ +#define XEL_TSR_XMIT_IE_MASK 0x00000008UL +/* Buffer is active, SW bit only */ +#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL +/* Program the MAC address */ +#define XEL_TSR_PROGRAM_MASK 0x00000002UL +/* define for programming the MAC address into the EMAC Lite */ +#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK) + +/* Transmit packet length upper byte */ +#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL +/* Transmit packet length lower byte */ +#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL + +/* Recv complete */ +#define XEL_RSR_RECV_DONE_MASK 0x00000001UL +/* Recv interrupt enable bit */ +#define XEL_RSR_RECV_IE_MASK 0x00000008UL + +typedef struct { + unsigned int baseaddress; /* Base address for device (IPIF) */ + unsigned int nexttxbuffertouse; /* Next TX buffer to write to */ + unsigned int nextrxbuffertouse; /* Next RX buffer to read from */ + unsigned char deviceid; /* Unique ID of device - for future */ +} xemaclite; + +static xemaclite emaclite; + +static char etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ + +/* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/ +#ifdef CFG_ENV_IS_NOWHERE +static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 }; +#else +static u8 emacaddr[ENET_ADDR_LENGTH]; +#endif + +void xemaclite_alignedread (u32 * srcptr, void *destptr, unsigned bytecount) +{ + unsigned int i; + u32 alignbuffer; + u32 *to32ptr; + u32 *from32ptr; + u8 *to8ptr; + u8 *from8ptr; + + from32ptr = (u32 *) srcptr; + + /* Word aligned buffer, no correction needed. */ + to32ptr = (u32 *) destptr; + while (bytecount > 3) { + *to32ptr++ = *from32ptr++; + bytecount -= 4; + } + to8ptr = (u8 *) to32ptr; + + alignbuffer = *from32ptr++; + from8ptr = (u8 *) & alignbuffer; + + for (i = 0; i < bytecount; i++) { + *to8ptr++ = *from8ptr++; + } +} + +void xemaclite_alignedwrite (void *srcptr, u32 destptr, unsigned bytecount) +{ + unsigned i; + u32 alignbuffer; + u32 *to32ptr = (u32 *) destptr; + u32 *from32ptr; + u8 *to8ptr; + u8 *from8ptr; + + from32ptr = (u32 *) srcptr; + while (bytecount > 3) { + + *to32ptr++ = *from32ptr++; + bytecount -= 4; + } + + alignbuffer = 0; + to8ptr = (u8 *) & alignbuffer; + from8ptr = (u8 *) from32ptr; + + for (i = 0; i < bytecount; i++) { + *to8ptr++ = *from8ptr++; + } + + *to32ptr++ = alignbuffer; +} + +void eth_halt (void) +{ + debug ("eth_halt\n"); +} + +int eth_init (bd_t * bis) +{ + debug ("EmacLite Initialization Started\n"); + memset (&emaclite, 0, sizeof (xemaclite)); + emaclite.baseaddress = XILINX_EMACLITE_BASEADDR; + + if (!getenv("ethaddr")) { + memcpy(bis->bi_enetaddr, emacaddr, ENET_ADDR_LENGTH); + } + +/* + * TX - TX_PING & TX_PONG initialization + */ + /* Restart PING TX */ + out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0); + /* Copy MAC address */ + xemaclite_alignedwrite (bis->bi_enetaddr, + emaclite.baseaddress, ENET_ADDR_LENGTH); + /* Set the length */ + out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); + /* Update the MAC address in the EMAC Lite */ + out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR); + /* Wait for EMAC Lite to finish with the MAC address update */ + while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET) & + XEL_TSR_PROG_MAC_ADDR) != 0) ; + +#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG + /* The same operation with PONG TX */ + out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0); + xemaclite_alignedwrite (bis->bi_enetaddr, emaclite.baseaddress + + XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH); + out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); + out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, + XEL_TSR_PROG_MAC_ADDR); + while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + + XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) ; +#endif + +/* + * RX - RX_PING & RX_PONG initialization + */ + /* Write out the value to flush the RX buffer */ + out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK); +#ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG + out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET, + XEL_RSR_RECV_IE_MASK); +#endif + + debug ("EmacLite Initialization complete\n"); + return 0; +} + +int xemaclite_txbufferavailable (xemaclite * instanceptr) +{ + u32 reg; + u32 txpingbusy; + u32 txpongbusy; + /* + * Read the other buffer register + * and determine if the other buffer is available + */ + reg = in_be32 (instanceptr->baseaddress + + instanceptr->nexttxbuffertouse + 0); + txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) == + XEL_TSR_XMIT_BUSY_MASK); + + reg = in_be32 (instanceptr->baseaddress + + (instanceptr->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0); + txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) == + XEL_TSR_XMIT_BUSY_MASK); + + return (!(txpingbusy && txpongbusy)); +} + +int eth_send (volatile void *ptr, int len) { + + unsigned int reg; + unsigned int baseaddress; + + unsigned maxtry = 1000; + + if (len > ENET_MAX_MTU) + len = ENET_MAX_MTU; + + while (!xemaclite_txbufferavailable (&emaclite) && maxtry) { + udelay (10); + maxtry--; + } + + if (!maxtry) { + printf ("Error: Timeout waiting for ethernet TX buffer\n"); + /* Restart PING TX */ + out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0); +#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG + out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + + XEL_BUFFER_OFFSET, 0); +#endif + return 0; + } + + /* Determine the expected TX buffer address */ + baseaddress = (emaclite.baseaddress + emaclite.nexttxbuffertouse); + + /* Determine if the expected buffer address is empty */ + reg = in_be32 (baseaddress + XEL_TSR_OFFSET); + if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) + && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET) + & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { + +#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG + emaclite.nexttxbuffertouse ^= XEL_BUFFER_OFFSET; +#endif + debug ("Send packet from 0x%x\n", baseaddress); + /* Write the frame to the buffer */ + xemaclite_alignedwrite ((void *) ptr, baseaddress, len); + out_be32 (baseaddress + XEL_TPLR_OFFSET,(len & + (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO))); + reg = in_be32 (baseaddress + XEL_TSR_OFFSET); + reg |= XEL_TSR_XMIT_BUSY_MASK; + if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) { + reg |= XEL_TSR_XMIT_ACTIVE_MASK; + } + out_be32 (baseaddress + XEL_TSR_OFFSET, reg); + return 1; + } +#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG + /* Switch to second buffer */ + baseaddress ^= XEL_BUFFER_OFFSET; + /* Determine if the expected buffer address is empty */ + reg = in_be32 (baseaddress + XEL_TSR_OFFSET); + if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) + && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET) + & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { + debug ("Send packet from 0x%x\n", baseaddress); + /* Write the frame to the buffer */ + xemaclite_alignedwrite ((void *) ptr, baseaddress, len); + out_be32 (baseaddress + XEL_TPLR_OFFSET,(len & + (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO))); + reg = in_be32 (baseaddress + XEL_TSR_OFFSET); + reg |= XEL_TSR_XMIT_BUSY_MASK; + if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) { + reg |= XEL_TSR_XMIT_ACTIVE_MASK; + } + out_be32 (baseaddress + XEL_TSR_OFFSET, reg); + return 1; + } +#endif + puts ("Error while sending frame\n"); + return 0; +} + +int eth_rx (void) +{ + unsigned int length; + unsigned int reg; + unsigned int baseaddress; + + baseaddress = emaclite.baseaddress + emaclite.nextrxbuffertouse; + reg = in_be32 (baseaddress + XEL_RSR_OFFSET); + debug ("Testing data at address 0x%x\n", baseaddress); + if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { +#ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG + emaclite.nextrxbuffertouse ^= XEL_BUFFER_OFFSET; +#endif + } else { +#ifndef CONFIG_XILINX_EMACLITE_RX_PING_PONG + debug ("No data was available - address 0x%x\n", baseaddress); + return 0; +#else + baseaddress ^= XEL_BUFFER_OFFSET; + reg = in_be32 (baseaddress + XEL_RSR_OFFSET); + if ((reg & XEL_RSR_RECV_DONE_MASK) != + XEL_RSR_RECV_DONE_MASK) { + debug ("No data was available - address 0x%x\n", + baseaddress); + return 0; + } +#endif + } + /* Get the length of the frame that arrived */ + switch(((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC)) & + 0xFFFF0000 ) >> 16) { + case 0x806: + length = 42 + 20; /* FIXME size of ARP */ + debug ("ARP Packet\n"); + break; + case 0x800: + length = 14 + 14 + + (((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0x10)) & + 0xFFFF0000) >> 16); /* FIXME size of IP packet */ + debug ("IP Packet\n"); + break; + default: + debug ("Other Packet\n"); + length = ENET_MAX_MTU; + break; + } + + xemaclite_alignedread ((u32 *) (baseaddress + XEL_RXBUFF_OFFSET), + etherrxbuff, length); + + /* Acknowledge the frame */ + reg = in_be32 (baseaddress + XEL_RSR_OFFSET); + reg &= ~XEL_RSR_RECV_DONE_MASK; + out_be32 (baseaddress + XEL_RSR_OFFSET, reg); + + debug ("Packet receive from 0x%x, length %dB\n", baseaddress, length); + NetReceive ((uchar *) etherrxbuff, length); + return 1; + +} |