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-rw-r--r--drivers/Makefile6
-rw-r--r--drivers/cfi_flash.c1
-rw-r--r--drivers/keyboard.c6
-rw-r--r--drivers/mpc8xx_pcmcia.c304
-rw-r--r--drivers/pci.c2
-rw-r--r--drivers/pci_auto.c2
-rw-r--r--drivers/pci_indirect.c2
-rw-r--r--drivers/ps2ser.c55
-rw-r--r--drivers/pxa_pcmcia.c95
-rw-r--r--drivers/rpx_pcmcia.c73
-rw-r--r--drivers/s3c4510b_eth.c2
-rw-r--r--drivers/tqm8xx_pcmcia.c330
12 files changed, 865 insertions, 13 deletions
diff --git a/drivers/Makefile b/drivers/Makefile
index e6176ed..9be95c7 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -31,7 +31,7 @@ OBJS = 3c589.o 5701rls.o ali512x.o \
bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \
e1000.o eepro100.o \
- i8042.o i82365.o inca-ip_sw.o keyboard.o \
+ i8042.o inca-ip_sw.o keyboard.o \
lan91c96.o \
natsemi.o ne2000.o netarm_eth.o netconsole.o \
ns16550.o ns8382x.o ns87308.o ns7520_eth.o omap1510_i2c.o \
@@ -48,7 +48,9 @@ OBJS = 3c589.o 5701rls.o ali512x.o \
ti_pci1410a.o tigon3.o tsec.o \
usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \
videomodes.o w83c553f.o \
- ks8695eth.o
+ ks8695eth.o \
+ pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \
+ rpx_pcmcia.o
all: $(LIB)
diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c
index 2e37480..fd0a186 100644
--- a/drivers/cfi_flash.c
+++ b/drivers/cfi_flash.c
@@ -793,6 +793,7 @@ static int flash_status_check (flash_info_t * info, flash_sect_t sector,
flash_write_cmd (info, sector, 0, info->cmd_reset);
return ERR_TIMOUT;
}
+ udelay (1); /* also triggers watchdog */
}
return ERR_OK;
}
diff --git a/drivers/keyboard.c b/drivers/keyboard.c
index 1579095..9975202 100644
--- a/drivers/keyboard.c
+++ b/drivers/keyboard.c
@@ -33,7 +33,7 @@
#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */
-#ifdef CONFIG_MPC5xxx
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
int ps2ser_check(void);
#endif
@@ -75,7 +75,7 @@ static void kbd_put_queue(char data)
/* test if a character is in the queue */
static int kbd_testc(void)
{
-#ifdef CONFIG_MPC5xxx
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
/* no ISR is used, so received chars must be polled */
ps2ser_check();
#endif
@@ -90,7 +90,7 @@ static int kbd_getc(void)
{
char c;
while(in_pointer==out_pointer) {
-#ifdef CONFIG_MPC5xxx
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
/* no ISR is used, so received chars must be polled */
ps2ser_check();
#endif
diff --git a/drivers/mpc8xx_pcmcia.c b/drivers/mpc8xx_pcmcia.c
new file mode 100644
index 0000000..399a719
--- /dev/null
+++ b/drivers/mpc8xx_pcmcia.c
@@ -0,0 +1,304 @@
+#include <common.h>
+#if defined(CONFIG_8xx)
+#include <mpc8xx.h>
+#endif
+#include <pcmcia.h>
+
+#undef CONFIG_PCMCIA
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#define CONFIG_PCMCIA
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define CONFIG_PCMCIA
+#endif
+
+#if defined(CONFIG_8xx) && defined(CONFIG_PCMCIA)
+
+#if defined(CONFIG_IDE_8xx_PCCARD)
+extern int check_ide_device (int slot);
+#endif
+
+extern int pcmcia_hardware_enable (int slot);
+extern int pcmcia_voltage_set(int slot, int vcc, int vpp);
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+extern int pcmcia_hardware_disable(int slot);
+#endif
+
+static u_int m8xx_get_graycode(u_int size);
+#if 0 /* Disabled */
+static u_int m8xx_get_speed(u_int ns, u_int is_io);
+#endif
+
+/* look up table for pgcrx registers */
+u_int *pcmcia_pgcrx[2] = {
+ &((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcra,
+ &((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb,
+};
+
+/*
+ * Search this table to see if the windowsize is
+ * supported...
+ */
+
+#define M8XX_SIZES_NO 32
+
+static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] =
+{ 0x00000001, 0x00000002, 0x00000008, 0x00000004,
+ 0x00000080, 0x00000040, 0x00000010, 0x00000020,
+ 0x00008000, 0x00004000, 0x00001000, 0x00002000,
+ 0x00000100, 0x00000200, 0x00000800, 0x00000400,
+
+ 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x01000000, 0x02000000, 0xffffffff, 0x04000000,
+ 0x00010000, 0x00020000, 0x00080000, 0x00040000,
+ 0x00800000, 0x00400000, 0x00100000, 0x00200000 };
+
+
+/* -------------------------------------------------------------------- */
+
+#ifdef CONFIG_HMI10
+#define HMI10_FRAM_TIMING ( PCMCIA_SHT(2) \
+ | PCMCIA_SST(2) \
+ | PCMCIA_SL(4))
+#endif
+
+#if defined(CONFIG_LWMON) || defined(CONFIG_NSCU)
+#define CFG_PCMCIA_TIMING ( PCMCIA_SHT(9) \
+ | PCMCIA_SST(3) \
+ | PCMCIA_SL(12))
+#else
+#define CFG_PCMCIA_TIMING ( PCMCIA_SHT(2) \
+ | PCMCIA_SST(4) \
+ | PCMCIA_SL(9))
+#endif
+
+/* -------------------------------------------------------------------- */
+
+int pcmcia_on (void)
+{
+ u_long reg, base;
+ pcmcia_win_t *win;
+ u_int slotbit;
+ u_int rc, slot;
+ int i;
+
+ debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+ /* intialize the fixed memory windows */
+ win = (pcmcia_win_t *)(&((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pbr0);
+ base = CFG_PCMCIA_MEM_ADDR;
+
+ if((reg = m8xx_get_graycode(CFG_PCMCIA_MEM_SIZE)) == -1) {
+ printf ("Cannot set window size to 0x%08x\n",
+ CFG_PCMCIA_MEM_SIZE);
+ return (1);
+ }
+
+ slotbit = PCMCIA_SLOT_x;
+ for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {
+ win->br = base;
+
+#if (PCMCIA_SOCKETS_NO == 2)
+ if (i == 4) /* Another slot starting from win 4 */
+ slotbit = (slotbit ? PCMCIA_PSLOT_A : PCMCIA_PSLOT_B);
+#endif
+ switch (i) {
+#ifdef CONFIG_IDE_8xx_PCCARD
+ case 4:
+#ifdef CONFIG_HMI10
+ { /* map FRAM area */
+ win->or = ( PCMCIA_BSIZE_256K
+ | PCMCIA_PPS_8
+ | PCMCIA_PRS_ATTR
+ | slotbit
+ | PCMCIA_PV
+ | HMI10_FRAM_TIMING );
+ break;
+ }
+#endif
+ case 0: { /* map attribute memory */
+ win->or = ( PCMCIA_BSIZE_64M
+ | PCMCIA_PPS_8
+ | PCMCIA_PRS_ATTR
+ | slotbit
+ | PCMCIA_PV
+ | CFG_PCMCIA_TIMING );
+ break;
+ }
+ case 5:
+ case 1: { /* map I/O window for data reg */
+ win->or = ( PCMCIA_BSIZE_1K
+ | PCMCIA_PPS_16
+ | PCMCIA_PRS_IO
+ | slotbit
+ | PCMCIA_PV
+ | CFG_PCMCIA_TIMING );
+ break;
+ }
+ case 6:
+ case 2: { /* map I/O window for cmd/ctrl reg block */
+ win->or = ( PCMCIA_BSIZE_1K
+ | PCMCIA_PPS_8
+ | PCMCIA_PRS_IO
+ | slotbit
+ | PCMCIA_PV
+ | CFG_PCMCIA_TIMING );
+ break;
+ }
+#endif /* CONFIG_IDE_8xx_PCCARD */
+#ifdef CONFIG_HMI10
+ case 3: { /* map I/O window for 4xUART data/ctrl */
+ win->br += 0x40000;
+ win->or = ( PCMCIA_BSIZE_256K
+ | PCMCIA_PPS_8
+ | PCMCIA_PRS_IO
+ | slotbit
+ | PCMCIA_PV
+ | CFG_PCMCIA_TIMING );
+ break;
+ }
+#endif /* CONFIG_HMI10 */
+ default: /* set to not valid */
+ win->or = 0;
+ break;
+ }
+
+ debug ("MemWin %d: PBR 0x%08lX POR %08lX\n",
+ i, win->br, win->or);
+ base += CFG_PCMCIA_MEM_SIZE;
+ ++win;
+ }
+
+ for (i=0, rc=0, slot=_slot_; i<PCMCIA_SOCKETS_NO; i++, slot = !slot) {
+ /* turn off voltage */
+ if ((rc = pcmcia_voltage_set(slot, 0, 0)))
+ continue;
+
+ /* Enable external hardware */
+ if ((rc = pcmcia_hardware_enable(slot)))
+ continue;
+
+#ifdef CONFIG_IDE_8xx_PCCARD
+ if ((rc = check_ide_device(i)))
+ continue;
+#endif
+ }
+ return rc;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+int pcmcia_off (void)
+{
+ int i;
+ pcmcia_win_t *win;
+
+ printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+ /* clear interrupt state, and disable interrupts */
+ ((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pscr = PCMCIA_MASK(_slot_);
+ ((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_per &= ~PCMCIA_MASK(_slot_);
+
+ /* turn off interrupt and disable CxOE */
+ PCMCIA_PGCRX(_slot_) = __MY_PCMCIA_GCRX_CXOE;
+
+ /* turn off memory windows */
+ win = (pcmcia_win_t *)(&((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pbr0);
+
+ for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {
+ /* disable memory window */
+ win->or = 0;
+ ++win;
+ }
+
+ /* turn off voltage */
+ pcmcia_voltage_set(_slot_, 0, 0);
+
+ /* disable external hardware */
+ printf ("Shutdown and Poweroff " PCMCIA_SLOT_MSG "\n");
+ pcmcia_hardware_disable(_slot_);
+ return 0;
+}
+#endif /* CFG_CMD_PCMCIA */
+
+
+static u_int m8xx_get_graycode(u_int size)
+{
+ u_int k;
+
+ for (k = 0; k < M8XX_SIZES_NO; k++) {
+ if(m8xx_size_to_gray[k] == size)
+ break;
+ }
+
+ if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
+ k = -1;
+
+ return k;
+}
+
+#if 0
+
+#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
+
+/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
+ * SYPCR is write once only, therefore must the slowest memory be faster
+ * than the bus monitor or we will get a machine check due to the bus timeout.
+ */
+#undef PCMCIA_BMT_LIMIT
+#define PCMCIA_BMT_LIMIT (6*8)
+#endif
+
+static u_int m8xx_get_speed(u_int ns, u_int is_io)
+{
+ u_int reg, clocks, psst, psl, psht;
+
+ if(!ns) {
+
+ /*
+ * We get called with IO maps setup to 0ns
+ * if not specified by the user.
+ * They should be 255ns.
+ */
+
+ if(is_io)
+ ns = 255;
+ else
+ ns = 100; /* fast memory if 0 */
+ }
+
+ /*
+ * In PSST, PSL, PSHT fields we tell the controller
+ * timing parameters in CLKOUT clock cycles.
+ * CLKOUT is the same as GCLK2_50.
+ */
+
+ /* how we want to adjust the timing - in percent */
+
+#define ADJ 180 /* 80 % longer accesstime - to be sure */
+
+ clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000;
+ clocks = (clocks * ADJ) / (100*1000);
+
+ if(clocks >= PCMCIA_BMT_LIMIT) {
+ DEBUG(0, "Max access time limit reached\n");
+ clocks = PCMCIA_BMT_LIMIT-1;
+ }
+
+ psst = clocks / 7; /* setup time */
+ psht = clocks / 7; /* hold time */
+ psl = (clocks * 5) / 7; /* strobe length */
+
+ psst += clocks - (psst + psht + psl);
+
+ reg = psst << 12;
+ reg |= psl << 7;
+ reg |= psht << 16;
+
+ return reg;
+}
+#endif /* 0 */
+
+#endif /* CONFIG_8xx && CONFIG_PCMCIA */
diff --git a/drivers/pci.c b/drivers/pci.c
index 3c24b99..050582f 100644
--- a/drivers/pci.c
+++ b/drivers/pci.c
@@ -163,7 +163,7 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
#endif
for (bdf = PCI_BDF(bus,0,0);
-#ifdef CONFIG_ELPPC
+#if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
#else
bdf < PCI_BDF(bus+1,0,0);
diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c
index 9e921b2..9691675 100644
--- a/drivers/pci_auto.c
+++ b/drivers/pci_auto.c
@@ -187,7 +187,7 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
} else {
/* We don't support prefetchable memory for now, so disable */
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
- pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000);
+ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
}
if (pci_io) {
diff --git a/drivers/pci_indirect.c b/drivers/pci_indirect.c
index f0c4a1c..d7be081 100644
--- a/drivers/pci_indirect.c
+++ b/drivers/pci_indirect.c
@@ -60,7 +60,7 @@ indirect_##rw##_config_##size(struct pci_controller *hose, \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \
}
-#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
static int \
indirect_##rw##_config_##size(struct pci_controller *hose, \
diff --git a/drivers/ps2ser.c b/drivers/ps2ser.c
index 724fa40..4e304f7 100644
--- a/drivers/ps2ser.c
+++ b/drivers/ps2ser.c
@@ -20,6 +20,9 @@
#include <asm/io.h>
#include <asm/atomic.h>
#include <ps2mult.h>
+#if defined(CFG_NS16550) || defined(CONFIG_MPC85xx)
+#include <ns16550.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -45,13 +48,24 @@ DECLARE_GLOBAL_DATA_PTR;
#else
#error CONFIG_PS2SERIAL must be in 1 ... 6
#endif
-#endif /* CONFIG_MPC5xxx */
+
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+
+#if CONFIG_PS2SERIAL == 1
+#define COM_BASE (CFG_CCSRBAR+0x4500)
+#elif CONFIG_PS2SERIAL == 2
+#define COM_BASE (CFG_CCSRBAR+0x4600)
+#else
+#error CONFIG_PS2SERIAL must be in 1 ... 2
+#endif
+
+#endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */
static int ps2ser_getc_hw(void);
static void ps2ser_interrupt(void *dev_id);
extern struct serial_state rs_table[]; /* in serial.c */
-#ifndef CONFIG_MPC5xxx
+#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8555)
static struct serial_state *state;
#endif
@@ -106,7 +120,23 @@ int ps2ser_init(void)
return (0);
}
-#else /* !CONFIG_MPC5xxx */
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+int ps2ser_init(void)
+{
+ NS16550_t com_port = (NS16550_t)COM_BASE;
+
+ com_port->ier = 0x00;
+ com_port->lcr = LCR_BKSE | LCR_8N1;
+ com_port->dll = (CFG_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff;
+ com_port->dlm = ((CFG_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff;
+ com_port->lcr = LCR_8N1;
+ com_port->mcr = (MCR_DTR | MCR_RTS);
+ com_port->fcr = (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR);
+
+ return (0);
+}
+
+#else /* !CONFIG_MPC5xxx && !CONFIG_MPC8540 / other */
static inline unsigned int ps2ser_in(int offset)
{
@@ -150,12 +180,14 @@ int ps2ser_init(void)
return 0;
}
-#endif /* CONFIG_MPC5xxx */
+#endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */
void ps2ser_putc(int chr)
{
#ifdef CONFIG_MPC5xxx
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+ NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
#ifdef DEBUG
printf(">>>> 0x%02x\n", chr);
@@ -165,6 +197,9 @@ void ps2ser_putc(int chr)
while (!(psc->psc_status & PSC_SR_TXRDY));
psc->psc_buffer_8 = chr;
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+ while ((com_port->lsr & LSR_THRE) == 0);
+ com_port->thr = chr;
#else
while (!(ps2ser_in(UART_LSR) & UART_LSR_THRE));
@@ -176,6 +211,8 @@ static int ps2ser_getc_hw(void)
{
#ifdef CONFIG_MPC5xxx
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+ NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
int res = -1;
@@ -183,6 +220,10 @@ static int ps2ser_getc_hw(void)
if (psc->psc_status & PSC_SR_RXRDY) {
res = (psc->psc_buffer_8);
}
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+ if (com_port->lsr & LSR_DR) {
+ res = com_port->rbr;
+ }
#else
if (ps2ser_in(UART_LSR) & UART_LSR_DR) {
res = (ps2ser_in(UART_RX));
@@ -238,6 +279,8 @@ static void ps2ser_interrupt(void *dev_id)
{
#ifdef CONFIG_MPC5xxx
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+ NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
int chr;
int status;
@@ -246,6 +289,8 @@ static void ps2ser_interrupt(void *dev_id)
chr = ps2ser_getc_hw();
#ifdef CONFIG_MPC5xxx
status = psc->psc_status;
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+ status = com_port->lsr;
#else
status = ps2ser_in(UART_IIR);
#endif
@@ -260,6 +305,8 @@ static void ps2ser_interrupt(void *dev_id)
}
#ifdef CONFIG_MPC5xxx
} while (status & PSC_SR_RXRDY);
+#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+ } while (status & LSR_DR);
#else
} while (status & UART_IIR_RDI);
#endif
diff --git a/drivers/pxa_pcmcia.c b/drivers/pxa_pcmcia.c
new file mode 100644
index 0000000..d9d38bb
--- /dev/null
+++ b/drivers/pxa_pcmcia.c
@@ -0,0 +1,95 @@
+#include <common.h>
+#include <config.h>
+
+#ifdef CONFIG_PXA_PCMCIA
+
+#include <pcmcia.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
+
+static inline void msWait(unsigned msVal)
+{
+ udelay(msVal*1000);
+}
+
+int pcmcia_on (void)
+{
+ unsigned int reg_arr[] = {
+ 0x48000028, CFG_MCMEM0_VAL,
+ 0x4800002c, CFG_MCMEM1_VAL,
+ 0x48000030, CFG_MCATT0_VAL,
+ 0x48000034, CFG_MCATT1_VAL,
+ 0x48000038, CFG_MCIO0_VAL,
+ 0x4800003c, CFG_MCIO1_VAL,
+
+ 0, 0
+ };
+ int i, rc;
+
+#ifdef CONFIG_EXADRON1
+ int cardDetect;
+ volatile unsigned int *v_pBCRReg =
+ (volatile unsigned int *) 0x08000000;
+#endif
+
+ debug ("%s\n", __FUNCTION__);
+
+ i = 0;
+ while (reg_arr[i])
+ *((volatile unsigned int *) reg_arr[i++]) |= reg_arr[i++];
+ udelay (1000);
+
+ debug ("%s: programmed mem controller \n", __FUNCTION__);
+
+#ifdef CONFIG_EXADRON1
+
+/*define useful BCR masks */
+#define BCR_CF_INIT_VAL 0x00007230
+#define BCR_CF_PWRON_BUSOFF_RESETOFF_VAL 0x00007231
+#define BCR_CF_PWRON_BUSOFF_RESETON_VAL 0x00007233
+#define BCR_CF_PWRON_BUSON_RESETON_VAL 0x00007213
+#define BCR_CF_PWRON_BUSON_RESETOFF_VAL 0x00007211
+
+ /* we see from the GPIO bit if the card is present */
+ cardDetect = !(GPLR0 & GPIO_bit (14));
+
+ if (cardDetect) {
+ printf ("No PCMCIA card found!\n");
+ }
+
+ /* reset the card via the BCR line */
+ *v_pBCRReg = (unsigned) BCR_CF_INIT_VAL;
+ msWait (500);
+
+ *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSOFF_RESETOFF_VAL;
+ msWait (500);
+
+ *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSOFF_RESETON_VAL;
+ msWait (500);
+
+ *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSON_RESETON_VAL;
+ msWait (500);
+
+ *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSON_RESETOFF_VAL;
+ msWait (1500);
+
+ /* enable address bus */
+ GPCR1 = 0x01;
+ /* and the first CF slot */
+ MECR = 0x00000002;
+
+#endif /* EXADRON 1 */
+
+ rc = check_ide_device (0); /* use just slot 0 */
+
+ return rc;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+int pcmcia_off (void)
+{
+ return 0;
+}
+#endif
+
+#endif /* CONFIG_PXA_PCMCIA */
diff --git a/drivers/rpx_pcmcia.c b/drivers/rpx_pcmcia.c
new file mode 100644
index 0000000..2a0a9e0
--- /dev/null
+++ b/drivers/rpx_pcmcia.c
@@ -0,0 +1,73 @@
+/* -------------------------------------------------------------------- */
+/* RPX Boards from Embedded Planet */
+/* -------------------------------------------------------------------- */
+#include <common.h>
+#ifdef CONFIG_8xx
+#include <mpc8xx.h>
+#endif
+#include <pcmcia.h>
+
+#undef CONFIG_PCMCIA
+
+#if CONFIG_COMMANDS & CFG_CMD_PCMCIA
+#define CONFIG_PCMCIA
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define CONFIG_PCMCIA
+#endif
+
+#if defined(CONFIG_PCMCIA) \
+ && (defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE))
+
+#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+ u_long reg = 0;
+
+ switch(vcc) {
+ case 0: break;
+ case 33: reg |= BCSR1_PCVCTL4; break;
+ case 50: reg |= BCSR1_PCVCTL5; break;
+ default: return 1;
+ }
+
+ switch(vpp) {
+ case 0: break;
+ case 33:
+ case 50:
+ if(vcc == vpp)
+ reg |= BCSR1_PCVCTL6;
+ else
+ return 1;
+ break;
+ case 120:
+ reg |= BCSR1_PCVCTL7;
+ default: return 1;
+ }
+
+ /* first, turn off all power */
+ *((uint *)RPX_CSR_ADDR) &= ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5
+ | BCSR1_PCVCTL6 | BCSR1_PCVCTL7);
+
+ /* enable new powersettings */
+ *((uint *)RPX_CSR_ADDR) |= reg;
+
+ return 0;
+}
+
+int pcmcia_hardware_enable (int slot)
+{
+ return 0; /* No hardware to enable */
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+static int pcmcia_hardware_disable(int slot)
+{
+ return 0; /* No hardware to disable */
+}
+#endif /* CONFIG_COMMANDS & CFG_CMD_PCMCIA */
+
+
+#endif /* CONFIG_PCMCIA && (CONFIG_RPXCLASSIC || CONFIG_RPXLITE) */
diff --git a/drivers/s3c4510b_eth.c b/drivers/s3c4510b_eth.c
index 0274dd2..48901aa 100644
--- a/drivers/s3c4510b_eth.c
+++ b/drivers/s3c4510b_eth.c
@@ -175,7 +175,7 @@ s32 eth_send(volatile void *packet, s32 length)
}
/* copy user data into frame data pointer */
- memcpy((void *)eth->m_curTX_FD->m_frameDataPtr.bf.dataPtr,
+ memcpy((void *)(eth->m_curTX_FD->m_frameDataPtr.bf.dataPtr),
(void *)packet,
length);
diff --git a/drivers/tqm8xx_pcmcia.c b/drivers/tqm8xx_pcmcia.c
new file mode 100644
index 0000000..a0f53cd
--- /dev/null
+++ b/drivers/tqm8xx_pcmcia.c
@@ -0,0 +1,330 @@
+/* -------------------------------------------------------------------- */
+/* TQM8xxL Boards by TQ Components */
+/* SC8xx Boards by SinoVee Microsystems */
+/* -------------------------------------------------------------------- */
+#include <common.h>
+#ifdef CONFIG_8xx
+#include <mpc8xx.h>
+#endif
+#include <pcmcia.h>
+
+#undef CONFIG_PCMCIA
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#define CONFIG_PCMCIA
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#define CONFIG_PCMCIA
+#endif
+
+#if defined(CONFIG_PCMCIA) \
+ && (defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx))
+
+#if defined(CONFIG_VIRTLAB2)
+#define PCMCIA_BOARD_MSG "Virtlab2"
+#elif defined(CONFIG_TQM8xxL)
+#define PCMCIA_BOARD_MSG "TQM8xxL"
+#elif defined(CONFIG_SVM_SC8xx)
+#define PCMCIA_BOARD_MSG "SC8xx"
+#endif
+
+#if defined(CONFIG_NSCU)
+
+#define power_config(slot) do {} while (0)
+#define power_off(slot) do {} while (0)
+#define power_on_5_0(slot) do {} while (0)
+#define power_on_3_3(slot) do {} while (0)
+
+#elif defined(CONFIG_HMI10)
+
+static inline void power_config(int slot)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ /*
+ * Configure Port B pins for
+ * 5 Volts Enable and 3 Volts enable
+ */
+ immap->im_cpm.cp_pbpar &= ~(0x00000300);
+}
+
+static inline void power_off(int slot)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ /* remove all power */
+ immap->im_cpm.cp_pbdat |= 0x00000300;
+}
+
+static inline void power_on_5_0(int slot)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ immap->im_cpm.cp_pbdat &= ~(0x0000100);
+ immap->im_cpm.cp_pbdir |= 0x00000300;
+}
+
+static inline void power_on_3_3(int slot)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ immap->im_cpm.cp_pbdat &= ~(0x0000200);
+ immap->im_cpm.cp_pbdir |= 0x00000300;
+}
+
+#elif defined(CONFIG_VIRTLAB2)
+
+#define power_config(slot) do {} while (0)
+static inline void power_off(int slot)
+{
+ volatile unsigned char *powerctl =
+ (volatile unsigned char *)PCMCIA_CTRL;
+ *powerctl = 0;
+}
+
+static inline void power_on_5_0(int slot)
+{
+ volatile unsigned char *powerctl =
+ (volatile unsigned char *)PCMCIA_CTRL;
+ *powerctl = 2; /* Enable 5V Vccout */
+}
+
+static inline void power_on_3_3(int slot)
+{
+ volatile unsigned char *powerctl =
+ (volatile unsigned char *)PCMCIA_CTRL;
+ *powerctl = 1; /* Enable 3.3V Vccout */
+}
+
+#else
+
+static inline void power_config(int slot)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ /*
+ * Configure Port C pins for
+ * 5 Volts Enable and 3 Volts enable
+ */
+ immap->im_ioport.iop_pcpar &= ~(0x0002 | 0x0004);
+ immap->im_ioport.iop_pcso &= ~(0x0002 | 0x0004);
+}
+
+static inline void power_off(int slot)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004);
+}
+
+static inline void power_on_5_0(int slot)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ immap->im_ioport.iop_pcdat |= 0x0004;
+ immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004);
+}
+
+static inline void power_on_3_3(int slot)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ immap->im_ioport.iop_pcdat |= 0x0002;
+ immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004);
+}
+
+#endif
+
+#ifdef CONFIG_HMI10
+static inline int check_card_is_absent(int slot)
+{
+ volatile pcmconf8xx_t *pcmp =
+ (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ return pcmp->pcmc_pipr & (0x10000000 >> (slot << 4));
+}
+#else
+static inline int check_card_is_absent(int slot)
+{
+ volatile pcmconf8xx_t *pcmp =
+ (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ return pcmp->pcmc_pipr & (0x18000000 >> (slot << 4));
+}
+#endif
+
+#ifdef NSCU_OE_INV
+#define NSCU_GCRX_CXOE 0
+#else
+#define NSCU_GCRX_CXOE __MY_PCMCIA_GCRX_CXOE
+#endif
+
+int pcmcia_hardware_enable(int slot)
+{
+ volatile pcmconf8xx_t *pcmp =
+ (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+ volatile sysconf8xx_t *sysp =
+ (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
+ uint reg, mask;
+
+ debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+ udelay(10000);
+
+ /*
+ * Configure SIUMCR to enable PCMCIA port B
+ * (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
+ */
+ sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
+
+ /* clear interrupt state, and disable interrupts */
+ pcmp->pcmc_pscr = PCMCIA_MASK(slot);
+ pcmp->pcmc_per &= ~PCMCIA_MASK(slot);
+
+ /*
+ * Disable interrupts, DMA, and PCMCIA buffers
+ * (isolate the interface) and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = 0;
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= NSCU_GCRX_CXOE;
+
+ PCMCIA_PGCRX(slot) = reg;
+ udelay(500);
+
+ power_config(slot);
+ power_off(slot);
+
+ /*
+ * Make sure there is a card in the slot, then configure the interface.
+ */
+ udelay(10000);
+ debug ("[%d] %s: PIPR(%p)=0x%x\n", __LINE__,__FUNCTION__,
+ &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
+
+ if (check_card_is_absent(slot)) {
+ printf (" No Card found\n");
+ return (1);
+ }
+
+ /*
+ * Power On.
+ */
+ mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
+ reg = pcmp->pcmc_pipr;
+ debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
+ reg,
+ (reg&PCMCIA_VS1(slot))?"n":"ff",
+ (reg&PCMCIA_VS2(slot))?"n":"ff");
+
+ if ((reg & mask) == mask) {
+ power_on_5_0(slot);
+ puts (" 5.0V card found: ");
+ } else {
+ power_on_3_3(slot);
+ puts (" 3.3V card found: ");
+ }
+
+#if 0
+ /* VCC switch error flag, PCMCIA slot INPACK_ pin */
+ cp->cp_pbdir &= ~(0x0020 | 0x0010);
+ cp->cp_pbpar &= ~(0x0020 | 0x0010);
+ udelay(500000);
+#endif
+
+ udelay(1000);
+ debug ("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(slot);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ reg &= ~NSCU_GCRX_CXOE;
+
+ PCMCIA_PGCRX(slot) = reg;
+
+ udelay(250000); /* some cards need >150 ms to come up :-( */
+
+ debug ("# hardware_enable done\n");
+
+ return (0);
+}
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+int pcmcia_hardware_disable(int slot)
+{
+ u_long reg;
+
+ debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
+
+
+ /* remove all power */
+ power_off(slot);
+
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = 0;
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= NSCU_GCRX_CXOE; /* active low */
+
+ PCMCIA_PGCRX(slot) = reg;
+
+ udelay(10000);
+
+ return (0);
+}
+#endif /* CFG_CMD_PCMCIA */
+
+int pcmcia_voltage_set(int slot, int vcc, int vpp)
+{
+#ifndef CONFIG_NSCU
+ u_long reg;
+# ifdef DEBUG
+ volatile pcmconf8xx_t *pcmp =
+ (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+# endif
+
+ debug ("voltage_set: " PCMCIA_BOARD_MSG
+ " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
+ 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
+
+ /*
+ * Disable PCMCIA buffers (isolate the interface)
+ * and assert RESET signal
+ */
+ debug ("Disable PCMCIA buffers and assert RESET\n");
+ reg = PCMCIA_PGCRX(slot);
+ reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
+ reg |= NSCU_GCRX_CXOE; /* active low */
+
+ PCMCIA_PGCRX(slot) = reg;
+ udelay(500);
+
+ debug ("PCMCIA power OFF\n");
+ power_config(slot);
+ power_off(slot);
+
+ switch(vcc) {
+ case 0: break;
+ case 33: power_on_3_3(slot); break;
+ case 50: power_on_5_0(slot); break;
+ default: goto done;
+ }
+
+ /* Checking supported voltages */
+
+ debug("PIPR: 0x%x --> %s\n", pcmp->pcmc_pipr,
+ (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
+
+ if (vcc)
+ debug("PCMCIA powered at %sV\n", (vcc == 50) ? "5.0" : "3.3");
+ else
+ debug("PCMCIA powered down\n");
+
+done:
+ debug("Enable PCMCIA buffers and stop RESET\n");
+ reg = PCMCIA_PGCRX(slot);
+ reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
+ reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
+ reg &= ~NSCU_GCRX_CXOE; /* active low */
+
+ PCMCIA_PGCRX(slot) = reg;
+ udelay(500);
+
+ debug("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", slot+'A');
+#endif /* CONFIG_NSCU */
+ return (0);
+}
+
+#endif /* CONFIG_PCMCIA && (CONFIG_TQM8xxL || CONFIG_SVM_SC8xx) */
generated by cgit v1.1 at 2024-12-12 10:54:03 +0000