diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/Makefile | 14 | ||||
| -rw-r--r-- | drivers/cfb_console.c | 1 | ||||
| -rw-r--r-- | drivers/dm9000x.c | 590 | ||||
| -rw-r--r-- | drivers/dm9000x.h | 119 | ||||
| -rw-r--r-- | drivers/serial_imx.c | 201 |
5 files changed, 917 insertions, 8 deletions
diff --git a/drivers/Makefile b/drivers/Makefile index 11738b9..afca70e 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -29,23 +29,23 @@ LIB = libdrivers.a OBJS = 3c589.o 5701rls.o ali512x.o \ bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \ - cs8900.o ct69000.o dataflash.o dc2114x.o \ + cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \ e1000.o eepro100.o \ i8042.o i82365.o inca-ip_sw.o keyboard.o \ lan91c96.o natsemi.o netarm_eth.o \ - ns16550.o ns8382x.o ns87308.o \ + ns16550.o ns8382x.o ns87308.o omap1510_i2c.o \ pci.o pci_auto.o pci_indirect.o \ pcnet.o plb2800_eth.o \ ps2ser.o ps2mult.o pc_keyb.o \ rtl8019.o rtl8139.o rtl8169.o \ s3c24x0_i2c.o s3c4510b_eth.o s3c4510b_uart.o \ sed13806.o sed156x.o \ - serial.o serial_max3100.o serial_pl010.o serial_pl011.o \ - serial_xuartlite.o sl811_usb.o \ - smc91111.o smiLynxEM.o status_led.o sym53c8xx.o \ - ti_pci1410a.o tigon3.o w83c553f.o omap1510_i2c.o \ + serial.o serial_imx.o serial_max3100.o \ + serial_pl010.o serial_pl011.o serial_xuartlite.o \ + sl811_usb.o smc91111.o smiLynxEM.o status_led.o sym53c8xx.o \ + ti_pci1410a.o tigon3.o \ usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \ - videomodes.o + videomodes.o w83c553f.o all: $(LIB) diff --git a/drivers/cfb_console.c b/drivers/cfb_console.c index 6a8df79..3d26ae2 100644 --- a/drivers/cfb_console.c +++ b/drivers/cfb_console.c @@ -1169,7 +1169,6 @@ int drv_video_init (void) { int skip_dev_init; device_t console_dev; - char *penv; skip_dev_init = 0; diff --git a/drivers/dm9000x.c b/drivers/dm9000x.c new file mode 100644 index 0000000..0e475d4 --- /dev/null +++ b/drivers/dm9000x.c @@ -0,0 +1,590 @@ +/* + dm9000.c: Version 1.2 12/15/2003 + + A Davicom DM9000 ISA NIC fast Ethernet driver for Linux. + Copyright (C) 1997 Sten Wang + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2 + of the License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. + +V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match + 06/22/2001 Support DM9801 progrmming + E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000 + E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200 + R17 = (R17 & 0xfff0) | NF + 3 + E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200 + R17 = (R17 & 0xfff0) | NF + +v1.00 modify by simon 2001.9.5 + change for kernel 2.4.x + +v1.1 11/09/2001 fix force mode bug + +v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>: + Fixed phy reset. + Added tx/rx 32 bit mode. + Cleaned up for kernel merge. + +-------------------------------------- + + 12/15/2003 Initial port to u-boot by Sascha Hauer <saschahauer@web.de> + +TODO: Homerun NIC and longrun NIC are not functional, only internal at the + moment. +*/ + +#include <common.h> +#include <command.h> +#include <net.h> +#include <asm/io.h> + +#ifdef CONFIG_DRIVER_DM9000 + +#include "dm9000x.h" + +/* Board/System/Debug information/definition ---------------- */ + +#define DM9801_NOISE_FLOOR 0x08 +#define DM9802_NOISE_FLOOR 0x05 + +/* #define CONFIG_DM9000_DEBUG */ + +#ifdef CONFIG_DM9000_DEBUG +#define DM9000_DBG(fmt,args...) printf(fmt ,##args) +#else /* */ +#define DM9000_DBG(fmt,args...) +#endif /* */ +enum DM9000_PHY_mode { DM9000_10MHD = 0, DM9000_100MHD = + 1, DM9000_10MFD = 4, DM9000_100MFD = 5, DM9000_AUTO = + 8, DM9000_1M_HPNA = 0x10 +}; +enum DM9000_NIC_TYPE { FASTETHER_NIC = 0, HOMERUN_NIC = 1, LONGRUN_NIC = 2 +}; + +/* Structure/enum declaration ------------------------------- */ +typedef struct board_info { + u32 runt_length_counter; /* counter: RX length < 64byte */ + u32 long_length_counter; /* counter: RX length > 1514byte */ + u32 reset_counter; /* counter: RESET */ + u32 reset_tx_timeout; /* RESET caused by TX Timeout */ + u32 reset_rx_status; /* RESET caused by RX Statsus wrong */ + u16 tx_pkt_cnt; + u16 queue_start_addr; + u16 dbug_cnt; + u8 phy_addr; + u8 device_wait_reset; /* device state */ + u8 nic_type; /* NIC type */ + unsigned char srom[128]; +} board_info_t; +board_info_t dmfe_info; + +/* For module input parameter */ +static int media_mode = DM9000_AUTO; +static u8 nfloor = 0; + +/* function declaration ------------------------------------- */ +int eth_init(bd_t * bd); +int eth_send(volatile void *, int); +int eth_rx(void); +void eth_halt(void); +static int dm9000_probe(void); +static u16 phy_read(int); +static void phy_write(int, u16); +static u16 read_srom_word(int); +static u8 DM9000_ior(int); +static void DM9000_iow(int reg, u8 value); + +/* DM9000 network board routine ---------------------------- */ + +#define DM9000_outb(d,r) ( *(volatile u8 *)r = d ) +#define DM9000_outw(d,r) ( *(volatile u16 *)r = d ) +#define DM9000_outl(d,r) ( *(volatile u32 *)r = d ) +#define DM9000_inb(r) (*(volatile u8 *)r) +#define DM9000_inw(r) (*(volatile u16 *)r) +#define DM9000_inl(r) (*(volatile u32 *)r) + +#ifdef CONFIG_DM9000_DEBUG +static void +dump_regs(void) +{ + DM9000_DBG("\n"); + DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0)); + DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1)); + DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2)); + DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3)); + DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4)); + DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5)); + DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6)); + DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(ISR)); + DM9000_DBG("\n"); +} +#endif /* */ + +/* + Search DM9000 board, allocate space and register it +*/ +int +dm9000_probe(void) +{ + u32 id_val; + id_val = DM9000_ior(DM9000_VIDL); + id_val |= DM9000_ior(DM9000_VIDH) << 8; + id_val |= DM9000_ior(DM9000_PIDL) << 16; + id_val |= DM9000_ior(DM9000_PIDH) << 24; + if (id_val == DM9000_ID) { + printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE, + id_val); + return 0; + } else { + printf("dm9000 not found at 0x%08x id: 0x%08x\n", + CONFIG_DM9000_BASE, id_val); + return -1; + } +} + +/* Set PHY operationg mode +*/ +static void +set_PHY_mode(void) +{ + u16 phy_reg4 = 0x01e1, phy_reg0 = 0x1000; + if (!(media_mode & DM9000_AUTO)) { + switch (media_mode) { + case DM9000_10MHD: + phy_reg4 = 0x21; + phy_reg0 = 0x0000; + break; + case DM9000_10MFD: + phy_reg4 = 0x41; + phy_reg0 = 0x1100; + break; + case DM9000_100MHD: + phy_reg4 = 0x81; + phy_reg0 = 0x2000; + break; + case DM9000_100MFD: + phy_reg4 = 0x101; + phy_reg0 = 0x3100; + break; + } + phy_write(4, phy_reg4); /* Set PHY media mode */ + phy_write(0, phy_reg0); /* Tmp */ + } + DM9000_iow(DM9000_GPCR, 0x01); /* Let GPIO0 output */ + DM9000_iow(DM9000_GPR, 0x00); /* Enable PHY */ +} + +/* + Init HomeRun DM9801 +*/ +static void +program_dm9801(u16 HPNA_rev) +{ + __u16 reg16, reg17, reg24, reg25; + if (!nfloor) + nfloor = DM9801_NOISE_FLOOR; + reg16 = phy_read(16); + reg17 = phy_read(17); + reg24 = phy_read(24); + reg25 = phy_read(25); + switch (HPNA_rev) { + case 0xb900: /* DM9801 E3 */ + reg16 |= 0x1000; + reg25 = ((reg24 + nfloor) & 0x00ff) | 0xf000; + break; + case 0xb901: /* DM9801 E4 */ + reg25 = ((reg24 + nfloor) & 0x00ff) | 0xc200; + reg17 = (reg17 & 0xfff0) + nfloor + 3; + break; + case 0xb902: /* DM9801 E5 */ + case 0xb903: /* DM9801 E6 */ + default: + reg16 |= 0x1000; + reg25 = ((reg24 + nfloor - 3) & 0x00ff) | 0xc200; + reg17 = (reg17 & 0xfff0) + nfloor; + } + phy_write(16, reg16); + phy_write(17, reg17); + phy_write(25, reg25); +} + +/* + Init LongRun DM9802 +*/ +static void +program_dm9802(void) +{ + __u16 reg25; + if (!nfloor) + nfloor = DM9802_NOISE_FLOOR; + reg25 = phy_read(25); + reg25 = (reg25 & 0xff00) + nfloor; + phy_write(25, reg25); +} + +/* Identify NIC type +*/ +static void +identify_nic(void) +{ + struct board_info *db = &dmfe_info; /* Point a board information structure */ + u16 phy_reg3; + DM9000_iow(DM9000_NCR, NCR_EXT_PHY); + phy_reg3 = phy_read(3); + switch (phy_reg3 & 0xfff0) { + case 0xb900: + if (phy_read(31) == 0x4404) { + db->nic_type = HOMERUN_NIC; + program_dm9801(phy_reg3); + DM9000_DBG("found homerun NIC\n"); + } else { + db->nic_type = LONGRUN_NIC; + DM9000_DBG("found longrun NIC\n"); + program_dm9802(); + } + break; + default: + db->nic_type = FASTETHER_NIC; + break; + } + DM9000_iow(DM9000_NCR, 0); +} + +/* General Purpose dm9000 reset routine */ +static void +dm9000_reset(void) +{ + DM9000_DBG("resetting\n"); + DM9000_iow(DM9000_NCR, NCR_RST); + udelay(1000); /* delay 1ms */ +} + +/* Initilize dm9000 board +*/ +int +eth_init(bd_t * bd) +{ + int i, oft, lnk; + DM9000_DBG("eth_init()\n"); + + /* RESET device */ + dm9000_reset(); + dm9000_probe(); + + /* NIC Type: FASTETHER, HOMERUN, LONGRUN */ + identify_nic(); + + /* GPIO0 on pre-activate PHY */ + DM9000_iow(DM9000_GPR, 0x00); /*REG_1F bit0 activate phyxcer */ + + /* Set PHY */ + set_PHY_mode(); + + /* Program operating register */ + DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */ + DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */ + DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ + DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */ + DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */ + DM9000_iow(DM9000_SMCR, 0); /* Special Mode */ + DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */ + DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */ + + /* Set Node address */ + for (i = 0; i < 6; i++) + ((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i); + printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0], + bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3], + bd->bi_enetaddr[4], bd->bi_enetaddr[5]); + for (i = 0, oft = 0x10; i < 6; i++, oft++) + DM9000_iow(oft, bd->bi_enetaddr[i]); + for (i = 0, oft = 0x16; i < 8; i++, oft++) + DM9000_iow(oft, 0xff); + + /* read back mac, just to be sure */ + for (i = 0, oft = 0x10; i < 6; i++, oft++) + DM9000_DBG("%02x:", DM9000_ior(oft)); + DM9000_DBG("\n"); + + /* Activate DM9000 */ + DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */ + DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */ + i = 0; + while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */ + udelay(1000); + i++; + if (i == 10000) { + printf("could not establish link\n"); + return 0; + } + } + + /* see what we've got */ + lnk = phy_read(17) >> 12; + printf("operating at "); + switch (lnk) { + case 1: + printf("10M half duplex "); + break; + case 2: + printf("10M full duplex "); + break; + case 4: + printf("100M half duplex "); + break; + case 8: + printf("100M full duplex "); + break; + default: + printf("unknown: %d ", lnk); + break; + } + printf("mode\n"); + return 0; +} + +/* + Hardware start transmission. + Send a packet to media from the upper layer. +*/ +int +eth_send(volatile void *packet, int length) +{ + char *data_ptr; + u32 tmplen, i; + int tmo; + DM9000_DBG("eth_send: length: %d\n", length); + for (i = 0; i < length; i++) { + if (i % 8 == 0) + DM9000_DBG("\nSend: 02x: ", i); + DM9000_DBG("%02x ", ((unsigned char *) packet)[i]); + } DM9000_DBG("\n"); + + /* Move data to DM9000 TX RAM */ + data_ptr = (char *) packet; + DM9000_outb(DM9000_MWCMD, DM9000_IO); + +#ifdef CONFIG_DM9000_USE_8BIT + /* Byte mode */ + for (i = 0; i < length; i++) + DM9000_outb((data_ptr[i] & 0xff), DM9000_DATA); + +#endif /* */ +#ifdef CONFIG_DM9000_USE_16BIT + tmplen = (length + 1) / 2; + for (i = 0; i < tmplen; i++) + DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA); + +#endif /* */ +#ifdef CONFIG_DM9000_USE_32BIT + tmplen = (length + 3) / 4; + for (i = 0; i < tmplen; i++) + DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA); + +#endif /* */ + + /* Set TX length to DM9000 */ + DM9000_iow(DM9000_TXPLL, length & 0xff); + DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff); + + /* Issue TX polling command */ + DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ + + /* wait for end of transmission */ + tmo = get_timer(0) + 5 * CFG_HZ; + while (DM9000_ior(DM9000_TCR) & TCR_TXREQ) { + if (get_timer(0) >= tmo) { + printf("transmission timeout\n"); + break; + } + } + DM9000_DBG("transmit done\n\n"); + return 0; +} + +/* + Stop the interface. + The interface is stopped when it is brought. +*/ +void +eth_halt(void) +{ + DM9000_DBG("eth_halt\n"); + + /* RESET devie */ + phy_write(0, 0x8000); /* PHY RESET */ + DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */ + DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */ + DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */ +} + +/* + Received a packet and pass to upper layer +*/ +int +eth_rx(void) +{ + u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0]; + u16 RxStatus, RxLen = 0; + u32 tmplen, i; + + /* Check packet ready or not */ + DM9000_ior(DM9000_MRCMDX); /* Dummy read */ + rxbyte = DM9000_inb(DM9000_DATA); /* Got most updated data */ + if (rxbyte == 0) + return 0; + + /* Status check: this byte must be 0 or 1 */ + if (rxbyte > 1) { + DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */ + DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */ + DM9000_DBG("rx status check: %d\n", rxbyte); + } + DM9000_DBG("receiving packet\n"); + + /* A packet ready now & Get status/length */ + DM9000_outb(DM9000_MRCMD, DM9000_IO); + +#ifdef CONFIG_DM9000_USE_8BIT + RxStatus = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8); + RxLen = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8); + +#endif /* */ +#ifdef CONFIG_DM9000_USE_16BIT + RxStatus = DM9000_inw(DM9000_DATA); + RxLen = DM9000_inw(DM9000_DATA); + +#endif /* */ +#ifdef CONFIG_DM9000_USE_32BIT + tmpdata = DM9000_inl(DM9000_DATA); + RxStatus = tmpdata; + RxLen = tmpdata >> 16; + +#endif /* */ + DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen); + + /* Move data from DM9000 */ + /* Read received packet from RX SRAM */ +#ifdef CONFIG_DM9000_USE_8BIT + for (i = 0; i < RxLen; i++) + rdptr[i] = DM9000_inb(DM9000_DATA); + +#endif /* */ +#ifdef CONFIG_DM9000_USE_16BIT + tmplen = (RxLen + 1) / 2; + for (i = 0; i < tmplen; i++) + ((u16 *) rdptr)[i] = DM9000_inw(DM9000_DATA); + +#endif /* */ +#ifdef CONFIG_DM9000_USE_32BIT + tmplen = (RxLen + 3) / 4; + for (i = 0; i < tmplen; i++) + ((u32 *) rdptr)[i] = DM9000_inl(DM9000_DATA); + +#endif /* */ + if ((RxStatus & 0xbf00) || (RxLen < 0x40) + || (RxLen > DM9000_PKT_MAX)) { + if (RxStatus & 0x100) { + printf("rx fifo error\n"); + } + if (RxStatus & 0x200) { + printf("rx crc error\n"); + } + if (RxStatus & 0x8000) { + printf("rx length error\n"); + } + if (RxLen > DM9000_PKT_MAX) { + printf("rx length too big\n"); + dm9000_reset(); + } + } else { + + /* Pass to upper layer */ + DM9000_DBG("passing packet to upper layer\n"); + NetReceive(NetRxPackets[0], RxLen); + return RxLen; + } + return 0; +} + +/* + Read a word data from SROM +*/ +static u16 +read_srom_word(int offset) +{ + DM9000_iow(DM9000_EPAR, offset); + DM9000_iow(DM9000_EPCR, 0x4); + udelay(200); + DM9000_iow(DM9000_EPCR, 0x0); + return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8)); +} + +/* + Read a byte from I/O port +*/ +static u8 +DM9000_ior(int reg) +{ + DM9000_outb(reg, DM9000_IO); + return DM9000_inb(DM9000_DATA); +} + +/* + Write a byte to I/O port +*/ +static void +DM9000_iow(int reg, u8 value) +{ + DM9000_outb(reg, DM9000_IO); + DM9000_outb(value, DM9000_DATA); +} + +/* + Read a word from phyxcer +*/ +static u16 +phy_read(int reg) +{ + u16 val; + + /* Fill the phyxcer register into REG_0C */ + DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); + DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */ + udelay(100); /* Wait read complete */ + DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */ + val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL); + + /* The read data keeps on REG_0D & REG_0E */ + DM9000_DBG("phy_read(%d): %d\n", reg, val); + return val; +} + +/* + Write a word to phyxcer +*/ +static void +phy_write(int reg, u16 value) +{ + + /* Fill the phyxcer register into REG_0C */ + DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); + + /* Fill the written data into REG_0D & REG_0E */ + DM9000_iow(DM9000_EPDRL, (value & 0xff)); + DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff)); + DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */ + udelay(500); /* Wait write complete */ + DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */ + DM9000_DBG("phy_write(reg:%d, value:%d)\n", reg, value); +} +#endif /* CONFIG_DRIVER_DM9000 */ diff --git a/drivers/dm9000x.h b/drivers/dm9000x.h new file mode 100644 index 0000000..f47ff8c --- /dev/null +++ b/drivers/dm9000x.h @@ -0,0 +1,119 @@ +/* + * dm9000 Ethernet + */ + +#ifdef CONFIG_DRIVER_DM9000 + +#define DM9000_ID 0x90000A46 +#define DM9000_PKT_MAX 1536 /* Received packet max size */ +#define DM9000_PKT_RDY 0x01 /* Packet ready to receive */ + +/* although the registers are 16 bit, they are 32-bit aligned. + */ + +#define DM9000_NCR 0x00 +#define DM9000_NSR 0x01 +#define DM9000_TCR 0x02 +#define DM9000_TSR1 0x03 +#define DM9000_TSR2 0x04 +#define DM9000_RCR 0x05 +#define DM9000_RSR 0x06 +#define DM9000_ROCR 0x07 +#define DM9000_BPTR 0x08 +#define DM9000_FCTR 0x09 +#define DM9000_FCR 0x0A +#define DM9000_EPCR 0x0B +#define DM9000_EPAR 0x0C +#define DM9000_EPDRL 0x0D +#define DM9000_EPDRH 0x0E +#define DM9000_WCR 0x0F + +#define DM9000_PAR 0x10 +#define DM9000_MAR 0x16 + +#define DM9000_GPCR 0x1e +#define DM9000_GPR 0x1f +#define DM9000_TRPAL 0x22 +#define DM9000_TRPAH 0x23 +#define DM9000_RWPAL 0x24 +#define DM9000_RWPAH 0x25 + +#define DM9000_VIDL 0x28 +#define DM9000_VIDH 0x29 +#define DM9000_PIDL 0x2A +#define DM9000_PIDH 0x2B + +#define DM9000_CHIPR 0x2C +#define DM9000_SMCR 0x2F + +#define DM9000_PHY 0x40 /* PHY address 0x01 */ + +#define DM9000_MRCMDX 0xF0 +#define DM9000_MRCMD 0xF2 +#define DM9000_MRRL 0xF4 +#define DM9000_MRRH 0xF5 +#define DM9000_MWCMDX 0xF6 +#define DM9000_MWCMD 0xF8 +#define DM9000_MWRL 0xFA +#define DM9000_MWRH 0xFB +#define DM9000_TXPLL 0xFC +#define DM9000_TXPLH 0xFD +#define DM9000_ISR 0xFE +#define DM9000_IMR 0xFF + +#define NCR_EXT_PHY (1<<7) +#define NCR_WAKEEN (1<<6) +#define NCR_FCOL (1<<4) +#define NCR_FDX (1<<3) +#define NCR_LBK (3<<1) +#define NCR_RST (1<<0) + +#define NSR_SPEED (1<<7) +#define NSR_LINKST (1<<6) +#define NSR_WAKEST (1<<5) +#define NSR_TX2END (1<<3) +#define NSR_TX1END (1<<2) +#define NSR_RXOV (1<<1) + +#define TCR_TJDIS (1<<6) +#define TCR_EXCECM (1<<5) +#define TCR_PAD_DIS2 (1<<4) +#define TCR_CRC_DIS2 (1<<3) +#define TCR_PAD_DIS1 (1<<2) +#define TCR_CRC_DIS1 (1<<1) +#define TCR_TXREQ (1<<0) + +#define TSR_TJTO (1<<7) +#define TSR_LC (1<<6) +#define TSR_NC (1<<5) +#define TSR_LCOL (1<<4) +#define TSR_COL (1<<3) +#define TSR_EC (1<<2) + +#define RCR_WTDIS (1<<6) +#define RCR_DIS_LONG (1<<5) +#define RCR_DIS_CRC (1<<4) +#define RCR_ALL (1<<3) +#define RCR_RUNT (1<<2) +#define RCR_PRMSC (1<<1) +#define RCR_RXEN (1<<0) + +#define RSR_RF (1<<7) +#define RSR_MF (1<<6) +#define RSR_LCS (1<<5) +#define RSR_RWTO (1<<4) +#define RSR_PLE (1<<3) +#define RSR_AE (1<<2) +#define RSR_CE (1<<1) +#define RSR_FOE (1<<0) + +#define FCTR_HWOT(ot) (( ot & 0xf ) << 4 ) +#define FCTR_LWOT(ot) ( ot & 0xf ) + +#define IMR_PAR (1<<7) +#define IMR_ROOM (1<<3) +#define IMR_ROM (1<<2) +#define IMR_PTM (1<<1) +#define IMR_PRM (1<<0) + +#endif diff --git a/drivers/serial_imx.c b/drivers/serial_imx.c new file mode 100644 index 0000000..9dbaa56 --- /dev/null +++ b/drivers/serial_imx.c @@ -0,0 +1,201 @@ +/* + * (c) 2004 Sascha Hauer <sascha@saschahauer.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <common.h> +#if defined (CONFIG_IMX) + +#include <asm/arch/imx-regs.h> + +#ifndef CONFIG_IMX_SERIAL_NONE + +#if defined CONFIG_IMX_SERIAL1 +#define UART_BASE IMX_UART1_BASE +#elif defined CONFIG_IMX_SERIAL2 +#define UART_BASE IMX_UART2_BASE +#else +#error "define CONFIG_IMX_SERIAL1, CONFIG_IMX_SERIAL2 or CONFIG_IMX_SERIAL_NONE" +#endif + +struct imx_serial { + volatile uint32_t urxd[16]; + volatile uint32_t utxd[16]; + volatile uint32_t ucr1; + volatile uint32_t ucr2; + volatile uint32_t ucr3; + volatile uint32_t ucr4; + volatile uint32_t ufcr; + volatile uint32_t usr1; + volatile uint32_t usr2; + volatile uint32_t uesc; + volatile uint32_t utim; + volatile uint32_t ubir; + volatile uint32_t ubmr; + volatile uint32_t ubrc; + volatile uint32_t bipr[4]; + volatile uint32_t bmpr[4]; + volatile uint32_t uts; +}; + +void serial_setbrg (void) +{ + serial_init(); +} + +extern void imx_gpio_mode(int gpio_mode); + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init (void) +{ + volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; +#ifdef CONFIG_IMX_SERIAL1 + imx_gpio_mode(PC11_PF_UART1_TXD); + imx_gpio_mode(PC12_PF_UART1_RXD); +#else + imx_gpio_mode(PB30_PF_UART2_TXD); + imx_gpio_mode(PB31_PF_UART2_RXD); +#endif + + /* Disable UART */ + base->ucr1 &= ~UCR1_UARTEN; + + /* Set to default POR state */ + + base->ucr1 = 0x00000004; + base->ucr2 = 0x00000000; + base->ucr3 = 0x00000000; + base->ucr4 = 0x00008040; + base->uesc = 0x0000002B; + base->utim = 0x00000000; + base->ubir = 0x00000000; + base->ubmr = 0x00000000; + base->uts = 0x00000000; + /* Set clocks */ + base->ucr4 |= UCR4_REF16; + + /* Configure FIFOs */ + base->ufcr = 0xa81; + + /* Set the numerator value minus one of the BRM ratio */ + base->ubir = (CONFIG_BAUDRATE / 100) - 1; + + /* Set the denominator value minus one of the BRM ratio */ + base->ubmr = 10000 - 1; + + /* Set to 8N1 */ + base->ucr2 &= ~UCR2_PREN; + base->ucr2 |= UCR2_WS; + base->ucr2 &= ~UCR2_STPB; + + /* Ignore RTS */ + base->ucr2 |= UCR2_IRTS; + + /* Enable UART */ + base->ucr1 |= UCR1_UARTEN | UCR1_UARTCLKEN; + + /* Enable FIFOs */ + base->ucr2 |= UCR2_SRST | UCR2_RXEN | UCR2_TXEN; + + /* Clear status flags */ + base->usr2 |= USR2_ADET | + USR2_DTRF | + USR2_IDLE | + USR2_IRINT | + USR2_WAKE | + USR2_RTSF | + USR2_BRCD | + USR2_ORE | + USR2_RDR; + + /* Clear status flags */ + base->usr1 |= USR1_PARITYERR | + USR1_RTSD | + USR1_ESCF | + USR1_FRAMERR | + USR1_AIRINT | + USR1_AWAKE; + return (0); +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is successful, the character read is + * written into its argument c. + */ +int serial_getc (void) +{ + volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; + unsigned char ch; + + while(base->uts & UTS_RXEMPTY); + + ch = (char)base->urxd[0]; + + return ch; +} + +#ifdef CONFIG_HWFLOW +static int hwflow = 0; /* turned off by default */ +int hwflow_onoff(int on) +{ +} +#endif + +/* + * Output a single byte to the serial port. + */ +void serial_putc (const char c) +{ + volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; + + /* Wait for Tx FIFO not full */ + while (base->uts & UTS_TXFULL); + + base->utxd[0] = c; + + /* If \n, also do \r */ + if (c == '\n') + serial_putc ('\r'); +} + +/* + * Test whether a character is in the RX buffer + */ +int serial_tstc (void) +{ + volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; + + /* If receive fifo is empty, return false */ + if (base->uts & UTS_RXEMPTY) + return 0; + return 1; +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} +#endif /* CONFIG_IMX_SERIAL_NONE */ +#endif /* defined CONFIG_IMX */ |