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-rw-r--r--drivers/block/pata_bfin.c25
-rw-r--r--drivers/mmc/bfin_sdh.c18
-rw-r--r--drivers/mtd/nand/bfin_nand.c16
-rw-r--r--drivers/net/bfin_mac.c49
-rw-r--r--drivers/spi/bfin_spi.c292
5 files changed, 147 insertions, 253 deletions
diff --git a/drivers/block/pata_bfin.c b/drivers/block/pata_bfin.c
index f16dabe..847c032 100644
--- a/drivers/block/pata_bfin.c
+++ b/drivers/block/pata_bfin.c
@@ -14,6 +14,7 @@
#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/errno.h>
+#include <asm/portmux.h>
#include <asm/mach-common/bits/pata.h>
#include <ata.h>
#include <libata.h>
@@ -769,19 +770,17 @@ static int bfin_ata_reset_port(struct ata_port *ap)
*/
static int bfin_config_atapi_gpio(struct ata_port *ap)
{
- bfin_write_PORTH_FER(bfin_read_PORTH_FER() | 0x4);
- bfin_write_PORTH_MUX(bfin_read_PORTH_MUX() & ~0x30);
- bfin_write_PORTH_DIR_SET(0x4);
-
- bfin_write_PORTJ_FER(0x7f8);
- bfin_write_PORTJ_MUX(bfin_read_PORTI_MUX() & ~0x3fffc0);
- bfin_write_PORTJ_DIR_SET(0x5f8);
- bfin_write_PORTJ_DIR_CLEAR(0x200);
- bfin_write_PORTJ_INEN(0x200);
-
- bfin_write_PINT2_ASSIGN(0x0707);
- bfin_write_PINT2_MASK_SET(0x200);
- SSYNC();
+ const unsigned short pins[] = {
+ P_ATAPI_RESET, P_ATAPI_DIOR, P_ATAPI_DIOW, P_ATAPI_CS0,
+ P_ATAPI_CS1, P_ATAPI_DMACK, P_ATAPI_DMARQ, P_ATAPI_INTRQ,
+ P_ATAPI_IORDY, P_ATAPI_D0A, P_ATAPI_D1A, P_ATAPI_D2A,
+ P_ATAPI_D3A, P_ATAPI_D4A, P_ATAPI_D5A, P_ATAPI_D6A,
+ P_ATAPI_D7A, P_ATAPI_D8A, P_ATAPI_D9A, P_ATAPI_D10A,
+ P_ATAPI_D11A, P_ATAPI_D12A, P_ATAPI_D13A, P_ATAPI_D14A,
+ P_ATAPI_D15A, P_ATAPI_A0A, P_ATAPI_A1A, P_ATAPI_A2A, 0,
+ };
+
+ peripheral_request_list(pins, "pata_bfin");
return 0;
}
diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c
index f9d560a..4a77779 100644
--- a/drivers/mmc/bfin_sdh.c
+++ b/drivers/mmc/bfin_sdh.c
@@ -15,6 +15,7 @@
#include <asm/errno.h>
#include <asm/byteorder.h>
#include <asm/blackfin.h>
+#include <asm/portmux.h>
#include <asm/mach-common/bits/sdh.h>
#include <asm/mach-common/bits/dma.h>
@@ -41,11 +42,15 @@
# define bfin_write_DMA_X_COUNT bfin_write_DMA4_X_COUNT
# define bfin_write_DMA_X_MODIFY bfin_write_DMA4_X_MODIFY
# define bfin_write_DMA_CONFIG bfin_write_DMA4_CONFIG
+# define PORTMUX_PINS \
+ { P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 }
#elif defined(__ADSPBF54x__)
# define bfin_write_DMA_START_ADDR bfin_write_DMA22_START_ADDR
# define bfin_write_DMA_X_COUNT bfin_write_DMA22_X_COUNT
# define bfin_write_DMA_X_MODIFY bfin_write_DMA22_X_MODIFY
# define bfin_write_DMA_CONFIG bfin_write_DMA22_CONFIG
+# define PORTMUX_PINS \
+ { P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0 }
#else
# error no support for this proc yet
#endif
@@ -208,18 +213,13 @@ static void bfin_sdh_set_ios(struct mmc *mmc)
static int bfin_sdh_init(struct mmc *mmc)
{
-
+ const unsigned short pins[] = PORTMUX_PINS;
u16 pwr_ctl = 0;
-/* Initialize sdh controller */
+
+ /* Initialize sdh controller */
+ peripheral_request_list(pins, "bfin_sdh");
#if defined(__ADSPBF54x__)
bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
- bfin_write_PORTC_FER(bfin_read_PORTC_FER() | 0x3F00);
- bfin_write_PORTC_MUX(bfin_read_PORTC_MUX() & ~0xFFF0000);
-#elif defined(__ADSPBF51x__)
- bfin_write_PORTG_FER(bfin_read_PORTG_FER() | 0x01F8);
- bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~0x3FC) | 0x154);
-#else
-# error no portmux for this proc yet
#endif
bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
/* Disable card detect pin */
diff --git a/drivers/mtd/nand/bfin_nand.c b/drivers/mtd/nand/bfin_nand.c
index 6d3d450..3ee060f 100644
--- a/drivers/mtd/nand/bfin_nand.c
+++ b/drivers/mtd/nand/bfin_nand.c
@@ -26,6 +26,7 @@
#include <nand.h>
#include <asm/blackfin.h>
+#include <asm/portmux.h>
/* Bit masks for NFC_CTL */
@@ -337,6 +338,12 @@ static struct nand_ecclayout bootrom_ecclayout = {
*/
int board_nand_init(struct nand_chip *chip)
{
+ const unsigned short pins[] = {
+ P_NAND_CE, P_NAND_RB, P_NAND_D0, P_NAND_D1, P_NAND_D2,
+ P_NAND_D3, P_NAND_D4, P_NAND_D5, P_NAND_D6, P_NAND_D7,
+ P_NAND_WE, P_NAND_RE, P_NAND_CLE, P_NAND_ALE, 0,
+ };
+
pr_stamp();
/* set width/ecc/timings/etc... */
@@ -347,14 +354,7 @@ int board_nand_init(struct nand_chip *chip)
bfin_write_NFC_IRQSTAT(0xffff);
/* enable GPIO function enable register */
-#ifdef __ADSPBF54x__
- bfin_write_PORTJ_FER(bfin_read_PORTJ_FER() | 6);
-#elif defined(__ADSPBF52x__)
- bfin_write_PORTH_FER(bfin_read_PORTH_FER() | 0xFCFF);
- bfin_write_PORTH_MUX(0);
-#else
-# error no support for this variant
-#endif
+ peripheral_request_list(pins, "bfin_nand");
chip->cmd_ctrl = bfin_nfc_cmd_ctrl;
chip->read_buf = bfin_nfc_read_buf;
diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c
index 720e126..e691bdf 100644
--- a/drivers/net/bfin_mac.c
+++ b/drivers/net/bfin_mac.c
@@ -16,6 +16,7 @@
#include <linux/mii.h>
#include <asm/blackfin.h>
+#include <asm/portmux.h>
#include <asm/mach-common/bits/dma.h>
#include <asm/mach-common/bits/emac.h>
#include <asm/mach-common/bits/pll.h>
@@ -98,7 +99,7 @@ int bfin_EMAC_initialize(bd_t *bis)
hang();
memset(dev, 0, sizeof(*dev));
- sprintf(dev->name, "Blackfin EMAC");
+ strcpy(dev->name, "bfin_mac");
dev->iobase = 0;
dev->priv = 0;
@@ -213,8 +214,17 @@ static int bfin_EMAC_recv(struct eth_device *dev)
/* MDC = SCLK / MDC_freq / 2 - 1 */
#define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)
+#ifndef CONFIG_BFIN_MAC_PINS
+# ifdef CONFIG_RMII
+# define CONFIG_BFIN_MAC_PINS P_RMII0
+# else
+# define CONFIG_BFIN_MAC_PINS P_MII0
+# endif
+#endif
+
static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
{
+ const unsigned short pins[] = CONFIG_BFIN_MAC_PINS;
u16 phydat;
size_t count;
@@ -222,42 +232,7 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
*pVR_CTL |= CLKBUFOE;
/* Set all the pins to peripheral mode */
-#ifdef CONFIG_RMII
- /* grab RMII pins */
-# if defined(__ADSPBF51x__)
- *pPORTF_MUX = (*pPORTF_MUX & \
- ~(PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \
- PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1;
- *pPORTF_FER |= PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15;
- *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1;
- *pPORTG_FER |= PG0 | PG1 | PG2;
-# elif defined(__ADSPBF52x__)
- *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2;
- *pPORTG_FER |= PG14 | PG15;
- *pPORTH_MUX = (*pPORTH_MUX & ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK)) | \
- PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2;
- *pPORTH_FER |= PH0 | PH1 | PH2 | PH3 | PH4 | PH5 | PH6 | PH7 | PH8;
-# else
- *pPORTH_FER |= PH0 | PH1 | PH4 | PH5 | PH6 | PH8 | PH9 | PH14 | PH15;
-# endif
-#else
- /* grab MII & RMII pins */
-# if defined(__ADSPBF51x__)
- *pPORTF_MUX = (*pPORTF_MUX & \
- ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \
- PORT_x_MUX_0_FUNC_1 | PORT_x_MUX_1_FUNC_1 | PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1;
- *pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15;
- *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1;
- *pPORTG_FER |= PG0 | PG1 | PG2;
-# elif defined(__ADSPBF52x__)
- *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2;
- *pPORTG_FER |= PG14 | PG15;
- *pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2 | PORT_x_MUX_2_FUNC_2;
- *pPORTH_FER = -1; /* all pins */
-# else
- *pPORTH_FER = -1; /* all pins */
-# endif
-#endif
+ peripheral_request_list(pins, "bfin_mac");
/* Odd word alignment for Receive Frame DMA word */
/* Configure checksum support and rcve frame word alignment */
diff --git a/drivers/spi/bfin_spi.c b/drivers/spi/bfin_spi.c
index f28d42b..e0ad029 100644
--- a/drivers/spi/bfin_spi.c
+++ b/drivers/spi/bfin_spi.c
@@ -13,6 +13,8 @@
#include <spi.h>
#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/portmux.h>
#include <asm/mach-common/bits/spi.h>
struct bfin_spi_slave {
@@ -33,54 +35,110 @@ MAKE_SPI_FUNC(SPI_BAUD, 0x14)
#define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
-__attribute__((weak))
+#define MAX_CTRL_CS 7
+
+#define gpio_cs(cs) ((cs) - MAX_CTRL_CS)
+#ifdef CONFIG_BFIN_SPI_GPIO_CS
+# define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS)
+#else
+# define is_gpio_cs(cs) 0
+#endif
+
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
-#if defined(__ADSPBF538__) || defined(__ADSPBF539__)
- /* The SPI1/SPI2 buses are weird ... only 1 CS */
- if (bus > 0 && cs != 1)
- return 0;
-#endif
- return (cs >= 1 && cs <= 7);
+ if (is_gpio_cs(cs))
+ return gpio_is_valid(gpio_cs(cs));
+ else
+ return (cs >= 1 && cs <= MAX_CTRL_CS);
}
-__attribute__((weak))
void spi_cs_activate(struct spi_slave *slave)
{
struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
- write_SPI_FLG(bss,
- (read_SPI_FLG(bss) &
- ~((!bss->flg << 8) << slave->cs)) |
- (1 << slave->cs));
+
+ if (is_gpio_cs(slave->cs)) {
+ unsigned int cs = gpio_cs(slave->cs);
+ gpio_set_value(cs, bss->flg);
+ debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
+ } else {
+ write_SPI_FLG(bss,
+ (read_SPI_FLG(bss) &
+ ~((!bss->flg << 8) << slave->cs)) |
+ (1 << slave->cs));
+ debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
+ }
+
SSYNC();
- debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
}
-__attribute__((weak))
void spi_cs_deactivate(struct spi_slave *slave)
{
struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
- u16 flg;
-
- /* make sure we force the cs to deassert rather than let the
- * pin float back up. otherwise, exact timings may not be
- * met some of the time leading to random behavior (ugh).
- */
- flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
- write_SPI_FLG(bss, flg);
- SSYNC();
- debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
- flg &= ~(1 << slave->cs);
- write_SPI_FLG(bss, flg);
+ if (is_gpio_cs(slave->cs)) {
+ unsigned int cs = gpio_cs(slave->cs);
+ gpio_set_value(cs, !bss->flg);
+ debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
+ } else {
+ u16 flg;
+
+ /* make sure we force the cs to deassert rather than let the
+ * pin float back up. otherwise, exact timings may not be
+ * met some of the time leading to random behavior (ugh).
+ */
+ flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
+ write_SPI_FLG(bss, flg);
+ SSYNC();
+ debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
+
+ flg &= ~(1 << slave->cs);
+ write_SPI_FLG(bss, flg);
+ debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
+ }
+
SSYNC();
- debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
}
void spi_init()
{
}
+#ifdef SPI_CTL
+# define SPI0_CTL SPI_CTL
+#endif
+
+#define SPI_PINS(n) \
+ [n] = { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 }
+static unsigned short pins[][5] = {
+#ifdef SPI0_CTL
+ SPI_PINS(0),
+#endif
+#ifdef SPI1_CTL
+ SPI_PINS(1),
+#endif
+#ifdef SPI2_CTL
+ SPI_PINS(2),
+#endif
+};
+
+#define SPI_CS_PINS(n) \
+ [n] = { \
+ P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \
+ P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \
+ P_SPI##n##_SSEL7, \
+ }
+static const unsigned short cs_pins[][7] = {
+#ifdef SPI0_CTL
+ SPI_CS_PINS(0),
+#endif
+#ifdef SPI1_CTL
+ SPI_CS_PINS(1),
+#endif
+#ifdef SPI2_CTL
+ SPI_CS_PINS(2),
+#endif
+};
+
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
@@ -92,11 +150,14 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
if (!spi_cs_is_valid(bus, cs))
return NULL;
+ if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) {
+ debug("%s: invalid bus %u\n", __func__, bus);
+ return NULL;
+ }
switch (bus) {
-#ifdef SPI_CTL
-# define SPI0_CTL SPI_CTL
-#endif
+#ifdef SPI0_CTL
case 0: mmr_base = SPI0_CTL; break;
+#endif
#ifdef SPI1_CTL
case 1: mmr_base = SPI1_CTL; break;
#endif
@@ -142,168 +203,21 @@ void spi_free_slave(struct spi_slave *slave)
free(bss);
}
-static void spi_portmux(struct spi_slave *slave)
-{
-#if defined(__ADSPBF51x__)
-#define SET_MUX(port, mux, func) port##_mux = ((port##_mux & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_##func)
- u16 f_mux = bfin_read_PORTF_MUX();
- u16 f_fer = bfin_read_PORTF_FER();
- u16 g_mux = bfin_read_PORTG_MUX();
- u16 g_fer = bfin_read_PORTG_FER();
- u16 h_mux = bfin_read_PORTH_MUX();
- u16 h_fer = bfin_read_PORTH_FER();
- switch (slave->bus) {
- case 0:
- /* set SCK/MISO/MOSI */
- SET_MUX(g, 7, 1);
- g_fer |= PG12 | PG13 | PG14;
- switch (slave->cs) {
- case 1: SET_MUX(f, 2, 1); f_fer |= PF7; break;
- case 2: /* see G above */ g_fer |= PG15; break;
- case 3: SET_MUX(h, 1, 3); f_fer |= PH4; break;
- case 4: /* no muxing */ h_fer |= PH8; break;
- case 5: SET_MUX(g, 1, 3); h_fer |= PG3; break;
- case 6: /* no muxing */ break;
- case 7: /* no muxing */ break;
- }
- case 1:
- /* set SCK/MISO/MOSI */
- SET_MUX(h, 0, 2);
- h_fer |= PH1 | PH2 | PH3;
- switch (slave->cs) {
- case 1: SET_MUX(h, 2, 3); h_fer |= PH6; break;
- case 2: SET_MUX(f, 0, 3); f_fer |= PF0; break;
- case 3: SET_MUX(g, 0, 3); g_fer |= PG0; break;
- case 4: SET_MUX(f, 3, 3); f_fer |= PF8; break;
- case 5: SET_MUX(g, 6, 3); h_fer |= PG11; break;
- case 6: /* no muxing */ break;
- case 7: /* no muxing */ break;
- }
- }
- bfin_write_PORTF_MUX(f_mux);
- bfin_write_PORTF_FER(f_fer);
- bfin_write_PORTG_MUX(g_mux);
- bfin_write_PORTG_FER(g_fer);
- bfin_write_PORTH_MUX(h_mux);
- bfin_write_PORTH_FER(h_fer);
-#elif defined(__ADSPBF52x__)
-#define SET_MUX(port, mux, func) port##_mux = ((port##_mux & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_##func)
- u16 f_mux = bfin_read_PORTF_MUX();
- u16 f_fer = bfin_read_PORTF_FER();
- u16 g_mux = bfin_read_PORTG_MUX();
- u16 g_fer = bfin_read_PORTG_FER();
- u16 h_mux = bfin_read_PORTH_MUX();
- u16 h_fer = bfin_read_PORTH_FER();
- /* set SCK/MISO/MOSI */
- SET_MUX(g, 0, 3);
- g_fer |= PG2 | PG3 | PG4;
- switch (slave->cs) {
- case 1: /* see G above */ g_fer |= PG1; break;
- case 2: SET_MUX(f, 4, 3); f_fer |= PF12; break;
- case 3: SET_MUX(f, 4, 3); f_fer |= PF13; break;
- case 4: SET_MUX(h, 1, 1); h_fer |= PH8; break;
- case 5: SET_MUX(h, 2, 1); h_fer |= PH9; break;
- case 6: SET_MUX(f, 1, 3); f_fer |= PF9; break;
- case 7: SET_MUX(f, 2, 3); f_fer |= PF10; break;
- }
- bfin_write_PORTF_MUX(f_mux);
- bfin_write_PORTF_FER(f_fer);
- bfin_write_PORTG_MUX(g_mux);
- bfin_write_PORTG_FER(g_fer);
- bfin_write_PORTH_MUX(h_mux);
- bfin_write_PORTH_FER(h_fer);
-#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
- u16 mux = bfin_read_PORT_MUX();
- u16 f_fer = bfin_read_PORTF_FER();
- /* set SCK/MISO/MOSI */
- f_fer |= PF11 | PF12 | PF13;
- switch (slave->cs) {
- case 1: f_fer |= PF10; break;
- case 2: mux |= PJSE; break;
- case 3: mux |= PJSE; break;
- case 4: mux |= PFS4E; f_fer |= PF6; break;
- case 5: mux |= PFS5E; f_fer |= PF5; break;
- case 6: mux |= PFS6E; f_fer |= PF4; break;
- case 7: mux |= PJCE_SPI; break;
- }
- bfin_write_PORT_MUX(mux);
- bfin_write_PORTF_FER(f_fer);
-#elif defined(__ADSPBF538__) || defined(__ADSPBF539__)
- u16 fer, pins;
- if (slave->bus == 1)
- pins = PD0 | PD1 | PD2 | (slave->cs == 1 ? PD4 : 0);
- else if (slave->bus == 2)
- pins = PD5 | PD6 | PD7 | (slave->cs == 1 ? PD9 : 0);
- else
- pins = 0;
- if (pins) {
- fer = bfin_read_PORTDIO_FER();
- fer &= ~pins;
- bfin_write_PORTDIO_FER(fer);
- }
-#elif defined(__ADSPBF54x__)
-#define DO_MUX(port, pin) \
- mux = ((mux & ~PORT_x_MUX_##pin##_MASK) | PORT_x_MUX_##pin##_FUNC_1); \
- fer |= P##port##pin;
- u32 mux;
- u16 fer;
- switch (slave->bus) {
- case 0:
- mux = bfin_read_PORTE_MUX();
- fer = bfin_read_PORTE_FER();
- /* set SCK/MISO/MOSI */
- DO_MUX(E, 0);
- DO_MUX(E, 1);
- DO_MUX(E, 2);
- switch (slave->cs) {
- case 1: DO_MUX(E, 4); break;
- case 2: DO_MUX(E, 5); break;
- case 3: DO_MUX(E, 6); break;
- }
- bfin_write_PORTE_MUX(mux);
- bfin_write_PORTE_FER(fer);
- break;
- case 1:
- mux = bfin_read_PORTG_MUX();
- fer = bfin_read_PORTG_FER();
- /* set SCK/MISO/MOSI */
- DO_MUX(G, 8);
- DO_MUX(G, 9);
- DO_MUX(G, 10);
- switch (slave->cs) {
- case 1: DO_MUX(G, 5); break;
- case 2: DO_MUX(G, 6); break;
- case 3: DO_MUX(G, 7); break;
- }
- bfin_write_PORTG_MUX(mux);
- bfin_write_PORTG_FER(fer);
- break;
- case 2:
- mux = bfin_read_PORTB_MUX();
- fer = bfin_read_PORTB_FER();
- /* set SCK/MISO/MOSI */
- DO_MUX(B, 12);
- DO_MUX(B, 13);
- DO_MUX(B, 14);
- switch (slave->cs) {
- case 1: DO_MUX(B, 9); break;
- case 2: DO_MUX(B, 10); break;
- case 3: DO_MUX(B, 11); break;
- }
- bfin_write_PORTB_MUX(mux);
- bfin_write_PORTB_FER(fer);
- break;
- }
-#endif
-}
-
int spi_claim_bus(struct spi_slave *slave)
{
struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
- spi_portmux(slave);
+ if (is_gpio_cs(slave->cs)) {
+ unsigned int cs = gpio_cs(slave->cs);
+ gpio_request(cs, "bfin-spi");
+ gpio_direction_output(cs, !bss->flg);
+ pins[slave->bus][0] = P_DONTCARE;
+ } else
+ pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
+ peripheral_request_list(pins[slave->bus], "bfin-spi");
+
write_SPI_CTL(bss, bss->ctl);
write_SPI_BAUD(bss, bss->baud);
SSYNC();
@@ -314,7 +228,13 @@ int spi_claim_bus(struct spi_slave *slave)
void spi_release_bus(struct spi_slave *slave)
{
struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
+
debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
+
+ peripheral_free_list(pins[slave->bus]);
+ if (is_gpio_cs(slave->cs))
+ gpio_free(gpio_cs(slave->cs));
+
write_SPI_CTL(bss, 0);
SSYNC();
}
generated by cgit v1.1 at 2024-11-10 08:58:33 +0000