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-rw-r--r--drivers/gpio/mxs_gpio.c4
-rw-r--r--drivers/i2c/tegra_i2c.c5
-rw-r--r--drivers/misc/fsl_iim.c13
-rw-r--r--drivers/net/fec_mxc.c177
-rw-r--r--drivers/power/power_fsl.c3
-rw-r--r--drivers/serial/ns16550.c5
6 files changed, 121 insertions, 86 deletions
diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c
index d9a7a3a..da0199b 100644
--- a/drivers/gpio/mxs_gpio.c
+++ b/drivers/gpio/mxs_gpio.c
@@ -95,10 +95,10 @@ int gpio_direction_output(unsigned gpio, int value)
struct mxs_register_32 *reg =
(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
- writel(1 << PAD_PIN(gpio), &reg->reg_set);
-
gpio_set_value(gpio, value);
+ writel(1 << PAD_PIN(gpio), &reg->reg_set);
+
return 0;
}
diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c
index 9847cf1..594e5dd 100644
--- a/drivers/i2c/tegra_i2c.c
+++ b/drivers/i2c/tegra_i2c.c
@@ -629,3 +629,8 @@ U_BOOT_I2C_ADAP_COMPLETE(tegra2, tegra_i2c_init, tegra_i2c_probe,
U_BOOT_I2C_ADAP_COMPLETE(tegra3, tegra_i2c_init, tegra_i2c_probe,
tegra_i2c_read, tegra_i2c_write,
tegra_i2c_set_bus_speed, 100000, 0, 3)
+#if TEGRA_I2C_NUM_CONTROLLERS > 4
+U_BOOT_I2C_ADAP_COMPLETE(tegra4, tegra_i2c_init, tegra_i2c_probe,
+ tegra_i2c_read, tegra_i2c_write,
+ tegra_i2c_set_bus_speed, 100000, 0, 4)
+#endif
diff --git a/drivers/misc/fsl_iim.c b/drivers/misc/fsl_iim.c
index 44ae7b1..36433a7 100644
--- a/drivers/misc/fsl_iim.c
+++ b/drivers/misc/fsl_iim.c
@@ -16,6 +16,9 @@
#ifndef CONFIG_MPC512X
#include <asm/arch/imx-regs.h>
#endif
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#include <asm/arch/clock.h>
+#endif
/* FSL IIM-specific constants */
#define STAT_BUSY 0x80
@@ -93,6 +96,10 @@ struct fsl_iim {
} bank[8];
};
+#if !defined(CONFIG_MX51) && !defined(CONFIG_MX53)
+#define enable_efuse_prog_supply(enable)
+#endif
+
static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int assert,
const char *caller)
{
@@ -237,12 +244,16 @@ int fuse_prog(u32 bank, u32 word, u32 val)
if (ret)
return ret;
+ enable_efuse_prog_supply(1);
for (bit = 0; val; bit++, val >>= 1)
if (val & 0x01) {
ret = prog_bit(regs, bank, word, bit);
- if (ret)
+ if (ret) {
+ enable_efuse_prog_supply(0);
return ret;
+ }
}
+ enable_efuse_prog_supply(0);
return 0;
}
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 107cd6e..3b2b995 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -270,49 +270,34 @@ static int fec_tx_task_disable(struct fec_priv *fec)
* @param[in] dsize desired size of each receive buffer
* @return 0 on success
*
- * For this task we need additional memory for the data buffers. And each
- * data buffer requires some alignment. Thy must be aligned to a specific
- * boundary each.
+ * Init all RX descriptors to default values.
*/
-static int fec_rbd_init(struct fec_priv *fec, int count, int dsize)
+static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
{
uint32_t size;
+ uint8_t *data;
int i;
/*
- * Allocate memory for the buffers. This allocation respects the
- * alignment
+ * Reload the RX descriptors with default values and wipe
+ * the RX buffers.
*/
size = roundup(dsize, ARCH_DMA_MINALIGN);
for (i = 0; i < count; i++) {
- uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
- if (data_ptr == 0) {
- uint8_t *data = memalign(ARCH_DMA_MINALIGN,
- size);
- if (!data) {
- printf("%s: error allocating rxbuf %d\n",
- __func__, i);
- goto err;
- }
- writel((uint32_t)data, &fec->rbd_base[i].data_pointer);
- } /* needs allocation */
- writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status);
- writew(0, &fec->rbd_base[i].data_length);
+ data = (uint8_t *)fec->rbd_base[i].data_pointer;
+ memset(data, 0, dsize);
+ flush_dcache_range((uint32_t)data, (uint32_t)data + size);
+
+ fec->rbd_base[i].status = FEC_RBD_EMPTY;
+ fec->rbd_base[i].data_length = 0;
}
/* Mark the last RBD to close the ring. */
- writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status);
+ fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
fec->rbd_index = 0;
- return 0;
-
-err:
- for (; i >= 0; i--) {
- uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
- free((void *)data_ptr);
- }
-
- return -ENOMEM;
+ flush_dcache_range((unsigned)fec->rbd_base,
+ (unsigned)fec->rbd_base + size);
}
/**
@@ -332,10 +317,12 @@ static void fec_tbd_init(struct fec_priv *fec)
unsigned addr = (unsigned)fec->tbd_base;
unsigned size = roundup(2 * sizeof(struct fec_bd),
ARCH_DMA_MINALIGN);
- writew(0x0000, &fec->tbd_base[0].status);
- writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
+
+ memset(fec->tbd_base, 0, size);
+ fec->tbd_base[0].status = 0;
+ fec->tbd_base[1].status = FEC_TBD_WRAP;
fec->tbd_index = 0;
- flush_dcache_range(addr, addr+size);
+ flush_dcache_range(addr, addr + size);
}
/**
@@ -527,51 +514,18 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
{
struct fec_priv *fec = (struct fec_priv *)dev->priv;
uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
- uint32_t size;
- int i, ret;
+ int i;
/* Initialize MAC address */
fec_set_hwaddr(dev);
/*
- * Allocate transmit descriptors, there are two in total. This
- * allocation respects cache alignment.
+ * Setup transmit descriptors, there are two in total.
*/
- if (!fec->tbd_base) {
- size = roundup(2 * sizeof(struct fec_bd),
- ARCH_DMA_MINALIGN);
- fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
- if (!fec->tbd_base) {
- ret = -ENOMEM;
- goto err1;
- }
- memset(fec->tbd_base, 0, size);
- fec_tbd_init(fec);
- }
+ fec_tbd_init(fec);
- /*
- * Allocate receive descriptors. This allocation respects cache
- * alignment.
- */
- if (!fec->rbd_base) {
- size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
- ARCH_DMA_MINALIGN);
- fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
- if (!fec->rbd_base) {
- ret = -ENOMEM;
- goto err2;
- }
- memset(fec->rbd_base, 0, size);
- /*
- * Initialize RxBD ring
- */
- if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
- ret = -ENOMEM;
- goto err3;
- }
- flush_dcache_range((unsigned)fec->rbd_base,
- (unsigned)fec->rbd_base + size);
- }
+ /* Setup receive descriptors. */
+ fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
fec_reg_setup(fec);
@@ -608,13 +562,6 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
#endif
fec_open(dev);
return 0;
-
-err3:
- free(fec->rbd_base);
-err2:
- free(fec->tbd_base);
-err1:
- return ret;
}
/**
@@ -907,6 +854,74 @@ static void fec_set_dev_name(char *dest, int dev_id)
sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
}
+static int fec_alloc_descs(struct fec_priv *fec)
+{
+ unsigned int size;
+ int i;
+ uint8_t *data;
+
+ /* Allocate TX descriptors. */
+ size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
+ fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
+ if (!fec->tbd_base)
+ goto err_tx;
+
+ /* Allocate RX descriptors. */
+ size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
+ fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
+ if (!fec->rbd_base)
+ goto err_rx;
+
+ memset(fec->rbd_base, 0, size);
+
+ /* Allocate RX buffers. */
+
+ /* Maximum RX buffer size. */
+ size = roundup(FEC_MAX_PKT_SIZE, ARCH_DMA_MINALIGN);
+ for (i = 0; i < FEC_RBD_NUM; i++) {
+ data = memalign(ARCH_DMA_MINALIGN, size);
+ if (!data) {
+ printf("%s: error allocating rxbuf %d\n", __func__, i);
+ goto err_ring;
+ }
+
+ memset(data, 0, size);
+
+ fec->rbd_base[i].data_pointer = (uint32_t)data;
+ fec->rbd_base[i].status = FEC_RBD_EMPTY;
+ fec->rbd_base[i].data_length = 0;
+ /* Flush the buffer to memory. */
+ flush_dcache_range((uint32_t)data, (uint32_t)data + size);
+ }
+
+ /* Mark the last RBD to close the ring. */
+ fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
+
+ fec->rbd_index = 0;
+ fec->tbd_index = 0;
+
+ return 0;
+
+err_ring:
+ for (; i >= 0; i--)
+ free((void *)fec->rbd_base[i].data_pointer);
+ free(fec->rbd_base);
+err_rx:
+ free(fec->tbd_base);
+err_tx:
+ return -ENOMEM;
+}
+
+static void fec_free_descs(struct fec_priv *fec)
+{
+ int i;
+
+ for (i = 0; i < FEC_RBD_NUM; i++)
+ free((void *)fec->rbd_base[i].data_pointer);
+ free(fec->rbd_base);
+ free(fec->tbd_base);
+}
+
#ifdef CONFIG_PHYLIB
int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
struct mii_dev *bus, struct phy_device *phydev)
@@ -939,6 +954,10 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
memset(edev, 0, sizeof(*edev));
memset(fec, 0, sizeof(*fec));
+ ret = fec_alloc_descs(fec);
+ if (ret)
+ goto err3;
+
edev->priv = fec;
edev->init = fec_init;
edev->send = fec_send;
@@ -957,7 +976,7 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
printf("FEC MXC: Timeout reseting chip\n");
- goto err3;
+ goto err4;
}
udelay(10);
}
@@ -984,6 +1003,8 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
eth_setenv_enetaddr("ethaddr", ethaddr);
}
return ret;
+err4:
+ fec_free_descs(fec);
err3:
free(fec);
err2:
diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c
index ed778f3..ac0b541 100644
--- a/drivers/power/power_fsl.c
+++ b/drivers/power/power_fsl.c
@@ -36,10 +36,10 @@ int pmic_init(unsigned char bus)
p->name = name;
p->number_of_regs = PMIC_NUM_OF_REGS;
+ p->bus = bus;
#if defined(CONFIG_POWER_SPI)
p->interface = PMIC_SPI;
- p->bus = CONFIG_FSL_PMIC_BUS;
p->hw.spi.cs = CONFIG_FSL_PMIC_CS;
p->hw.spi.clk = CONFIG_FSL_PMIC_CLK;
p->hw.spi.mode = CONFIG_FSL_PMIC_MODE;
@@ -50,7 +50,6 @@ int pmic_init(unsigned char bus)
p->interface = PMIC_I2C;
p->hw.i2c.addr = CONFIG_SYS_FSL_PMIC_I2C_ADDR;
p->hw.i2c.tx_num = FSL_PMIC_I2C_LENGTH;
- p->bus = bus;
#else
#error "You must select CONFIG_POWER_SPI or CONFIG_PMIC_I2C"
#endif
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 181c818..fbc37b2 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -56,9 +56,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
;
serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
-#if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
- defined(CONFIG_AM33XX) || defined(CONFIG_TI81XX) || \
- defined(CONFIG_AM43XX)
+#if defined(CONFIG_OMAP) || defined(CONFIG_AM33XX) || \
+ defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX)
serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/
#endif
serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
generated by cgit v1.1 at 2024-12-24 04:14:14 +0000