diff options
Diffstat (limited to 'drivers/spi/mxc_spi.c')
| -rw-r--r-- | drivers/spi/mxc_spi.c | 441 |
1 files changed, 368 insertions, 73 deletions
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index fad9840..81381d9 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -23,27 +23,18 @@ #include <spi.h> #include <asm/errno.h> #include <asm/io.h> +#include <mxc_gpio.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> #ifdef CONFIG_MX27 /* i.MX27 has a completely wrong register layout and register definitions in the * datasheet, the correct one is in the Freescale's Linux driver */ -#error "i.MX27 CSPI not supported due to drastic differences in register definisions" \ +#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \ "See linux mxc_spi driver from Freescale for details." -#else - -#include <asm/arch/mx31.h> - -#define MXC_CSPIRXDATA 0x00 -#define MXC_CSPITXDATA 0x04 -#define MXC_CSPICTRL 0x08 -#define MXC_CSPIINT 0x0C -#define MXC_CSPIDMA 0x10 -#define MXC_CSPISTAT 0x14 -#define MXC_CSPIPERIOD 0x18 -#define MXC_CSPITEST 0x1C -#define MXC_CSPIRESET 0x00 +#elif defined(CONFIG_MX31) #define MXC_CSPICTRL_EN (1 << 0) #define MXC_CSPICTRL_MODE (1 << 1) @@ -56,8 +47,12 @@ #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) +#define MXC_CSPICTRL_TC (1 << 8) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPICTRL_MAXBITS 0x1f #define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 4 static unsigned long spi_bases[] = { 0x43fa4000, @@ -65,13 +60,80 @@ static unsigned long spi_bases[] = { 0x53f84000, }; +#elif defined(CONFIG_MX51) + +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) +#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) +#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) +#define MXC_CSPICTRL_MAXBITS 0xfff +#define MXC_CSPICTRL_TC (1 << 7) +#define MXC_CSPICTRL_RXOVF (1 << 6) + +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 32 + +/* Bit position inside CTRL register to be associated with SS */ +#define MXC_CSPICTRL_CHAN 18 + +/* Bit position inside CON register to be associated with SS */ +#define MXC_CSPICON_POL 4 +#define MXC_CSPICON_PHA 0 +#define MXC_CSPICON_SSPOL 12 + +static unsigned long spi_bases[] = { + CSPI1_BASE_ADDR, + CSPI2_BASE_ADDR, + CSPI3_BASE_ADDR, +}; + +#elif defined(CONFIG_MX35) + +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_SMC (1 << 3) +#define MXC_CSPICTRL_POL (1 << 4) +#define MXC_CSPICTRL_PHA (1 << 5) +#define MXC_CSPICTRL_SSCTL (1 << 6) +#define MXC_CSPICTRL_SSPOL (1 << 7) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) +#define MXC_CSPICTRL_TC (1 << 7) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPICTRL_MAXBITS 0xfff + +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 4 + +static unsigned long spi_bases[] = { + 0x43fa4000, + 0x50010000, +}; + +#else +#error "Unsupported architecture" #endif +#define OUT MXC_GPIO_DIRECTION_OUT + +#define reg_read readl +#define reg_write(a, v) writel(v, a) + struct mxc_spi_slave { struct spi_slave slave; unsigned long base; u32 ctrl_reg; +#if defined(CONFIG_MX51) + u32 cfg_reg; +#endif int gpio; + int ss_pol; }; static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) @@ -79,70 +141,309 @@ static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) return container_of(slave, struct mxc_spi_slave, slave); } -static inline u32 reg_read(unsigned long addr) +void spi_cs_activate(struct spi_slave *slave) { - return *(volatile unsigned long*)addr; + struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); + if (mxcs->gpio > 0) + mxc_gpio_set(mxcs->gpio, mxcs->ss_pol); } -static inline void reg_write(unsigned long addr, u32 val) +void spi_cs_deactivate(struct spi_slave *slave) { - *(volatile unsigned long*)addr = val; + struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); + if (mxcs->gpio > 0) + mxc_gpio_set(mxcs->gpio, + !(mxcs->ss_pol)); +} + +u32 get_cspi_div(u32 div) +{ + int i; + + for (i = 0; i < 8; i++) { + if (div <= (4 << i)) + return i; + } + return i; +} + +#if defined(CONFIG_MX31) || defined(CONFIG_MX35) +static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + unsigned int ctrl_reg; + u32 clk_src; + u32 div; + + clk_src = mxc_get_clock(MXC_CSPI_CLK); + + div = clk_src / max_hz; + div = get_cspi_div(div); + + debug("clk %d Hz, div %d, real clk %d Hz\n", + max_hz, div, clk_src / (4 << div)); + + ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | + MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) | + MXC_CSPICTRL_DATARATE(div) | + MXC_CSPICTRL_EN | +#ifdef CONFIG_MX35 + MXC_CSPICTRL_SSCTL | +#endif + MXC_CSPICTRL_MODE; + + if (mode & SPI_CPHA) + ctrl_reg |= MXC_CSPICTRL_PHA; + if (mode & SPI_CPOL) + ctrl_reg |= MXC_CSPICTRL_POL; + if (mode & SPI_CS_HIGH) + ctrl_reg |= MXC_CSPICTRL_SSPOL; + mxcs->ctrl_reg = ctrl_reg; + + return 0; } +#endif -static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen, - unsigned long flags) +#if defined(CONFIG_MX51) +static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); + s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config; + u32 ss_pol = 0, sclkpol = 0, sclkpha = 0; + struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; + + if (max_hz == 0) { + printf("Error: desired clock is 0\n"); + return -1; + } + + reg_ctrl = reg_read(®s->ctrl); + + /* Reset spi */ + reg_write(®s->ctrl, 0); + reg_write(®s->ctrl, (reg_ctrl | 0x1)); + + /* + * The following computation is taken directly from Freescale's code. + */ + if (clk_src > max_hz) { + pre_div = clk_src / max_hz; + if (pre_div > 16) { + post_div = pre_div / 16; + pre_div = 15; + } + if (post_div != 0) { + for (i = 0; i < 16; i++) { + if ((1 << i) >= post_div) + break; + } + if (i == 16) { + printf("Error: no divider for the freq: %d\n", + max_hz); + return -1; + } + post_div = i; + } + } + + debug("pre_div = %d, post_div=%d\n", pre_div, post_div); + reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | + MXC_CSPICTRL_SELCHAN(cs); + reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | + MXC_CSPICTRL_PREDIV(pre_div); + reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | + MXC_CSPICTRL_POSTDIV(post_div); + + /* always set to master mode */ + reg_ctrl |= 1 << (cs + 4); + + /* We need to disable SPI before changing registers */ + reg_ctrl &= ~MXC_CSPICTRL_EN; + + if (mode & SPI_CS_HIGH) + ss_pol = 1; + + if (mode & SPI_CPOL) + sclkpol = 1; + + if (mode & SPI_CPHA) + sclkpha = 1; + + reg_config = reg_read(®s->cfg); + + /* + * Configuration register setup + * The MX51 supports different setup for each SS + */ + reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) | + (ss_pol << (cs + MXC_CSPICON_SSPOL)); + reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) | + (sclkpol << (cs + MXC_CSPICON_POL)); + reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) | + (sclkpha << (cs + MXC_CSPICON_PHA)); + + debug("reg_ctrl = 0x%x\n", reg_ctrl); + reg_write(®s->ctrl, reg_ctrl); + debug("reg_config = 0x%x\n", reg_config); + reg_write(®s->cfg, reg_config); + + /* save config register and control register */ + mxcs->ctrl_reg = reg_ctrl; + mxcs->cfg_reg = reg_config; + + /* clear interrupt reg */ + reg_write(®s->intr, 0); + reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); + + return 0; +} +#endif + +int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, + const u8 *dout, u8 *din, unsigned long flags) { struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); - unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL); + int nbytes = (bitlen + 7) / 8; + u32 data, cnt, i; + struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; + + debug("%s: bitlen %d dout 0x%x din 0x%x\n", + __func__, bitlen, (u32)dout, (u32)din); - mxcs->ctrl_reg = (mxcs->ctrl_reg & ~MXC_CSPICTRL_BITCOUNT(31)) | + mxcs->ctrl_reg = (mxcs->ctrl_reg & + ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | MXC_CSPICTRL_BITCOUNT(bitlen - 1); - if (cfg_reg != mxcs->ctrl_reg) - reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg); + reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN); +#ifdef CONFIG_MX51 + reg_write(®s->cfg, mxcs->cfg_reg); +#endif + + /* Clear interrupt register */ + reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); + + /* + * The SPI controller works only with words, + * check if less than a word is sent. + * Access to the FIFO is only 32 bit + */ + if (bitlen % 32) { + data = 0; + cnt = (bitlen % 32) / 8; + if (dout) { + for (i = 0; i < cnt; i++) { + data = (data << 8) | (*dout++ & 0xFF); + } + } + debug("Sending SPI 0x%x\n", data); - if (mxcs->gpio > 0 && (flags & SPI_XFER_BEGIN)) - mx31_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL); + reg_write(®s->txdata, data); + nbytes -= cnt; + } - reg_write(mxcs->base + MXC_CSPITXDATA, data); + data = 0; + + while (nbytes > 0) { + data = 0; + if (dout) { + /* Buffer is not 32-bit aligned */ + if ((unsigned long)dout & 0x03) { + data = 0; + for (i = 0; i < 4; i++) + data = (data << 8) | (*dout++ & 0xFF); + } else { + data = *(u32 *)dout; + data = cpu_to_be32(data); + } + dout += 4; + } + debug("Sending SPI 0x%x\n", data); + reg_write(®s->txdata, data); + nbytes -= 4; + } - reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_XCH); + /* FIFO is written, now starts the transfer setting the XCH bit */ + reg_write(®s->ctrl, mxcs->ctrl_reg | + MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH); - while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH) + /* Wait until the TC (Transfer completed) bit is set */ + while ((reg_read(®s->stat) & MXC_CSPICTRL_TC) == 0) ; - if (mxcs->gpio > 0 && (flags & SPI_XFER_END)) { - mx31_gpio_set(mxcs->gpio, - !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL)); + /* Transfer completed, clear any pending request */ + reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); + + nbytes = (bitlen + 7) / 8; + + cnt = nbytes % 32; + + if (bitlen % 32) { + data = reg_read(®s->rxdata); + cnt = (bitlen % 32) / 8; + data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8); + debug("SPI Rx unaligned: 0x%x\n", data); + if (din) { + memcpy(din, &data, cnt); + din += cnt; + } + nbytes -= cnt; } - return reg_read(mxcs->base + MXC_CSPIRXDATA); + while (nbytes > 0) { + u32 tmp; + tmp = reg_read(®s->rxdata); + data = cpu_to_be32(tmp); + debug("SPI Rx: 0x%x 0x%x\n", tmp, data); + cnt = min(nbytes, sizeof(data)); + if (din) { + memcpy(din, &data, cnt); + din += cnt; + } + nbytes -= cnt; + } + + return 0; + } int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { - int n_blks = (bitlen + 31) / 32; - u32 *out_l, *in_l; - int i; + int n_bytes = (bitlen + 7) / 8; + int n_bits; + int ret; + u32 blk_size; + u8 *p_outbuf = (u8 *)dout; + u8 *p_inbuf = (u8 *)din; + + if (!slave) + return -1; + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + while (n_bytes > 0) { + if (n_bytes < MAX_SPI_BYTES) + blk_size = n_bytes; + else + blk_size = MAX_SPI_BYTES; + + n_bits = blk_size * 8; + + ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0); - if ((int)dout & 3 || (int)din & 3) { - printf("Error: unaligned buffers in: %p, out: %p\n", din, dout); - return 1; + if (ret) + return ret; + if (dout) + p_outbuf += blk_size; + if (din) + p_inbuf += blk_size; + n_bytes -= blk_size; } - for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout; - i < n_blks; - i++, in_l++, out_l++, bitlen -= 32) { - u32 data = spi_xchg_single(slave, *out_l, bitlen, flags); - - /* Check if we're only transfering 8 or 16 bits */ - if (!i) { - if (bitlen < 9) - *(u8 *)din = data; - else if (bitlen < 17) - *(u16 *)din = data; - } + if (flags & SPI_XFER_END) { + spi_cs_deactivate(slave); } return 0; @@ -167,7 +468,7 @@ static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs) if (cs > 3) { mxcs->gpio = cs >> 8; cs &= 3; - ret = mx31_gpio_direction(mxcs->gpio, MX31_GPIO_DIRECTION_OUT); + ret = mxc_gpio_direction(mxcs->gpio, OUT); if (ret) { printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio); return -EINVAL; @@ -182,7 +483,6 @@ static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs) struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { - unsigned int ctrl_reg; struct mxc_spi_slave *mxcs; int ret; @@ -190,8 +490,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return NULL; mxcs = malloc(sizeof(struct mxc_spi_slave)); - if (!mxcs) + if (!mxcs) { + puts("mxc_spi: SPI Slave not allocated !\n"); return NULL; + } ret = decode_cs(mxcs, cs); if (ret < 0) { @@ -201,24 +503,17 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, cs = ret; - ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | - MXC_CSPICTRL_BITCOUNT(31) | - MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */ - MXC_CSPICTRL_EN | - MXC_CSPICTRL_MODE; - - if (mode & SPI_CPHA) - ctrl_reg |= MXC_CSPICTRL_PHA; - if (!(mode & SPI_CPOL)) - ctrl_reg |= MXC_CSPICTRL_POL; - if (mode & SPI_CS_HIGH) - ctrl_reg |= MXC_CSPICTRL_SSPOL; - mxcs->slave.bus = bus; mxcs->slave.cs = cs; mxcs->base = spi_bases[bus]; - mxcs->ctrl_reg = ctrl_reg; + mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; + ret = spi_cfg_mxc(mxcs, cs, max_hz, mode); + if (ret) { + printf("mxc_spi: cannot setup SPI controller\n"); + free(mxcs); + return NULL; + } return &mxcs->slave; } @@ -232,13 +527,13 @@ void spi_free_slave(struct spi_slave *slave) int spi_claim_bus(struct spi_slave *slave) { struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); + struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; - reg_write(mxcs->base + MXC_CSPIRESET, 1); + reg_write(®s->rxdata, 1); udelay(1); - reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg); - reg_write(mxcs->base + MXC_CSPIPERIOD, - MXC_CSPIPERIOD_32KHZ); - reg_write(mxcs->base + MXC_CSPIINT, 0); + reg_write(®s->ctrl, mxcs->ctrl_reg); + reg_write(®s->period, MXC_CSPIPERIOD_32KHZ); + reg_write(®s->intr, 0); return 0; } |