diff options
Diffstat (limited to 'drivers/qe/uec.h')
| -rw-r--r-- | drivers/qe/uec.h | 56 |
1 files changed, 52 insertions, 4 deletions
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h index 0b64499..1568310 100644 --- a/drivers/qe/uec.h +++ b/drivers/qe/uec.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. * * Dave Liu <daveliu@freescale.com> * based on source code of Shlomi Gridish @@ -47,6 +47,7 @@ #define UPSMR_CAM 0x00000400 /* CAM Address Matching */ #define UPSMR_BRO 0x00000200 /* Broadcast Address */ #define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */ +#define UPSMR_SGMM 0x00000020 /* SGMII mode */ #define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1) @@ -621,6 +622,31 @@ typedef enum enet_tbi_mii_reg { ENET_TBI_MII_TBICON = 0x11 } enet_tbi_mii_reg_e; +/* TBI MDIO register bit fields*/ +#define TBICON_CLK_SELECT 0x0020 +#define TBIANA_ASYMMETRIC_PAUSE 0x0100 +#define TBIANA_SYMMETRIC_PAUSE 0x0080 +#define TBIANA_HALF_DUPLEX 0x0040 +#define TBIANA_FULL_DUPLEX 0x0020 +#define TBICR_PHY_RESET 0x8000 +#define TBICR_ANEG_ENABLE 0x1000 +#define TBICR_RESTART_ANEG 0x0200 +#define TBICR_FULL_DUPLEX 0x0100 +#define TBICR_SPEED1_SET 0x0040 + +#define TBIANA_SETTINGS ( \ + TBIANA_ASYMMETRIC_PAUSE \ + | TBIANA_SYMMETRIC_PAUSE \ + | TBIANA_FULL_DUPLEX \ + ) + +#define TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_ANEG_ENABLE \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) + /* UEC number of threads */ typedef enum uec_num_of_threads { @@ -645,17 +671,36 @@ typedef enum enet_interface { ENET_1000_RGMII_ID, ENET_1000_RGMII_RXID, ENET_1000_TBI, - ENET_1000_RTBI + ENET_1000_RTBI, + ENET_1000_SGMII } enet_interface_e; /* UEC initialization info struct */ +#define STD_UEC_INFO(num) \ +{ \ + .uf_info = { \ + .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\ + .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \ + .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \ + .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\ + }, \ + .num_threads_tx = UEC_NUM_OF_THREADS_1, \ + .num_threads_rx = UEC_NUM_OF_THREADS_1, \ + .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \ + .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \ + .tx_bd_ring_len = 16, \ + .rx_bd_ring_len = 16, \ + .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \ + .enet_interface = CONFIG_SYS_UEC##num##_INTERFACE_MODE, \ +} + typedef struct uec_info { ucc_fast_info_t uf_info; uec_num_of_threads_e num_threads_tx; uec_num_of_threads_e num_threads_rx; - qe_risc_allocation_e riscTx; - qe_risc_allocation_e riscRx; + unsigned int risc_tx; + unsigned int risc_rx; u16 rx_bd_ring_len; u16 tx_bd_ring_len; u8 phy_address; @@ -716,4 +761,7 @@ typedef struct uec_private { int oldlink; } uec_private_t; +int uec_initialize(bd_t *bis, uec_info_t *uec_info); +int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num); +int uec_standard_init(bd_t *bis); #endif /* __UEC_H__ */ |