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Diffstat (limited to 'drivers/qe/uec.c')
-rw-r--r--drivers/qe/uec.c224
1 files changed, 60 insertions, 164 deletions
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index bba3ef2..3686575 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
*
@@ -31,146 +31,34 @@
#include "uec_phy.h"
#include "miiphy.h"
+static uec_info_t uec_info[] = {
#ifdef CONFIG_UEC_ETH1
-static uec_info_t eth1_uec_info = {
- .uf_info = {
- .ucc_num = CONFIG_SYS_UEC1_UCC_NUM,
- .rx_clock = CONFIG_SYS_UEC1_RX_CLK,
- .tx_clock = CONFIG_SYS_UEC1_TX_CLK,
- .eth_type = CONFIG_SYS_UEC1_ETH_TYPE,
- },
-#if (CONFIG_SYS_UEC1_ETH_TYPE == FAST_ETH)
- .num_threads_tx = UEC_NUM_OF_THREADS_1,
- .num_threads_rx = UEC_NUM_OF_THREADS_1,
-#else
- .num_threads_tx = UEC_NUM_OF_THREADS_4,
- .num_threads_rx = UEC_NUM_OF_THREADS_4,
-#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .tx_bd_ring_len = 16,
- .rx_bd_ring_len = 16,
- .phy_address = CONFIG_SYS_UEC1_PHY_ADDR,
- .enet_interface = CONFIG_SYS_UEC1_INTERFACE_MODE,
-};
+ STD_UEC_INFO(1), /* UEC1 */
#endif
#ifdef CONFIG_UEC_ETH2
-static uec_info_t eth2_uec_info = {
- .uf_info = {
- .ucc_num = CONFIG_SYS_UEC2_UCC_NUM,
- .rx_clock = CONFIG_SYS_UEC2_RX_CLK,
- .tx_clock = CONFIG_SYS_UEC2_TX_CLK,
- .eth_type = CONFIG_SYS_UEC2_ETH_TYPE,
- },
-#if (CONFIG_SYS_UEC2_ETH_TYPE == FAST_ETH)
- .num_threads_tx = UEC_NUM_OF_THREADS_1,
- .num_threads_rx = UEC_NUM_OF_THREADS_1,
-#else
- .num_threads_tx = UEC_NUM_OF_THREADS_4,
- .num_threads_rx = UEC_NUM_OF_THREADS_4,
-#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .tx_bd_ring_len = 16,
- .rx_bd_ring_len = 16,
- .phy_address = CONFIG_SYS_UEC2_PHY_ADDR,
- .enet_interface = CONFIG_SYS_UEC2_INTERFACE_MODE,
-};
+ STD_UEC_INFO(2), /* UEC2 */
#endif
#ifdef CONFIG_UEC_ETH3
-static uec_info_t eth3_uec_info = {
- .uf_info = {
- .ucc_num = CONFIG_SYS_UEC3_UCC_NUM,
- .rx_clock = CONFIG_SYS_UEC3_RX_CLK,
- .tx_clock = CONFIG_SYS_UEC3_TX_CLK,
- .eth_type = CONFIG_SYS_UEC3_ETH_TYPE,
- },
-#if (CONFIG_SYS_UEC3_ETH_TYPE == FAST_ETH)
- .num_threads_tx = UEC_NUM_OF_THREADS_1,
- .num_threads_rx = UEC_NUM_OF_THREADS_1,
-#else
- .num_threads_tx = UEC_NUM_OF_THREADS_4,
- .num_threads_rx = UEC_NUM_OF_THREADS_4,
-#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .tx_bd_ring_len = 16,
- .rx_bd_ring_len = 16,
- .phy_address = CONFIG_SYS_UEC3_PHY_ADDR,
- .enet_interface = CONFIG_SYS_UEC3_INTERFACE_MODE,
-};
+ STD_UEC_INFO(3), /* UEC3 */
#endif
#ifdef CONFIG_UEC_ETH4
-static uec_info_t eth4_uec_info = {
- .uf_info = {
- .ucc_num = CONFIG_SYS_UEC4_UCC_NUM,
- .rx_clock = CONFIG_SYS_UEC4_RX_CLK,
- .tx_clock = CONFIG_SYS_UEC4_TX_CLK,
- .eth_type = CONFIG_SYS_UEC4_ETH_TYPE,
- },
-#if (CONFIG_SYS_UEC4_ETH_TYPE == FAST_ETH)
- .num_threads_tx = UEC_NUM_OF_THREADS_1,
- .num_threads_rx = UEC_NUM_OF_THREADS_1,
-#else
- .num_threads_tx = UEC_NUM_OF_THREADS_4,
- .num_threads_rx = UEC_NUM_OF_THREADS_4,
-#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .tx_bd_ring_len = 16,
- .rx_bd_ring_len = 16,
- .phy_address = CONFIG_SYS_UEC4_PHY_ADDR,
- .enet_interface = CONFIG_SYS_UEC4_INTERFACE_MODE,
-};
+ STD_UEC_INFO(4), /* UEC4 */
#endif
#ifdef CONFIG_UEC_ETH5
-static uec_info_t eth5_uec_info = {
- .uf_info = {
- .ucc_num = CONFIG_SYS_UEC5_UCC_NUM,
- .rx_clock = CONFIG_SYS_UEC5_RX_CLK,
- .tx_clock = CONFIG_SYS_UEC5_TX_CLK,
- .eth_type = CONFIG_SYS_UEC5_ETH_TYPE,
- },
-#if (CONFIG_SYS_UEC5_ETH_TYPE == FAST_ETH)
- .num_threads_tx = UEC_NUM_OF_THREADS_1,
- .num_threads_rx = UEC_NUM_OF_THREADS_1,
-#else
- .num_threads_tx = UEC_NUM_OF_THREADS_4,
- .num_threads_rx = UEC_NUM_OF_THREADS_4,
-#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .tx_bd_ring_len = 16,
- .rx_bd_ring_len = 16,
- .phy_address = CONFIG_SYS_UEC5_PHY_ADDR,
- .enet_interface = CONFIG_SYS_UEC5_INTERFACE_MODE,
-};
+ STD_UEC_INFO(5), /* UEC5 */
#endif
#ifdef CONFIG_UEC_ETH6
-static uec_info_t eth6_uec_info = {
- .uf_info = {
- .ucc_num = CONFIG_SYS_UEC6_UCC_NUM,
- .rx_clock = CONFIG_SYS_UEC6_RX_CLK,
- .tx_clock = CONFIG_SYS_UEC6_TX_CLK,
- .eth_type = CONFIG_SYS_UEC6_ETH_TYPE,
- },
-#if (CONFIG_SYS_UEC6_ETH_TYPE == FAST_ETH)
- .num_threads_tx = UEC_NUM_OF_THREADS_1,
- .num_threads_rx = UEC_NUM_OF_THREADS_1,
-#else
- .num_threads_tx = UEC_NUM_OF_THREADS_4,
- .num_threads_rx = UEC_NUM_OF_THREADS_4,
+ STD_UEC_INFO(6), /* UEC6 */
#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .tx_bd_ring_len = 16,
- .rx_bd_ring_len = 16,
- .phy_address = CONFIG_SYS_UEC6_PHY_ADDR,
- .enet_interface = CONFIG_SYS_UEC6_INTERFACE_MODE,
-};
+#ifdef CONFIG_UEC_ETH7
+ STD_UEC_INFO(7), /* UEC7 */
#endif
+#ifdef CONFIG_UEC_ETH8
+ STD_UEC_INFO(8), /* UEC8 */
+#endif
+};
-#define MAXCONTROLLERS (6)
+#define MAXCONTROLLERS (8)
static struct eth_device *devlist[MAXCONTROLLERS];
@@ -491,6 +379,10 @@ static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
upsmr |= (UPSMR_R10M | UPSMR_RMM);
break;
+ case ENET_1000_SGMII:
+ maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
+ upsmr |= UPSMR_SGMM;
+ break;
default:
return -EINVAL;
break;
@@ -1020,7 +912,7 @@ static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
/* Init Rx global parameter pointer */
p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
- (u32)uec_info->riscRx;
+ (u32)uec_info->risc_rx;
/* Init Rx threads */
for (i = 0; i < (thread_rx + 1); i++) {
@@ -1038,13 +930,13 @@ static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
}
entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
- init_enet_offset | (u32)uec_info->riscRx;
+ init_enet_offset | (u32)uec_info->risc_rx;
p_init_enet_param->rxthread[i] = entry_val;
}
/* Init Tx global parameter pointer */
p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
- (u32)uec_info->riscTx;
+ (u32)uec_info->risc_tx;
/* Init Tx threads */
for (i = 0; i < thread_tx; i++) {
@@ -1057,7 +949,7 @@ static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
UEC_THREAD_TX_PRAM_ALIGNMENT);
entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
- init_enet_offset | (u32)uec_info->riscTx;
+ init_enet_offset | (u32)uec_info->risc_tx;
p_init_enet_param->txthread[i] = entry_val;
}
@@ -1190,6 +1082,18 @@ static int uec_startup(uec_private_t *uec)
out_be32(&uec_regs->utbipar, utbipar);
+ /* Configure the TBI for SGMII operation */
+ if (uec->uec_info->enet_interface == ENET_1000_SGMII) {
+ uec_write_phy_reg(uec->dev, uec_regs->utbipar,
+ ENET_TBI_MII_ANA, TBIANA_SETTINGS);
+
+ uec_write_phy_reg(uec->dev, uec_regs->utbipar,
+ ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
+
+ uec_write_phy_reg(uec->dev, uec_regs->utbipar,
+ ENET_TBI_MII_CR, TBICR_SETTINGS);
+ }
+
/* Allocate Tx BDs */
length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
@@ -1417,12 +1321,11 @@ static int uec_recv(struct eth_device* dev)
return 1;
}
-int uec_initialize(int index)
+int uec_initialize(bd_t *bis, uec_info_t *uec_info)
{
struct eth_device *dev;
int i;
uec_private_t *uec;
- uec_info_t *uec_info;
int err;
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
@@ -1437,42 +1340,18 @@ int uec_initialize(int index)
}
memset(uec, 0, sizeof(uec_private_t));
- /* Init UEC private struct, they come from board.h */
- uec_info = NULL;
- if (index == 0) {
-#ifdef CONFIG_UEC_ETH1
- uec_info = &eth1_uec_info;
-#endif
- } else if (index == 1) {
-#ifdef CONFIG_UEC_ETH2
- uec_info = &eth2_uec_info;
-#endif
- } else if (index == 2) {
-#ifdef CONFIG_UEC_ETH3
- uec_info = &eth3_uec_info;
-#endif
- } else if (index == 3) {
-#ifdef CONFIG_UEC_ETH4
- uec_info = &eth4_uec_info;
+ /* Adjust uec_info */
+#if (MAX_QE_RISC == 4)
+ uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS;
+ uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS;
#endif
- } else if (index == 4) {
-#ifdef CONFIG_UEC_ETH5
- uec_info = &eth5_uec_info;
-#endif
- } else if (index == 5) {
-#ifdef CONFIG_UEC_ETH6
- uec_info = &eth6_uec_info;
-#endif
- } else {
- printf("%s: index is illegal.\n", __FUNCTION__);
- return -EINVAL;
- }
- devlist[index] = dev;
+ devlist[uec_info->uf_info.ucc_num] = dev;
uec->uec_info = uec_info;
+ uec->dev = dev;
- sprintf(dev->name, "FSL UEC%d", index);
+ sprintf(dev->name, "FSL UEC%d", uec_info->uf_info.ucc_num);
dev->iobase = 0;
dev->priv = (void *)uec;
dev->init = uec_init;
@@ -1499,3 +1378,20 @@ int uec_initialize(int index)
return 1;
}
+
+int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num)
+{
+ int i;
+
+ for (i = 0; i < num; i++)
+ uec_initialize(bis, &uecs[i]);
+
+ return 0;
+}
+
+int uec_standard_init(bd_t *bis)
+{
+ return uec_eth_init(bis, uec_info, ARRAY_SIZE(uec_info));
+}
+
+
generated by cgit v1.1 at 2024-12-24 17:06:01 +0000