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-rw-r--r--drivers/pci/fsl_pci_init.c17
-rw-r--r--drivers/pci/pci.c2
-rw-r--r--drivers/pci/pci_auto.c8
-rw-r--r--drivers/pci/pci_sh7751.c24
-rw-r--r--drivers/pci/pci_sh7780.c15
-rw-r--r--drivers/pci/tsi108_pci.c38
-rw-r--r--drivers/pci/w83c553f.c4
7 files changed, 63 insertions, 45 deletions
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index bb2813f..38a16e5 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -168,8 +168,21 @@ fsl_pci_init(struct pci_controller *hose)
}
#ifndef CONFIG_PCI_NOSCAN
- printf (" Scanning PCI bus %02x\n", hose->current_busno);
- hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno);
+ pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8);
+
+ /* Programming Interface (PCI_CLASS_PROG)
+ * 0 == pci host or pcie root-complex,
+ * 1 == pci agent or pcie end-point
+ */
+ if (!temp8) {
+ printf(" Scanning PCI bus %02x\n",
+ hose->current_busno);
+ hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
+ } else {
+ debug(" Not scanning PCI bus %02x. PI=%x\n",
+ hose->current_busno, temp8);
+ hose->last_busno = hose->current_busno;
+ }
if ( bridge ) { /* update limit regs and subordinate busno */
pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index b5eea89..41780db 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -157,7 +157,7 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
for (hose = hose_head; hose; hose = hose->next)
{
-#ifdef CFG_SCSI_SCAN_BUS_REVERSE
+#ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
#else
for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 2acf9bf..3844359 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -26,9 +26,9 @@
#define PCIAUTO_IDE_MODE_MASK 0x05
-/* the user can define CFG_PCI_CACHE_LINE_SIZE to avoid problems */
-#ifndef CFG_PCI_CACHE_LINE_SIZE
-#define CFG_PCI_CACHE_LINE_SIZE 8
+/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
+#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
+#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
#endif
/*
@@ -154,7 +154,7 @@ void pciauto_setup_device(struct pci_controller *hose,
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
- CFG_PCI_CACHE_LINE_SIZE);
+ CONFIG_SYS_PCI_CACHE_LINE_SIZE);
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
}
diff --git a/drivers/pci/pci_sh7751.c b/drivers/pci/pci_sh7751.c
index a058e1d..e3a0ea0 100644
--- a/drivers/pci/pci_sh7751.c
+++ b/drivers/pci/pci_sh7751.c
@@ -23,18 +23,19 @@
*/
#include <common.h>
+#include <pci.h>
#include <asm/processor.h>
#include <asm/io.h>
-#include <pci.h>
+#include <asm/pci.h>
/* Register addresses and such */
#define SH7751_BCR1 (vu_long *)0xFF800000
-#define SH7751_BCR2 (vu_short*)0xFF800004
+#define SH7751_BCR2 (vu_short *)0xFF800004
#define SH7751_WCR1 (vu_long *)0xFF800008
#define SH7751_WCR2 (vu_long *)0xFF80000C
#define SH7751_WCR3 (vu_long *)0xFF800010
#define SH7751_MCR (vu_long *)0xFF800014
-#define SH7751_BCR3 (vu_short*)0xFF800050
+#define SH7751_BCR3 (vu_short *)0xFF800050
#define SH7751_PCICONF0 (vu_long *)0xFE200000
#define SH7751_PCICONF1 (vu_long *)0xFE200004
#define SH7751_PCICONF2 (vu_long *)0xFE200008
@@ -87,12 +88,12 @@
#define SH7751_PCIPAR (vu_long *)0xFE2001C0
#define SH7751_PCIPDR (vu_long *)0xFE200220
-#define p4_in(addr) *(addr)
-#define p4_out(data,addr) *(addr) = (data)
+#define p4_in(addr) (*addr)
+#define p4_out(data, addr) (*addr) = (data)
/* Double word */
int pci_sh4_read_config_dword(struct pci_controller *hose,
- pci_dev_t dev, int offset, u32 * value)
+ pci_dev_t dev, int offset, u32 *value)
{
u32 par_data = 0x80000000 | dev;
@@ -103,7 +104,7 @@ int pci_sh4_read_config_dword(struct pci_controller *hose,
}
int pci_sh4_write_config_dword(struct pci_controller *hose,
- pci_dev_t dev, int offset, u32 * value)
+ pci_dev_t dev, int offset, u32 value)
{
u32 par_data = 0x80000000 | dev;
@@ -126,15 +127,18 @@ int pci_sh7751_init(struct pci_controller *hose)
/* Double-check some BSC config settings */
/* (Area 3 non-MPX 32-bit, PCI bus pins) */
if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) {
- printf("SH7751_BCR1 0x%08X\n", p4_in(SH7751_BCR1));
+ printf("SH7751_BCR1 value is wrong(0x%08X)\n",
+ (unsigned int)p4_in(SH7751_BCR1));
return 2;
}
if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) {
- printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2));
+ printf("SH7751_BCR2 value is wrong(0x%08X)\n",
+ (unsigned int)p4_in(SH7751_BCR2));
return 3;
}
if (p4_in(SH7751_BCR2) & 0x01) {
- printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2));
+ printf("SH7751_BCR2 value is wrong(0x%08X)\n",
+ (unsigned int)p4_in(SH7751_BCR2));
return 4;
}
diff --git a/drivers/pci/pci_sh7780.c b/drivers/pci/pci_sh7780.c
index 2d04b4f..7555d96 100644
--- a/drivers/pci/pci_sh7780.c
+++ b/drivers/pci/pci_sh7780.c
@@ -25,9 +25,10 @@
#include <common.h>
+#include <pci.h>
#include <asm/processor.h>
+#include <asm/pci.h>
#include <asm/io.h>
-#include <pci.h>
#define SH7780_VENDOR_ID 0x1912
#define SH7780_DEVICE_ID 0x0002
@@ -41,10 +42,10 @@
#define SH7780_PCICR_PRST 0x00000002
#define SH7780_PCICR_CFIN 0x00000001
-#define p4_in(addr) *((vu_long *)addr)
-#define p4_out(data,addr) *(vu_long *)(addr) = (data)
-#define p4_inw(addr) *((vu_short *)addr)
-#define p4_outw(data,addr) *(vu_short *)(addr) = (data)
+#define p4_in(addr) (*(vu_long *)addr)
+#define p4_out(data, addr) (*(vu_long *)addr) = (data)
+#define p4_inw(addr) (*(vu_short *)addr)
+#define p4_outw(data, addr) (*(vu_short *)addr) = (data)
int pci_sh4_read_config_dword(struct pci_controller *hose,
pci_dev_t dev, int offset, u32 *value)
@@ -72,9 +73,9 @@ int pci_sh7780_init(struct pci_controller *hose)
p4_out(0x01, SH7780_PCIECR);
if (p4_inw(SH7780_PCIVID) != SH7780_VENDOR_ID
- && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID){
+ && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID) {
printf("PCI: Unknown PCI host bridge.\n");
- return;
+ return -1;
}
printf("PCI: SH7780 PCI host bridge found.\n");
diff --git a/drivers/pci/tsi108_pci.c b/drivers/pci/tsi108_pci.c
index edd614f..d153fc6 100644
--- a/drivers/pci/tsi108_pci.c
+++ b/drivers/pci/tsi108_pci.c
@@ -47,32 +47,32 @@ void tsi108_clear_pci_error (void)
* requests.
*/
/* Read PB Error Log Registers */
- err_stat = *(volatile u32 *)(CFG_TSI108_CSR_BASE +
+ err_stat = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
TSI108_PB_REG_OFFSET + PB_ERRCS);
- err_addr = *(volatile u32 *)(CFG_TSI108_CSR_BASE +
+ err_addr = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
TSI108_PB_REG_OFFSET + PB_AERR);
if (err_stat & PB_ERRCS_ES) {
/* Clear PCI/X bus errors if applicable */
- if ((err_addr & 0xFF000000) == CFG_PCI_CFG_BASE) {
+ if ((err_addr & 0xFF000000) == CONFIG_SYS_PCI_CFG_BASE) {
/* Clear error flag */
- *(u32 *) (CFG_TSI108_CSR_BASE +
+ *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE +
TSI108_PB_REG_OFFSET + PB_ERRCS) =
PB_ERRCS_ES;
/* Clear read error reported in PB_ISR */
- *(u32 *) (CFG_TSI108_CSR_BASE +
+ *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE +
TSI108_PB_REG_OFFSET + PB_ISR) =
PB_ISR_PBS_RD_ERR;
/* Clear errors reported by PCI CSR (Normally Master Abort) */
- pci_stat = *(volatile u32 *)(CFG_TSI108_CSR_BASE +
+ pci_stat = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
TSI108_PCI_REG_OFFSET +
PCI_CSR);
- *(volatile u32 *)(CFG_TSI108_CSR_BASE +
+ *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
TSI108_PCI_REG_OFFSET + PCI_CSR) =
pci_stat;
- *(volatile u32 *)(CFG_TSI108_CSR_BASE +
+ *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
TSI108_PCI_REG_OFFSET +
PCI_IRP_STAT) = PCI_IRP_STAT_P_CSR;
}
@@ -102,8 +102,8 @@ unsigned int __get_pci_config_dword (u32 addr)
static int tsi108_read_config_dword (struct pci_controller *hose,
pci_dev_t dev, int offset, u32 * value)
{
- dev &= (CFG_PCI_CFG_SIZE - 1);
- dev |= (CFG_PCI_CFG_BASE | (offset & 0xfc));
+ dev &= (CONFIG_SYS_PCI_CFG_SIZE - 1);
+ dev |= (CONFIG_SYS_PCI_CFG_BASE | (offset & 0xfc));
*value = __get_pci_config_dword(dev);
if (0xFFFFFFFF == *value)
tsi108_clear_pci_error ();
@@ -113,8 +113,8 @@ static int tsi108_read_config_dword (struct pci_controller *hose,
static int tsi108_write_config_dword (struct pci_controller *hose,
pci_dev_t dev, int offset, u32 value)
{
- dev &= (CFG_PCI_CFG_SIZE - 1);
- dev |= (CFG_PCI_CFG_BASE | (offset & 0xfc));
+ dev &= (CONFIG_SYS_PCI_CFG_SIZE - 1);
+ dev |= (CONFIG_SYS_PCI_CFG_BASE | (offset & 0xfc));
out_le32 ((volatile unsigned *)dev, value);
@@ -129,19 +129,19 @@ void pci_init_board (void)
hose->last_busno = 0xff;
pci_set_region (hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY);
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI memory space */
pci_set_region (hose->regions + 1,
- CFG_PCI_MEM_BUS,
- CFG_PCI_MEM_PHYS, CFG_PCI_MEM_SIZE, PCI_REGION_MEM);
+ CONFIG_SYS_PCI_MEM_BUS,
+ CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region (hose->regions + 2,
- CFG_PCI_IO_BUS,
- CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO);
+ CONFIG_SYS_PCI_IO_BUS,
+ CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
hose->region_count = 3;
diff --git a/drivers/pci/w83c553f.c b/drivers/pci/w83c553f.c
index d7355a4..8561422 100644
--- a/drivers/pci/w83c553f.c
+++ b/drivers/pci/w83c553f.c
@@ -42,7 +42,7 @@
out_be16((u16*) (addr),(val)); udelay(1); \
} while (0)
-extern uint ide_bus_offset[CFG_IDE_MAXBUS];
+extern uint ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
void initialise_pic(void);
void initialise_dma(void);
@@ -105,7 +105,7 @@ void initialise_w83c553f(void)
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]);
ide_bus_offset[0] &= ~1;
-#if CFG_IDE_MAXBUS > 1
+#if CONFIG_SYS_IDE_MAXBUS > 1
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, &ide_bus_offset[1]);
ide_bus_offset[1] &= ~1;
#endif
generated by cgit v1.1 at 2024-12-28 18:14:00 +0000