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-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/fm/Makefile6
-rw-r--r--drivers/net/fm/eth.c41
-rw-r--r--drivers/net/fm/init.c18
-rw-r--r--drivers/net/fm/memac.c132
-rw-r--r--drivers/net/fm/memac_phy.c150
-rw-r--r--drivers/net/fm/p1023.c2
-rw-r--r--drivers/net/fm/p4080.c2
-rw-r--r--drivers/net/fm/p5020.c2
-rw-r--r--drivers/net/fm/t4240.c128
-rw-r--r--drivers/net/fm/tgec_phy.c10
-rw-r--r--drivers/net/macb.c2
-rw-r--r--drivers/net/mcfmii.c4
-rw-r--r--drivers/net/netarm_eth.c352
-rw-r--r--drivers/net/netarm_eth.h42
-rw-r--r--drivers/net/phy/atheros.c2
-rw-r--r--drivers/net/phy/phy.c19
-rw-r--r--drivers/net/phy/vitesse.c2
-rw-r--r--drivers/net/smc91111.c2
-rw-r--r--drivers/net/vsc7385.c1
20 files changed, 494 insertions, 424 deletions
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index e4abac7..786a656 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -59,7 +59,6 @@ COBJS-$(CONFIG_MVGBE) += mvgbe.o
COBJS-$(CONFIG_NATSEMI) += natsemi.o
COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
-COBJS-$(CONFIG_DRIVER_NETARMETH) += netarm_eth.o
COBJS-$(CONFIG_NETCONSOLE) += netconsole.o
COBJS-$(CONFIG_NS8382X) += ns8382x.o
COBJS-$(CONFIG_PCNET) += pcnet.o
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index cc57354..7a1fcdd 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -32,6 +32,10 @@ COBJS-y += init.o
COBJS-y += tgec.o
COBJS-y += tgec_phy.o
+# Soc have FMAN v3 with mEMAC
+COBJS-$(CONFIG_SYS_FMAN_V3) += memac_phy.o
+COBJS-$(CONFIG_SYS_FMAN_V3) += memac.o
+
# SoC specific SERDES support
COBJS-$(CONFIG_P1017) += p1023.o
COBJS-$(CONFIG_P1023) += p1023.o
@@ -40,6 +44,8 @@ COBJS-$(CONFIG_PPC_P2041) += p5020.o
COBJS-$(CONFIG_PPC_P3041) += p5020.o
COBJS-$(CONFIG_PPC_P4080) += p4080.o
COBJS-$(CONFIG_PPC_P5020) += p5020.o
+COBJS-$(CONFIG_PPC_T4240) += t4240.o
+COBJS-$(CONFIG_PPC_B4860) += b4860.o
endif
COBJS := $(COBJS-y)
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 2b616ad..54b142f 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ * Copyright 2009-2012 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* This program is free software; you can redistribute it and/or
@@ -28,6 +28,7 @@
#include <phy.h>
#include <asm/fsl_dtsec.h>
#include <asm/fsl_tgec.h>
+#include <asm/fsl_memac.h>
#include "fm.h"
@@ -45,8 +46,30 @@ static int num_controllers;
TBICR_FULL_DUPLEX | TBICR_SPEED1_SET)
/* Configure the TBI for SGMII operation */
-void dtsec_configure_serdes(struct fm_eth *priv)
+static void dtsec_configure_serdes(struct fm_eth *priv)
{
+#ifdef CONFIG_SYS_FMAN_V3
+ u32 value;
+ struct mii_dev bus;
+ bus.priv = priv->mac->phyregs;
+
+ /* SGMII IF mode + AN enable */
+ value = PHY_SGMII_IF_MODE_AN | PHY_SGMII_IF_MODE_SGMII;
+ memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
+
+ /* Dev ability according to SGMII specification */
+ value = PHY_SGMII_DEV_ABILITY_SGMII;
+ memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
+
+ /* Adjust link timer for SGMII -
+ 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
+ memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x3);
+ memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
+
+ /* Restart AN */
+ value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
+ memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
+#else
struct dtsec *regs = priv->mac->base;
struct tsec_mii_mng *phyregs = priv->mac->phyregs;
@@ -60,15 +83,18 @@ void dtsec_configure_serdes(struct fm_eth *priv)
TBIANA_SGMII_ACK);
tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0,
TBI_CR, TBICR_SETTINGS);
+#endif
}
static void dtsec_init_phy(struct eth_device *dev)
{
struct fm_eth *fm_eth = dev->priv;
- struct dtsec *regs = (struct dtsec *)fm_eth->mac->base;
+#ifndef CONFIG_SYS_FMAN_V3
+ struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
/* Assign a Physical address to the TBI */
out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);
+#endif
if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII)
dtsec_configure_serdes(fm_eth);
@@ -541,6 +567,10 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
num = fm_eth->num;
+#ifdef CONFIG_SYS_FMAN_V3
+ base = &reg->memac[num].fm_memac;
+ phyregs = &reg->memac[num].fm_memac_mdio;
+#else
/* Get the mac registers base address */
if (fm_eth->type == FM_ETH_1G_E) {
base = &reg->mac_1g[num].fm_dtesc;
@@ -549,6 +579,7 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
base = &reg->mac_10g[num].fm_10gec;
phyregs = &reg->mac_10g[num].fm_10gec_mdio;
}
+#endif
/* alloc mac controller */
mac = malloc(sizeof(struct fsl_enet_mac));
@@ -559,10 +590,14 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
/* save the mac to fm_eth struct */
fm_eth->mac = mac;
+#ifdef CONFIG_SYS_FMAN_V3
+ init_memac(mac, base, phyregs, MAX_RXBUF_LEN);
+#else
if (fm_eth->type == FM_ETH_1G_E)
init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
else
init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
+#endif
return 1;
}
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index 736b8b9..ae389b8 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -38,6 +38,15 @@ struct fm_eth_info fm_info[] = {
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 5)
FM_DTSEC_INFO_INITIALIZER(1, 5),
#endif
+#if (CONFIG_SYS_NUM_FM1_DTSEC >= 6)
+ FM_DTSEC_INFO_INITIALIZER(1, 6),
+#endif
+#if (CONFIG_SYS_NUM_FM1_DTSEC >= 7)
+ FM_DTSEC_INFO_INITIALIZER(1, 9),
+#endif
+#if (CONFIG_SYS_NUM_FM1_DTSEC >= 8)
+ FM_DTSEC_INFO_INITIALIZER(1, 10),
+#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 1)
FM_DTSEC_INFO_INITIALIZER(2, 1),
#endif
@@ -53,6 +62,15 @@ struct fm_eth_info fm_info[] = {
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 5)
FM_DTSEC_INFO_INITIALIZER(2, 5),
#endif
+#if (CONFIG_SYS_NUM_FM2_DTSEC >= 6)
+ FM_DTSEC_INFO_INITIALIZER(2, 6),
+#endif
+#if (CONFIG_SYS_NUM_FM2_DTSEC >= 7)
+ FM_DTSEC_INFO_INITIALIZER(2, 9),
+#endif
+#if (CONFIG_SYS_NUM_FM2_DTSEC >= 8)
+ FM_DTSEC_INFO_INITIALIZER(2, 10),
+#endif
#if (CONFIG_SYS_NUM_FM1_10GEC >= 1)
FM_TGEC_INFO_INITIALIZER(1, 1),
#endif
diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
new file mode 100644
index 0000000..32c7054
--- /dev/null
+++ b/drivers/net/fm/memac.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Roy Zang <tie-fei.zang@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* MAXFRM - maximum frame length */
+#define MAXFRM_MASK 0x0000ffff
+
+#include <common.h>
+#include <phy.h>
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/fsl_enet.h>
+#include <asm/fsl_memac.h>
+
+#include "fm.h"
+
+static void memac_init_mac(struct fsl_enet_mac *mac)
+{
+ struct memac *regs = mac->base;
+
+ /* mask all interrupt */
+ out_be32(&regs->imask, IMASK_MASK_ALL);
+
+ /* clear all events */
+ out_be32(&regs->ievent, IEVENT_CLEAR_ALL);
+
+ /* set the max receive length */
+ out_be32(&regs->maxfrm, mac->max_rx_len & MAXFRM_MASK);
+
+ /* multicast frame reception for the hash entry disable */
+ out_be32(&regs->hashtable_ctrl, 0);
+}
+
+static void memac_enable_mac(struct fsl_enet_mac *mac)
+{
+ struct memac *regs = mac->base;
+
+ setbits_be32(&regs->command_config, MEMAC_CMD_CFG_RXTX_EN);
+}
+
+static void memac_disable_mac(struct fsl_enet_mac *mac)
+{
+ struct memac *regs = mac->base;
+
+ clrbits_be32(&regs->command_config, MEMAC_CMD_CFG_RXTX_EN);
+}
+
+static void memac_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr)
+{
+ struct memac *regs = mac->base;
+ u32 mac_addr0, mac_addr1;
+
+ /*
+ * if a station address of 0x12345678ABCD, perform a write to
+ * MAC_ADDR0 of 0x78563412, MAC_ADDR1 of 0x0000CDAB
+ */
+ mac_addr0 = (mac_addr[3] << 24) | (mac_addr[2] << 16) | \
+ (mac_addr[1] << 8) | (mac_addr[0]);
+ out_be32(&regs->mac_addr_0, mac_addr0);
+
+ mac_addr1 = ((mac_addr[5] << 8) | mac_addr[4]) & 0x0000ffff;
+ out_be32(&regs->mac_addr_1, mac_addr1);
+}
+
+static void memac_set_interface_mode(struct fsl_enet_mac *mac,
+ phy_interface_t type, int speed)
+{
+ /* Roy need more work here */
+
+ struct memac *regs = mac->base;
+ u32 if_mode, if_status;
+
+ /* clear all bits relative with interface mode */
+ if_mode = in_be32(&regs->if_mode);
+ if_status = in_be32(&regs->if_status);
+
+ /* set interface mode */
+ switch (type) {
+ case PHY_INTERFACE_MODE_GMII:
+ if_mode &= ~IF_MODE_MASK;
+ if_mode |= IF_MODE_GMII;
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ if_mode |= (IF_MODE_GMII | IF_MODE_RG);
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ if_mode |= (IF_MODE_GMII | IF_MODE_RM);
+ break;
+ case PHY_INTERFACE_MODE_SGMII:
+ if_mode &= ~IF_MODE_MASK;
+ if_mode |= (IF_MODE_GMII);
+ break;
+ default:
+ break;
+ }
+ /* Enable automatic speed selection */
+ if_mode |= IF_MODE_EN_AUTO;
+
+ debug(" %s, if_mode = %x\n", __func__, if_mode);
+ debug(" %s, if_status = %x\n", __func__, if_status);
+ out_be32(&regs->if_mode, if_mode);
+ return;
+}
+
+void init_memac(struct fsl_enet_mac *mac, void *base,
+ void *phyregs, int max_rx_len)
+{
+ mac->base = base;
+ mac->phyregs = phyregs;
+ mac->max_rx_len = max_rx_len;
+ mac->init_mac = memac_init_mac;
+ mac->enable_mac = memac_enable_mac;
+ mac->disable_mac = memac_disable_mac;
+ mac->set_mac_addr = memac_set_mac_addr;
+ mac->set_if_mode = memac_set_interface_mode;
+}
diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c
new file mode 100644
index 0000000..ea6118b
--- /dev/null
+++ b/drivers/net/fm/memac_phy.c
@@ -0,0 +1,150 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Andy Fleming <afleming@freescale.com>
+ * Roy Zang <tie-fei.zang@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ * Some part is taken from tsec.c
+ */
+#include <common.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/io.h>
+#include <asm/fsl_memac.h>
+#include <fm_eth.h>
+
+/*
+ * Write value to the PHY for this device to the register at regnum, waiting
+ * until the write is done before it returns. All PHY configuration has to be
+ * done through the TSEC1 MIIM regs
+ */
+int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
+ int regnum, u16 value)
+{
+ u32 mdio_ctl;
+ struct memac_mdio_controller *regs = bus->priv;
+ u32 c45 = 1; /* Default to 10G interface */
+
+ if (dev_addr == MDIO_DEVAD_NONE) {
+ c45 = 0; /* clause 22 */
+ dev_addr = regnum & 0x1f;
+ clrbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
+ } else {
+ setbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
+ setbits_be32(&regs->mdio_stat, MDIO_STAT_HOLD_15_CLK);
+ }
+
+ /* Wait till the bus is free */
+ while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
+ ;
+
+ /* Set the port and dev addr */
+ mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
+ out_be32(&regs->mdio_ctl, mdio_ctl);
+
+ /* Set the register address */
+ if (c45)
+ out_be32(&regs->mdio_addr, regnum & 0xffff);
+
+ /* Wait till the bus is free */
+ while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
+ ;
+
+ /* Write the value to the register */
+ out_be32(&regs->mdio_data, MDIO_DATA(value));
+
+ /* Wait till the MDIO write is complete */
+ while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY)
+ ;
+
+ return 0;
+}
+
+/*
+ * Reads from register regnum in the PHY for device dev, returning the value.
+ * Clears miimcom first. All PHY configuration has to be done through the
+ * TSEC1 MIIM regs
+ */
+int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
+ int regnum)
+{
+ u32 mdio_ctl;
+ struct memac_mdio_controller *regs = bus->priv;
+ u32 c45 = 1;
+
+ if (dev_addr == MDIO_DEVAD_NONE) {
+ c45 = 0; /* clause 22 */
+ dev_addr = regnum & 0x1f;
+ clrbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
+ } else {
+ setbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
+ setbits_be32(&regs->mdio_stat, MDIO_STAT_HOLD_15_CLK);
+ }
+
+ /* Wait till the bus is free */
+ while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
+ ;
+
+ /* Set the Port and Device Addrs */
+ mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
+ out_be32(&regs->mdio_ctl, mdio_ctl);
+
+ /* Set the register address */
+ if (c45)
+ out_be32(&regs->mdio_addr, regnum & 0xffff);
+
+ /* Wait till the bus is free */
+ while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
+ ;
+
+ /* Initiate the read */
+ mdio_ctl |= MDIO_CTL_READ;
+ out_be32(&regs->mdio_ctl, mdio_ctl);
+
+ /* Wait till the MDIO write is complete */
+ while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY)
+ ;
+
+ /* Return all Fs if nothing was there */
+ if (in_be32(&regs->mdio_stat) & MDIO_STAT_RD_ER)
+ return 0xffff;
+
+ return in_be32(&regs->mdio_data) & 0xffff;
+}
+
+int memac_mdio_reset(struct mii_dev *bus)
+{
+ return 0;
+}
+
+int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
+{
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate FM TGEC MDIO bus\n");
+ return -1;
+ }
+
+ bus->read = memac_mdio_read;
+ bus->write = memac_mdio_write;
+ bus->reset = memac_mdio_reset;
+ sprintf(bus->name, info->name);
+
+ bus->priv = info->regs;
+
+ return mdio_register(bus);
+}
diff --git a/drivers/net/fm/p1023.c b/drivers/net/fm/p1023.c
index 9765da5..387d2a3 100644
--- a/drivers/net/fm/p1023.c
+++ b/drivers/net/fm/p1023.c
@@ -23,7 +23,7 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
-u32 port_to_devdisr[] = {
+static u32 port_to_devdisr[] = {
[FM1_DTSEC1] = MPC85xx_DEVDISR_TSEC1,
[FM1_DTSEC2] = MPC85xx_DEVDISR_TSEC2,
};
diff --git a/drivers/net/fm/p4080.c b/drivers/net/fm/p4080.c
index 9dc6049..b04fd0f 100644
--- a/drivers/net/fm/p4080.c
+++ b/drivers/net/fm/p4080.c
@@ -23,7 +23,7 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
-u32 port_to_devdisr[] = {
+static u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
diff --git a/drivers/net/fm/p5020.c b/drivers/net/fm/p5020.c
index a7a6e43..5391044 100644
--- a/drivers/net/fm/p5020.c
+++ b/drivers/net/fm/p5020.c
@@ -23,7 +23,7 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
-u32 port_to_devdisr[] = {
+static u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
diff --git a/drivers/net/fm/t4240.c b/drivers/net/fm/t4240.c
new file mode 100644
index 0000000..48c530c
--- /dev/null
+++ b/drivers/net/fm/t4240.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Roy Zang <tie-fei.zang@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+u32 port_to_devdisr[] = {
+ [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
+ [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
+ [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
+ [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
+ [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
+ [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
+ [FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9,
+ [FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10,
+ [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
+ [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
+ [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
+ [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
+ [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
+ [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
+ [FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5,
+ [FM2_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC2_6,
+ [FM2_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC2_9,
+ [FM2_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC2_10,
+ [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2_1,
+ [FM2_10GEC2] = FSL_CORENET_DEVDISR2_10GEC2_2,
+};
+
+static int is_device_disabled(enum fm_port port)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 devdisr2 = in_be32(&gur->devdisr2);
+
+ return port_to_devdisr[port] & devdisr2;
+}
+
+void fman_disable_port(enum fm_port port)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
+}
+
+phy_interface_t fman_port_enet_if(enum fm_port port)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+
+ if (is_device_disabled(port))
+ return PHY_INTERFACE_MODE_NONE;
+
+ if ((port == FM1_10GEC1 || port == FM1_10GEC2)
+ && (is_serdes_configured(XAUI_FM1)))
+ return PHY_INTERFACE_MODE_XGMII;
+
+ if ((port == FM2_10GEC1 || port == FM2_10GEC2)
+ && (is_serdes_configured(XAUI_FM2)))
+ return PHY_INTERFACE_MODE_XGMII;
+
+#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
+#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
+#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
+#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
+#define FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII 0x08000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
+ /* handle RGMII first */
+ if ((port == FM2_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
+ FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII))
+ return PHY_INTERFACE_MODE_RGMII;
+
+ if ((port == FM1_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+ FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII))
+ return PHY_INTERFACE_MODE_RGMII;
+
+ if ((port == FM2_DTSEC6) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+ FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII))
+ return PHY_INTERFACE_MODE_RGMII;
+ switch (port) {
+ case FM1_DTSEC1:
+ case FM1_DTSEC2:
+ case FM1_DTSEC3:
+ case FM1_DTSEC4:
+ case FM1_DTSEC5:
+ case FM1_DTSEC6:
+ case FM1_DTSEC9:
+ case FM1_DTSEC10:
+ if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
+ return PHY_INTERFACE_MODE_SGMII;
+ break;
+ case FM2_DTSEC1:
+ case FM2_DTSEC2:
+ case FM2_DTSEC3:
+ case FM2_DTSEC4:
+ case FM2_DTSEC5:
+ case FM2_DTSEC6:
+ case FM2_DTSEC9:
+ case FM2_DTSEC10:
+ if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
+ return PHY_INTERFACE_MODE_SGMII;
+ break;
+ default:
+ return PHY_INTERFACE_MODE_NONE;
+ }
+
+ return PHY_INTERFACE_MODE_NONE;
+}
diff --git a/drivers/net/fm/tgec_phy.c b/drivers/net/fm/tgec_phy.c
index 2d349ad..2be69d7 100644
--- a/drivers/net/fm/tgec_phy.c
+++ b/drivers/net/fm/tgec_phy.c
@@ -30,8 +30,8 @@
* until the write is done before it returns. All PHY configuration has to be
* done through the TSEC1 MIIM regs
*/
-int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
- int regnum, u16 value)
+static int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
+ int regnum, u16 value)
{
u32 mdio_ctl;
u32 stat_val;
@@ -72,8 +72,8 @@ int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
* Clears miimcom first. All PHY configuration has to be done through the
* TSEC1 MIIM regs
*/
-int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
- int regnum)
+static int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
+ int regnum)
{
u32 mdio_ctl;
u32 stat_val;
@@ -114,7 +114,7 @@ int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
return in_be32(&regs->mdio_data) & 0xffff;
}
-int tgec_mdio_reset(struct mii_dev *bus)
+static int tgec_mdio_reset(struct mii_dev *bus)
{
return 0;
}
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 0e1ced7..8bacbda 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -51,8 +51,6 @@
#include "macb.h"
-#define barrier() asm volatile("" ::: "memory")
-
#define CONFIG_SYS_MACB_RX_BUFFER_SIZE 4096
#define CONFIG_SYS_MACB_RX_RING_SIZE (CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128)
#define CONFIG_SYS_MACB_TX_RING_SIZE 16
diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c
index 471c5ef..5e64dbd 100644
--- a/drivers/net/mcfmii.c
+++ b/drivers/net/mcfmii.c
@@ -315,13 +315,11 @@ int mcffec_miiphy_read(const char *devname, unsigned char addr, unsigned char re
int mcffec_miiphy_write(const char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
- short rdreg; /* register working value */
-
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
- rdreg = mii_send(mk_mii_write(addr, reg, value));
+ mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
diff --git a/drivers/net/netarm_eth.c b/drivers/net/netarm_eth.c
deleted file mode 100644
index 325f16c..0000000
--- a/drivers/net/netarm_eth.c
+++ /dev/null
@@ -1,352 +0,0 @@
-/*
- * Copyright (C) 2004 IMMS gGmbH <www.imms.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * author(s): Thomas Elste, <info@elste.org>
- * (some parts derived from uCLinux Netarm Ethernet Driver)
- */
-
-
-#include <common.h>
-#include <command.h>
-#include <net.h>
-#include "netarm_eth.h"
-#include <asm/arch/netarm_registers.h>
-
-static int na_mii_poll_busy (void);
-
-static void na_get_mac_addr (void)
-{
- unsigned short p[3];
- char *m_addr;
- char ethaddr[20];
-
- m_addr = (char *) p;
-
- p[0] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_1);
- p[1] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_2);
- p[2] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_3);
-
- sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
- m_addr[0], m_addr[1],
- m_addr[2], m_addr[3], m_addr[4], m_addr[5]);
-
- printf ("HW-MAC Address: %s\n", ethaddr);
-
- /* set env, todo: check if already an adress is set */
- setenv ("ethaddr", ethaddr);
-}
-
-static void na_mii_write (int reg, int value)
-{
- int mii_addr;
-
- /* Select register */
- mii_addr = CONFIG_SYS_ETH_PHY_ADDR + reg;
- SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr);
- /* Write value */
- SET_EADDR (NETARM_ETH_MII_WRITE, value);
- na_mii_poll_busy ();
-}
-
-static unsigned int na_mii_read (int reg)
-{
- int mii_addr, val;
-
- /* Select register */
- mii_addr = CONFIG_SYS_ETH_PHY_ADDR + reg;
- SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr);
- /* do one management cycle */
- SET_EADDR (NETARM_ETH_MII_CMD,
- GET_EADDR (NETARM_ETH_MII_CMD) | NETARM_ETH_MIIC_RSTAT);
- na_mii_poll_busy ();
- /* Return read value */
- val = GET_EADDR (NETARM_ETH_MII_READ);
- return val;
-}
-
-static int na_mii_poll_busy (void)
-{
- ulong start;
- /* arm simple, non interrupt dependent timer */
- start = get_timer(0));
- while (get_timer(start) < NA_MII_POLL_BUSY_DELAY) {
- if (!(GET_EADDR (NETARM_ETH_MII_IND) & NETARM_ETH_MIII_BUSY)) {
- return 1;
- }
- }
- printf ("na_mii_busy timeout\n");
- return (0);
-}
-
-static int na_mii_identify_phy (void)
-{
- int id_reg_a = 0;
-
- /* get phy id register */
- id_reg_a = na_mii_read (MII_PHY_ID);
-
- if (id_reg_a == 0x0043) {
- /* This must be an Enable or a Lucent LU3X31 PHY chip */
- return 1;
- } else if (id_reg_a == 0x0013) {
- /* it is an Intel LXT971A */
- return 1;
- }
- return (0);
-}
-
-static int na_mii_negotiate (void)
-{
- int i = 0;
-
- /* Enable auto-negotiation */
- na_mii_write (MII_PHY_AUTONEGADV, 0x01e1);
- /* FIXME: 0x01E1 is 100Mb half and full duplex, 0x0061 is 10Mb only */
- /* Restart auto-negotiation */
- na_mii_write (MII_PHY_CONTROL, 0x1200);
-
- /* status register is 0xffff after setting the autoneg restart bit */
- while (na_mii_read (MII_PHY_STATUS) == 0xffff) {
- i++;
- }
-
- /* na_mii_read uses the timer already, so we can't use it again for
- timeout checking.
- Instead we just try some times.
- */
- for (i = 0; i < 40000; i++) {
- if ((na_mii_read (MII_PHY_STATUS) & 0x0024) == 0x0024) {
- return 0;
- }
- }
- /*
- printf("*Warning* autonegotiation timeout, status: 0x%x\n",na_mii_read(MII_PHY_STATUS));
- */
- return (1);
-}
-
-static unsigned int na_mii_check_speed (void)
-{
- unsigned int status;
-
- /* Read Status register */
- status = na_mii_read (MII_PHY_STATUS);
- /* Check link status. If 0, default to 100 Mbps. */
- if ((status & 0x0004) == 0) {
- printf ("*Warning* no link detected, set default speed to 100Mbs\n");
- return 1;
- } else {
- if ((na_mii_read (17) & 0x4000) != 0) {
- printf ("100Mbs link detected\n");
- return 1;
- } else {
- printf ("10Mbs link detected\n");
- return 0;
- }
- }
- return 0;
-}
-
-static int reset_eth (void)
-{
- int pt;
- ulong start;
-
- na_get_mac_addr ();
- pt = na_mii_identify_phy ();
-
- /* reset the phy */
- na_mii_write (MII_PHY_CONTROL, 0x8000);
- start = get_timer(0);
- while (get_timer(start) < NA_MII_NEGOTIATE_DELAY) {
- if ((na_mii_read (MII_PHY_STATUS) & 0x8000) == 0) {
- break;
- }
- }
- if (get_timer(start) >= NA_MII_NEGOTIATE_DELAY)
- printf ("phy reset timeout\n");
-
- /* set the PCS reg */
- SET_EADDR (NETARM_ETH_PCS_CFG, NETARM_ETH_PCSC_CLKS_25M |
- NETARM_ETH_PCSC_ENJAB | NETARM_ETH_PCSC_NOCFR);
-
- na_mii_negotiate ();
- na_mii_check_speed ();
-
- /* Delay 10 millisecond. (Maybe this should be 1 second.) */
- udelay (10000);
-
- /* Turn receive on.
- Enable statistics register autozero on read.
- Do not insert MAC address on transmit.
- Do not enable special test modes. */
- SET_EADDR (NETARM_ETH_STL_CFG,
- (NETARM_ETH_STLC_AUTOZ | NETARM_ETH_STLC_RXEN));
-
- /* Set the inter-packet gap delay to 0.96us for MII.
- The NET+ARM H/W Reference Guide indicates that the Back-to-back IPG
- Gap Timer Register should be set to 0x15 and the Non Back-to-back IPG
- Gap Timer Register should be set to 0x00000C12 for the MII PHY. */
- SET_EADDR (NETARM_ETH_B2B_IPG_GAP_TMR, 0x15);
- SET_EADDR (NETARM_ETH_NB2B_IPG_GAP_TMR, 0x00000C12);
-
- /* Add CRC to end of packets.
- Pad packets to minimum length of 64 bytes.
- Allow unlimited length transmit packets.
- Receive all broadcast packets.
- NOTE: Multicast addressing is NOT enabled here currently. */
- SET_EADDR (NETARM_ETH_MAC_CFG,
- (NETARM_ETH_MACC_CRCEN |
- NETARM_ETH_MACC_PADEN | NETARM_ETH_MACC_HUGEN));
- SET_EADDR (NETARM_ETH_SAL_FILTER, NETARM_ETH_SALF_BROAD);
-
- /* enable fifos */
- SET_EADDR (NETARM_ETH_GEN_CTRL,
- (NETARM_ETH_GCR_ERX | NETARM_ETH_GCR_ETX));
-
- return (0);
-}
-
-
-extern int eth_init (bd_t * bd)
-{
- reset_eth ();
- return 0;
-}
-
-extern void eth_halt (void)
-{
- SET_EADDR (NETARM_ETH_GEN_CTRL, 0);
-}
-
-/* Get a data block via Ethernet */
-extern int eth_rx (void)
-{
- int i;
- unsigned short rxlen;
- unsigned int *addr;
- unsigned int rxstatus, lastrxlen;
- char *pa;
-
- /* RXBR is 1, data block was received */
- if ((GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXBR) == 0)
- return 0;
-
- /* get status register and the length of received block */
- rxstatus = GET_EADDR (NETARM_ETH_RX_STAT);
- rxlen = (rxstatus & NETARM_ETH_RXSTAT_SIZE) >> 16;
-
- if (rxlen == 0)
- return 0;
-
- /* clear RXBR to make fifo available */
- SET_EADDR (NETARM_ETH_GEN_STAT,
- GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_RXBR);
-
- /* clear TXBC to make fifo available */
- /* According to NETARM50 data manual you just have to clear
- RXBR but that has no effect. Only after clearing TXBC the
- Fifo becomes readable. */
- SET_EADDR (NETARM_ETH_GEN_STAT,
- GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_TXBC);
-
- addr = (unsigned int *) NetRxPackets[0];
- pa = (char *) NetRxPackets[0];
-
- /* read the fifo */
- for (i = 0; i < rxlen / 4; i++) {
- *addr = GET_EADDR (NETARM_ETH_FIFO_DAT1);
- addr++;
- }
-
- if (GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXREGR) {
- /* RXFDB indicates wether the last word is 1,2,3 or 4 bytes long */
- lastrxlen =
- (GET_EADDR (NETARM_ETH_GEN_STAT) &
- NETARM_ETH_GST_RXFDB) >> 28;
- *addr = GET_EADDR (NETARM_ETH_FIFO_DAT1);
- switch (lastrxlen) {
- case 1:
- *addr &= 0xff000000;
- break;
- case 2:
- *addr &= 0xffff0000;
- break;
- case 3:
- *addr &= 0xffffff00;
- break;
- }
- }
-
- /* Pass the packet up to the protocol layers. */
- NetReceive (NetRxPackets[0], rxlen);
-
- return rxlen;
-}
-
-/* Send a data block via Ethernet. */
-extern int eth_send(void *packet, int length)
-{
- int i, length32;
- char *pa;
- unsigned int *pa32, lastp = 0, rest;
-
- pa = (char *) packet;
- pa32 = (unsigned int *) packet;
- length32 = length / 4;
- rest = length % 4;
-
- /* make sure there's no garbage in the last word */
- switch (rest) {
- case 0:
- lastp = pa32[length32];
- length32--;
- break;
- case 1:
- lastp = pa32[length32] & 0x000000ff;
- break;
- case 2:
- lastp = pa32[length32] & 0x0000ffff;
- break;
- case 3:
- lastp = pa32[length32] & 0x00ffffff;
- break;
- }
-
- /* write to the fifo */
- for (i = 0; i < length32; i++)
- SET_EADDR (NETARM_ETH_FIFO_DAT1, pa32[i]);
-
- /* the last word is written to an extra register, this
- starts the transmission */
- SET_EADDR (NETARM_ETH_FIFO_DAT2, lastp);
-
- /* NETARM_ETH_TXSTAT_TXOK should be checked, to know if the transmission
- went fine. But we can't use the timer for a timeout loop because
- of it is used already in upper layers. So we just try some times. */
- i = 0;
- while (i < 50000) {
- if ((GET_EADDR (NETARM_ETH_TX_STAT) & NETARM_ETH_TXSTAT_TXOK)
- == NETARM_ETH_TXSTAT_TXOK)
- return 0;
- i++;
- }
-
- printf ("eth_send timeout\n");
- return 1;
-}
diff --git a/drivers/net/netarm_eth.h b/drivers/net/netarm_eth.h
deleted file mode 100644
index 8edab82..0000000
--- a/drivers/net/netarm_eth.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2003 IMMS gGmbH <www.imms.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * author(s): Thomas Elste, <info@elste.org>
- */
-
-#include <asm/types.h>
-#include <config.h>
-
-#ifdef CONFIG_DRIVER_NETARMETH
-
-#define SET_EADDR(ad,val) *(volatile unsigned int*)(ad + NETARM_ETH_MODULE_BASE) = val
-#define GET_EADDR(ad) (*(volatile unsigned int*)(ad + NETARM_ETH_MODULE_BASE))
-
-#define NA_MII_POLL_BUSY_DELAY 900
-
-/* MII negotiation timeout value
- 500 jiffies = 5 seconds */
-#define NA_MII_NEGOTIATE_DELAY 30
-
-/* Registers in the physical layer chip */
-#define MII_PHY_CONTROL 0
-#define MII_PHY_STATUS 1
-#define MII_PHY_ID 2
-#define MII_PHY_AUTONEGADV 4
-
-#endif /* CONFIG_DRIVER_NETARMETH */
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 798473d..9b3808b 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -30,7 +30,7 @@ static int ar8021_config(struct phy_device *phydev)
return 0;
}
-struct phy_driver AR8021_driver = {
+static struct phy_driver AR8021_driver = {
.name = "AR8021",
.uid = 0x4dd040,
.mask = 0xfffff0,
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index baef60f..1ffa791 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -43,7 +43,7 @@
* what is supported. Returns < 0 on error, 0 if the PHY's advertisement
* hasn't changed, and > 0 if it has changed.
*/
-int genphy_config_advert(struct phy_device *phydev)
+static int genphy_config_advert(struct phy_device *phydev)
{
u32 advertise;
int oldadv, adv;
@@ -118,7 +118,7 @@ int genphy_config_advert(struct phy_device *phydev)
* Description: Configures MII_BMCR to force speed/duplex
* to the values in phydev. Assumes that the values are valid.
*/
-int genphy_setup_forced(struct phy_device *phydev)
+static int genphy_setup_forced(struct phy_device *phydev)
{
int err;
int ctl = 0;
@@ -465,7 +465,7 @@ int phy_register(struct phy_driver *drv)
return 0;
}
-int phy_probe(struct phy_device *phydev)
+static int phy_probe(struct phy_device *phydev)
{
int err = 0;
@@ -488,7 +488,7 @@ static struct phy_driver *generic_for_interface(phy_interface_t interface)
return &genphy_driver;
}
-struct phy_driver *get_phy_driver(struct phy_device *phydev,
+static struct phy_driver *get_phy_driver(struct phy_device *phydev,
phy_interface_t interface)
{
struct list_head *entry;
@@ -505,8 +505,9 @@ struct phy_driver *get_phy_driver(struct phy_device *phydev,
return generic_for_interface(interface);
}
-struct phy_device *phy_device_create(struct mii_dev *bus, int addr, int phy_id,
- phy_interface_t interface)
+static struct phy_device *phy_device_create(struct mii_dev *bus, int addr,
+ int phy_id,
+ phy_interface_t interface)
{
struct phy_device *dev;
@@ -549,7 +550,7 @@ struct phy_device *phy_device_create(struct mii_dev *bus, int addr, int phy_id,
* Description: Reads the ID registers of the PHY at @addr on the
* @bus, stores it in @phy_id and returns zero on success.
*/
-int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
+static int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
{
int phy_reg;
@@ -581,8 +582,8 @@ int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
* Description: Reads the ID registers of the PHY at @addr on the
* @bus, then allocates and returns the phy_device to represent it.
*/
-struct phy_device *get_phy_device(struct mii_dev *bus, int addr,
- phy_interface_t interface)
+static struct phy_device *get_phy_device(struct mii_dev *bus, int addr,
+ phy_interface_t interface)
{
u32 phy_id = 0x1fffffff;
int i;
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index 0a0f40d..6c5cb99 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -123,7 +123,7 @@ static int cis8204_config(struct phy_device *phydev)
}
/* Vitesse VSC8601 */
-int vsc8601_config(struct phy_device *phydev)
+static int vsc8601_config(struct phy_device *phydev)
{
/* Configure some basic stuff */
#ifdef CONFIG_SYS_VSC8601_SKEWFIX
diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c
index 6dc7ad5..1357ede 100644
--- a/drivers/net/smc91111.c
+++ b/drivers/net/smc91111.c
@@ -178,8 +178,6 @@ static void smc_phy_configure(struct eth_device *dev);
* inx,outx functions fixed this problem.
*/
-#define barrier() __asm__ __volatile__("": : :"memory")
-
static inline word SMC_inw(struct eth_device *dev, dword offset)
{
word v;
diff --git a/drivers/net/vsc7385.c b/drivers/net/vsc7385.c
index ada42c4..a5110e5 100644
--- a/drivers/net/vsc7385.c
+++ b/drivers/net/vsc7385.c
@@ -16,6 +16,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>
+#include "vsc7385.h"
/*
* Upload a Vitesse VSC7385 firmware image to the hardware