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path: root/drivers/mmc/fsl_esdhc.c
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Diffstat (limited to 'drivers/mmc/fsl_esdhc.c')
-rw-r--r--drivers/mmc/fsl_esdhc.c15
1 files changed, 13 insertions, 2 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index c5054d6..1ccc576 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -502,15 +502,22 @@ static void set_sysctl(struct mmc *mmc, uint clock)
clk = (pre_div << 8) | (div << 4);
+#ifdef CONFIG_FSL_USDHC
+ esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
+#else
esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
+#endif
esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
udelay(10000);
- clk = SYSCTL_PEREN | SYSCTL_CKEN;
+#ifdef CONFIG_FSL_USDHC
+ esdhc_clrbits32(&regs->sysctl, SYSCTL_RSTA);
+#else
+ esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
+#endif
- esdhc_setbits32(&regs->sysctl, clk);
}
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
@@ -585,7 +592,9 @@ static int esdhc_init(struct mmc *mmc)
esdhc_write32(&regs->scr, 0x00000040);
#endif
+#ifndef CONFIG_FSL_USDHC
esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
+#endif
/* Set the initial clock speed */
mmc_set_clock(mmc, 400000);
@@ -657,8 +666,10 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
/* First reset the eSDHC controller */
esdhc_reset(regs);
+#ifndef CONFIG_FSL_USDHC
esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
| SYSCTL_IPGEN | SYSCTL_CKEN);
+#endif
writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
memset(&cfg->cfg, 0, sizeof(cfg->cfg));