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-rw-r--r--drivers/misc/Makefile2
-rw-r--r--drivers/misc/fsl_iim.c286
-rw-r--r--drivers/misc/mxc_ocotp.c216
3 files changed, 504 insertions, 0 deletions
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 8cdc3b6..5d869b4 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -28,8 +28,10 @@ LIB := $(obj)libmisc.o
COBJS-$(CONFIG_ALI152X) += ali512x.o
COBJS-$(CONFIG_DS4510) += ds4510.o
COBJS-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o
+COBJS-$(CONFIG_FSL_IIM) += fsl_iim.o
COBJS-$(CONFIG_GPIO_LED) += gpio_led.o
COBJS-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
+COBJS-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
COBJS-$(CONFIG_NS87308) += ns87308.o
COBJS-$(CONFIG_PDSP188x) += pdsp188x.o
COBJS-$(CONFIG_STATUS_LED) += status_led.o
diff --git a/drivers/misc/fsl_iim.c b/drivers/misc/fsl_iim.c
new file mode 100644
index 0000000..9179fbb
--- /dev/null
+++ b/drivers/misc/fsl_iim.c
@@ -0,0 +1,286 @@
+/*
+ * (C) Copyright 2009-2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on the mpc512x iim code:
+ * Copyright 2008 Silicon Turnkey Express, Inc.
+ * Martha Marx <mmarx@silicontkx.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fuse.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#ifndef CONFIG_MPC512X
+#include <asm/arch/imx-regs.h>
+#endif
+
+/* FSL IIM-specific constants */
+#define STAT_BUSY 0x80
+#define STAT_PRGD 0x02
+#define STAT_SNSD 0x01
+
+#define STATM_PRGD_M 0x02
+#define STATM_SNSD_M 0x01
+
+#define ERR_PRGE 0x80
+#define ERR_WPE 0x40
+#define ERR_OPE 0x20
+#define ERR_RPE 0x10
+#define ERR_WLRE 0x08
+#define ERR_SNSE 0x04
+#define ERR_PARITYE 0x02
+
+#define EMASK_PRGE_M 0x80
+#define EMASK_WPE_M 0x40
+#define EMASK_OPE_M 0x20
+#define EMASK_RPE_M 0x10
+#define EMASK_WLRE_M 0x08
+#define EMASK_SNSE_M 0x04
+#define EMASK_PARITYE_M 0x02
+
+#define FCTL_DPC 0x80
+#define FCTL_PRG_LENGTH_MASK 0x70
+#define FCTL_ESNS_N 0x08
+#define FCTL_ESNS_0 0x04
+#define FCTL_ESNS_1 0x02
+#define FCTL_PRG 0x01
+
+#define UA_A_BANK_MASK 0x38
+#define UA_A_ROWH_MASK 0x07
+
+#define LA_A_ROWL_MASK 0xf8
+#define LA_A_BIT_MASK 0x07
+
+#define PREV_PROD_REV_MASK 0xf8
+#define PREV_PROD_VT_MASK 0x07
+
+/* Select the correct accessors depending on endianness */
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+#define iim_read32 in_le32
+#define iim_write32 out_le32
+#define iim_clrsetbits32 clrsetbits_le32
+#define iim_clrbits32 clrbits_le32
+#define iim_setbits32 setbits_le32
+#elif __BYTE_ORDER == __BIG_ENDIAN
+#define iim_read32 in_be32
+#define iim_write32 out_be32
+#define iim_clrsetbits32 clrsetbits_be32
+#define iim_clrbits32 clrbits_be32
+#define iim_setbits32 setbits_be32
+#else
+#error Endianess is not defined: please fix to continue
+#endif
+
+/* IIM control registers */
+struct fsl_iim {
+ u32 stat;
+ u32 statm;
+ u32 err;
+ u32 emask;
+ u32 fctl;
+ u32 ua;
+ u32 la;
+ u32 sdat;
+ u32 prev;
+ u32 srev;
+ u32 prg_p;
+ u32 scs[0x1f5];
+ struct {
+ u32 word[0x100];
+ } bank[8];
+};
+
+static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int assert,
+ const char *caller)
+{
+ *regs = (struct fsl_iim *)IIM_BASE_ADDR;
+
+ if (bank >= ARRAY_SIZE((*regs)->bank) ||
+ word >= ARRAY_SIZE((*regs)->bank[0].word) ||
+ !assert) {
+ printf("fsl_iim %s(): Invalid argument\n", caller);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void clear_status(struct fsl_iim *regs)
+{
+ iim_setbits32(&regs->stat, 0);
+ iim_setbits32(&regs->err, 0);
+}
+
+static void finish_access(struct fsl_iim *regs, u32 *stat, u32 *err)
+{
+ *stat = iim_read32(&regs->stat);
+ *err = iim_read32(&regs->err);
+ clear_status(regs);
+}
+
+static int prepare_read(struct fsl_iim **regs, u32 bank, u32 word, u32 *val,
+ const char *caller)
+{
+ int ret;
+
+ ret = prepare_access(regs, bank, word, val != NULL, caller);
+ if (ret)
+ return ret;
+
+ clear_status(*regs);
+
+ return 0;
+}
+
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+ struct fsl_iim *regs;
+ u32 stat, err;
+ int ret;
+
+ ret = prepare_read(&regs, bank, word, val, __func__);
+ if (ret)
+ return ret;
+
+ *val = iim_read32(&regs->bank[bank].word[word]);
+ finish_access(regs, &stat, &err);
+
+ if (err & ERR_RPE) {
+ puts("fsl_iim fuse_read(): Read protect error\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static void direct_access(struct fsl_iim *regs, u32 bank, u32 word, u32 bit,
+ u32 fctl, u32 *stat, u32 *err)
+{
+ iim_write32(&regs->ua, bank << 3 | word >> 5);
+ iim_write32(&regs->la, (word << 3 | bit) & 0xff);
+ if (fctl == FCTL_PRG)
+ iim_write32(&regs->prg_p, 0xaa);
+ iim_setbits32(&regs->fctl, fctl);
+ while (iim_read32(&regs->stat) & STAT_BUSY)
+ udelay(20);
+ finish_access(regs, stat, err);
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+ struct fsl_iim *regs;
+ u32 stat, err;
+ int ret;
+
+ ret = prepare_read(&regs, bank, word, val, __func__);
+ if (ret)
+ return ret;
+
+ direct_access(regs, bank, word, 0, FCTL_ESNS_N, &stat, &err);
+
+ if (err & ERR_SNSE) {
+ puts("fsl_iim fuse_sense(): Explicit sense cycle error\n");
+ return -EIO;
+ }
+
+ if (!(stat & STAT_SNSD)) {
+ puts("fsl_iim fuse_sense(): Explicit sense cycle did not complete\n");
+ return -EIO;
+ }
+
+ *val = iim_read32(&regs->sdat);
+ return 0;
+}
+
+static int prog_bit(struct fsl_iim *regs, u32 bank, u32 word, u32 bit)
+{
+ u32 stat, err;
+
+ clear_status(regs);
+ direct_access(regs, bank, word, bit, FCTL_PRG, &stat, &err);
+ iim_write32(&regs->prg_p, 0x00);
+
+ if (err & ERR_PRGE) {
+ puts("fsl_iim fuse_prog(): Program error\n");
+ return -EIO;
+ }
+
+ if (err & ERR_WPE) {
+ puts("fsl_iim fuse_prog(): Write protect error\n");
+ return -EIO;
+ }
+
+ if (!(stat & STAT_PRGD)) {
+ puts("fsl_iim fuse_prog(): Program did not complete\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int prepare_write(struct fsl_iim **regs, u32 bank, u32 word, u32 val,
+ const char *caller)
+{
+ return prepare_access(regs, bank, word, !(val & ~0xff), caller);
+}
+
+int fuse_prog(u32 bank, u32 word, u32 val)
+{
+ struct fsl_iim *regs;
+ u32 bit;
+ int ret;
+
+ ret = prepare_write(&regs, bank, word, val, __func__);
+ if (ret)
+ return ret;
+
+ for (bit = 0; val; bit++, val >>= 1)
+ if (val & 0x01) {
+ ret = prog_bit(regs, bank, word, bit);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int fuse_override(u32 bank, u32 word, u32 val)
+{
+ struct fsl_iim *regs;
+ u32 stat, err;
+ int ret;
+
+ ret = prepare_write(&regs, bank, word, val, __func__);
+ if (ret)
+ return ret;
+
+ clear_status(regs);
+ iim_write32(&regs->bank[bank].word[word], val);
+ finish_access(regs, &stat, &err);
+
+ if (err & ERR_OPE) {
+ puts("fsl_iim fuse_override(): Override protect error\n");
+ return -EIO;
+ }
+
+ return 0;
+}
diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
new file mode 100644
index 0000000..0095b47
--- /dev/null
+++ b/drivers/misc/mxc_ocotp.c
@@ -0,0 +1,216 @@
+/*
+ * (C) Copyright 2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on Dirk Behme's
+ * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
+ * which is based on Freescale's
+ * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
+ * which is:
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fuse.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+
+#define BO_CTRL_WR_UNLOCK 16
+#define BM_CTRL_WR_UNLOCK 0xffff0000
+#define BV_CTRL_WR_UNLOCK_KEY 0x3e77
+#define BM_CTRL_ERROR 0x00000200
+#define BM_CTRL_BUSY 0x00000100
+#define BO_CTRL_ADDR 0
+#define BM_CTRL_ADDR 0x0000007f
+
+#define BO_TIMING_STROBE_READ 16
+#define BM_TIMING_STROBE_READ 0x003f0000
+#define BV_TIMING_STROBE_READ_NS 37
+#define BO_TIMING_RELAX 12
+#define BM_TIMING_RELAX 0x0000f000
+#define BV_TIMING_RELAX_NS 17
+#define BO_TIMING_STROBE_PROG 0
+#define BM_TIMING_STROBE_PROG 0x00000fff
+#define BV_TIMING_STROBE_PROG_US 10
+
+#define BM_READ_CTRL_READ_FUSE 0x00000001
+
+#define BF(value, field) (((value) << BO_##field) & BM_##field)
+
+#define WRITE_POSTAMBLE_US 2
+
+static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
+{
+ while (readl(&regs->ctrl) & BM_CTRL_BUSY)
+ udelay(delay_us);
+}
+
+static void clear_error(struct ocotp_regs *regs)
+{
+ writel(BM_CTRL_ERROR, &regs->ctrl_clr);
+}
+
+static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
+ int assert, const char *caller)
+{
+ *regs = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+
+ if (bank >= ARRAY_SIZE((*regs)->bank) ||
+ word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 ||
+ !assert) {
+ printf("mxc_ocotp %s(): Invalid argument\n", caller);
+ return -EINVAL;
+ }
+
+ enable_ocotp_clk(1);
+
+ wait_busy(*regs, 1);
+ clear_error(*regs);
+
+ return 0;
+}
+
+static int finish_access(struct ocotp_regs *regs, const char *caller)
+{
+ u32 err;
+
+ err = !!(readl(&regs->ctrl) & BM_CTRL_ERROR);
+ clear_error(regs);
+
+ enable_ocotp_clk(0);
+
+ if (err) {
+ printf("mxc_ocotp %s(): Access protect error\n", caller);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val,
+ const char *caller)
+{
+ return prepare_access(regs, bank, word, val != NULL, caller);
+}
+
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+ struct ocotp_regs *regs;
+ int ret;
+
+ ret = prepare_read(&regs, bank, word, val, __func__);
+ if (ret)
+ return ret;
+
+ *val = readl(&regs->bank[bank].fuse_regs[word << 2]);
+
+ return finish_access(regs, __func__);
+}
+
+static void set_timing(struct ocotp_regs *regs)
+{
+ u32 ipg_clk;
+ u32 relax, strobe_read, strobe_prog;
+ u32 timing;
+
+ ipg_clk = mxc_get_clock(MXC_IPG_CLK);
+
+ relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
+ strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
+ 1000000000) + 2 * (relax + 1) - 1;
+ strobe_prog = DIV_ROUND(ipg_clk * BV_TIMING_STROBE_PROG_US, 1000000) +
+ 2 * (relax + 1) - 1;
+
+ timing = BF(strobe_read, TIMING_STROBE_READ) |
+ BF(relax, TIMING_RELAX) |
+ BF(strobe_prog, TIMING_STROBE_PROG);
+
+ clrsetbits_le32(&regs->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX |
+ BM_TIMING_STROBE_PROG, timing);
+}
+
+static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
+ int write)
+{
+ u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
+ u32 addr = bank << 3 | word;
+
+ set_timing(regs);
+ clrsetbits_le32(&regs->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR,
+ BF(wr_unlock, CTRL_WR_UNLOCK) |
+ BF(addr, CTRL_ADDR));
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+ struct ocotp_regs *regs;
+ int ret;
+
+ ret = prepare_read(&regs, bank, word, val, __func__);
+ if (ret)
+ return ret;
+
+ setup_direct_access(regs, bank, word, false);
+ writel(BM_READ_CTRL_READ_FUSE, &regs->read_ctrl);
+ wait_busy(regs, 1);
+ *val = readl(&regs->read_fuse_data);
+
+ return finish_access(regs, __func__);
+}
+
+static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
+ const char *caller)
+{
+ return prepare_access(regs, bank, word, true, caller);
+}
+
+int fuse_prog(u32 bank, u32 word, u32 val)
+{
+ struct ocotp_regs *regs;
+ int ret;
+
+ ret = prepare_write(&regs, bank, word, __func__);
+ if (ret)
+ return ret;
+
+ setup_direct_access(regs, bank, word, true);
+ writel(val, &regs->data);
+ wait_busy(regs, BV_TIMING_STROBE_PROG_US);
+ udelay(WRITE_POSTAMBLE_US);
+
+ return finish_access(regs, __func__);
+}
+
+int fuse_override(u32 bank, u32 word, u32 val)
+{
+ struct ocotp_regs *regs;
+ int ret;
+
+ ret = prepare_write(&regs, bank, word, __func__);
+ if (ret)
+ return ret;
+
+ writel(val, &regs->bank[bank].fuse_regs[word << 2]);
+
+ return finish_access(regs, __func__);
+}