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-rw-r--r--drivers/i2c/Makefile1
-rw-r--r--drivers/i2c/ihs_i2c.c203
-rw-r--r--drivers/i2c/kona_i2c.c2
-rw-r--r--drivers/i2c/mxc_i2c.c5
-rw-r--r--drivers/i2c/tegra_i2c.c44
5 files changed, 237 insertions, 18 deletions
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index e33586d..96bd45d 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_SYS_I2C) += i2c_core.o
obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
+obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c
new file mode 100644
index 0000000..fe66ce2
--- /dev/null
+++ b/drivers/i2c/ihs_i2c.c
@@ -0,0 +1,203 @@
+/*
+ * (C) Copyright 2013
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <gdsys_fpga.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ I2CINT_ERROR_EV = 1 << 13,
+ I2CINT_TRANSMIT_EV = 1 << 14,
+ I2CINT_RECEIVE_EV = 1 << 15,
+};
+
+enum {
+ I2CMB_WRITE = 1 << 10,
+ I2CMB_2BYTE = 1 << 11,
+ I2CMB_HOLD_BUS = 1 << 13,
+ I2CMB_NATIVE = 2 << 14,
+};
+
+static int wait_for_int(bool read)
+{
+ u16 val;
+ unsigned int ctr = 0;
+
+ FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
+ while (!(val & (I2CINT_ERROR_EV
+ | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
+ udelay(10);
+ if (ctr++ > 5000) {
+ return 1;
+ }
+ FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
+ }
+
+ return (val & I2CINT_ERROR_EV) ? 1 : 0;
+}
+
+static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
+ bool is_last)
+{
+ u16 val;
+
+ FPGA_SET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, I2CINT_ERROR_EV
+ | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV);
+ FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
+
+ if (!read && len) {
+ val = buffer[0];
+
+ if (len > 1)
+ val |= buffer[1] << 8;
+ FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox_ext, val);
+ }
+
+ FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox,
+ I2CMB_NATIVE
+ | (read ? 0 : I2CMB_WRITE)
+ | (chip << 1)
+ | ((len > 1) ? I2CMB_2BYTE : 0)
+ | (is_last ? 0 : I2CMB_HOLD_BUS));
+
+ if (wait_for_int(read))
+ return 1;
+
+ if (read) {
+ FPGA_GET_REG(I2C_ADAP_HWNR, i2c.read_mailbox_ext, &val);
+ buffer[0] = val & 0xff;
+ if (len > 1)
+ buffer[1] = val >> 8;
+ }
+
+ return 0;
+}
+
+static int ihs_i2c_address(uchar chip, uint addr, int alen, bool hold_bus)
+{
+ int shift = (alen-1) * 8;
+
+ while (alen) {
+ int transfer = MIN(alen, 2);
+ uchar buf[2];
+ bool is_last = alen <= transfer;
+
+ buf[0] = addr >> shift;
+ if (alen > 1)
+ buf[1] = addr >> (shift - 8);
+
+ if (ihs_i2c_transfer(chip, buf, transfer, false,
+ hold_bus ? false : is_last))
+ return 1;
+
+ shift -= 16;
+ alen -= transfer;
+ }
+
+ return 0;
+}
+
+static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len, bool read)
+{
+ if (len <= 0)
+ return 1;
+
+ if (ihs_i2c_address(chip, addr, alen, !read))
+ return 1;
+
+ while (len) {
+ int transfer = MIN(len, 2);
+
+ if (ihs_i2c_transfer(chip, buffer, transfer, read,
+ len <= transfer))
+ return 1;
+
+ buffer += transfer;
+ addr += transfer;
+ len -= transfer;
+ }
+
+ return 0;
+}
+
+
+static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
+{
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+ /*
+ * Call board specific i2c bus reset routine before accessing the
+ * environment, which might be in a chip on that bus. For details
+ * about this problem see doc/I2C_Edge_Conditions.
+ */
+ i2c_init_board();
+#endif
+}
+
+static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
+{
+ uchar buffer[2];
+
+ if (ihs_i2c_transfer(chip, buffer, 0, true, true))
+ return 1;
+
+ return 0;
+}
+
+static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len)
+{
+ return ihs_i2c_access(adap, chip, addr, alen, buffer, len, true);
+}
+
+static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+ int alen, uchar *buffer, int len)
+{
+ return ihs_i2c_access(adap, chip, addr, alen, buffer, len, false);
+}
+
+static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
+ unsigned int speed)
+{
+ if (speed != adap->speed)
+ return 1;
+ return speed;
+}
+
+/*
+ * Register IHS i2c adapters
+ */
+#ifdef CONFIG_SYS_I2C_IHS_CH0
+U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
+ ihs_i2c_read, ihs_i2c_write,
+ ihs_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_IHS_SPEED_0,
+ CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
+#endif
+#ifdef CONFIG_SYS_I2C_IHS_CH1
+U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
+ ihs_i2c_read, ihs_i2c_write,
+ ihs_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_IHS_SPEED_1,
+ CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
+#endif
+#ifdef CONFIG_SYS_I2C_IHS_CH2
+U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
+ ihs_i2c_read, ihs_i2c_write,
+ ihs_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_IHS_SPEED_2,
+ CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
+#endif
+#ifdef CONFIG_SYS_I2C_IHS_CH3
+U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
+ ihs_i2c_read, ihs_i2c_write,
+ ihs_i2c_set_bus_speed,
+ CONFIG_SYS_I2C_IHS_SPEED_3,
+ CONFIG_SYS_I2C_IHS_SLAVE_3, 3)
+#endif
diff --git a/drivers/i2c/kona_i2c.c b/drivers/i2c/kona_i2c.c
index 0b1715a..5eab338 100644
--- a/drivers/i2c/kona_i2c.c
+++ b/drivers/i2c/kona_i2c.c
@@ -663,7 +663,7 @@ static int kona_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
int alen, uchar *buffer, int len)
{
- struct i2c_msg msg[0];
+ struct i2c_msg msg[1];
unsigned char msgbuf0[64];
unsigned int i;
struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 48468d7..c14797c 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -429,6 +429,11 @@ static void * const i2c_bases[] = {
(void *)I2C3_BASE_ADDR
#elif defined(CONFIG_VF610)
(void *)I2C0_BASE_ADDR
+#elif defined(CONFIG_FSL_LSCH3)
+ (void *)I2C1_BASE_ADDR,
+ (void *)I2C2_BASE_ADDR,
+ (void *)I2C3_BASE_ADDR,
+ (void *)I2C4_BASE_ADDR
#else
#error "architecture not supported"
#endif
diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c
index 594e5dd..257b72f 100644
--- a/drivers/i2c/tegra_i2c.c
+++ b/drivers/i2c/tegra_i2c.c
@@ -110,7 +110,8 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus)
static void send_packet_headers(
struct i2c_bus *i2c_bus,
struct i2c_trans_info *trans,
- u32 packet_id)
+ u32 packet_id,
+ bool end_with_repeated_start)
{
u32 data;
@@ -132,6 +133,8 @@ static void send_packet_headers(
/* Enable Read if it is not a write transaction */
if (!(trans->flags & I2C_IS_WRITE))
data |= PKT_HDR3_READ_MODE_MASK;
+ if (end_with_repeated_start)
+ data |= PKT_HDR3_REPEAT_START_MASK;
/* Write I2C specific header */
writel(data, &i2c_bus->control->tx_fifo);
@@ -209,7 +212,8 @@ static int send_recv_packets(struct i2c_bus *i2c_bus,
int_status = readl(&control->int_status);
writel(int_status, &control->int_status);
- send_packet_headers(i2c_bus, trans, 1);
+ send_packet_headers(i2c_bus, trans, 1,
+ trans->flags & I2C_USE_REPEATED_START);
words = DIV_ROUND_UP(trans->num_bytes, 4);
last_bytes = trans->num_bytes & 3;
@@ -220,14 +224,16 @@ static int send_recv_packets(struct i2c_bus *i2c_bus,
if (is_write) {
/* deal with word alignment */
- if ((unsigned)dptr & 3) {
+ if ((words == 1) && last_bytes) {
+ local = 0;
+ memcpy(&local, dptr, last_bytes);
+ } else if ((unsigned)dptr & 3) {
memcpy(&local, dptr, sizeof(u32));
- writel(local, &control->tx_fifo);
- debug("pkt data sent (0x%x)\n", local);
} else {
- writel(*wptr, &control->tx_fifo);
- debug("pkt data sent (0x%x)\n", *wptr);
+ local = *wptr;
}
+ writel(local, &control->tx_fifo);
+ debug("pkt data sent (0x%x)\n", local);
if (!wait_for_tx_fifo_empty(control)) {
error = -1;
goto exit;
@@ -267,7 +273,7 @@ exit:
}
static int tegra_i2c_write_data(struct i2c_bus *bus, u32 addr, u8 *data,
- u32 len)
+ u32 len, bool end_with_repeated_start)
{
int error;
struct i2c_trans_info trans_info;
@@ -275,6 +281,8 @@ static int tegra_i2c_write_data(struct i2c_bus *bus, u32 addr, u8 *data,
trans_info.address = addr;
trans_info.buf = data;
trans_info.flags = I2C_IS_WRITE;
+ if (end_with_repeated_start)
+ trans_info.flags |= I2C_USE_REPEATED_START;
trans_info.num_bytes = len;
trans_info.is_10bit_address = 0;
@@ -463,7 +471,8 @@ static void tegra_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
}
/* i2c write version without the register address */
-int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len)
+int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len,
+ bool end_with_repeated_start)
{
int rc;
@@ -475,7 +484,8 @@ int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len)
debug("\n");
/* Shift 7-bit address over for lower-level i2c functions */
- rc = tegra_i2c_write_data(bus, chip << 1, buffer, len);
+ rc = tegra_i2c_write_data(bus, chip << 1, buffer, len,
+ end_with_repeated_start);
if (rc)
debug("i2c_write_data(): rc=%d\n", rc);
@@ -516,7 +526,7 @@ static int tegra_i2c_probe(struct i2c_adapter *adap, uchar chip)
if (!bus)
return 1;
reg = 0;
- rc = i2c_write_data(bus, chip, &reg, 1);
+ rc = i2c_write_data(bus, chip, &reg, 1, false);
if (rc) {
debug("Error probing 0x%x.\n", chip);
return 1;
@@ -538,8 +548,8 @@ static int tegra_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
uint offset;
int i;
- debug("i2c_read: chip=0x%x, addr=0x%x, len=0x%x\n",
- chip, addr, len);
+ debug("i2c_read: chip=0x%x, addr=0x%x, alen=0x%x len=0x%x\n",
+ chip, addr, alen, len);
bus = tegra_i2c_get_bus(adap);
if (!bus)
return 1;
@@ -554,7 +564,7 @@ static int tegra_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
data[alen - i - 1] =
(addr + offset) >> (8 * i);
}
- if (i2c_write_data(bus, chip, data, alen)) {
+ if (i2c_write_data(bus, chip, data, alen, true)) {
debug("i2c_read: error sending (0x%x)\n",
addr);
return 1;
@@ -577,8 +587,8 @@ static int tegra_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
uint offset;
int i;
- debug("i2c_write: chip=0x%x, addr=0x%x, len=0x%x\n",
- chip, addr, len);
+ debug("i2c_write: chip=0x%x, addr=0x%x, alen=0x%x len=0x%x\n",
+ chip, addr, alen, len);
bus = tegra_i2c_get_bus(adap);
if (!bus)
return 1;
@@ -591,7 +601,7 @@ static int tegra_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
for (i = 0; i < alen; i++)
data[alen - i - 1] = (addr + offset) >> (8 * i);
data[alen] = buffer[offset];
- if (i2c_write_data(bus, chip, data, alen + 1)) {
+ if (i2c_write_data(bus, chip, data, alen + 1, false)) {
debug("i2c_write: error sending (0x%x)\n", addr);
return 1;
}
generated by cgit v1.1 at 2024-11-06 05:59:05 +0000