diff options
Diffstat (limited to 'drivers/fpga')
| -rw-r--r-- | drivers/fpga/fpga.c | 36 | ||||
| -rw-r--r-- | drivers/fpga/spartan2.c | 3 | ||||
| -rw-r--r-- | drivers/fpga/spartan3.c | 3 | ||||
| -rw-r--r-- | drivers/fpga/virtex2.c | 3 | ||||
| -rw-r--r-- | drivers/fpga/xilinx.c | 26 | ||||
| -rw-r--r-- | drivers/fpga/zynqpl.c | 105 |
6 files changed, 153 insertions, 23 deletions
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index b940d9b..37946d5 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -173,16 +173,45 @@ int fpga_add(fpga_type devtype, void *desc) /* * Convert bitstream data and load into the fpga */ -int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size) +int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size, + bitstream_type bstype) { printf("Bitstream support not implemented for this FPGA device\n"); return FPGA_FAIL; } +#if defined(CONFIG_CMD_FPGA_LOADFS) +int fpga_fsload(int devnum, const void *buf, size_t size, + fpga_fs_info *fpga_fsinfo) +{ + int ret_val = FPGA_FAIL; /* assume failure */ + const fpga_desc *desc = fpga_validate(devnum, buf, size, + (char *)__func__); + + if (desc) { + switch (desc->devtype) { + case fpga_xilinx: +#if defined(CONFIG_FPGA_XILINX) + ret_val = xilinx_loadfs(desc->devdesc, buf, size, + fpga_fsinfo); +#else + fpga_no_sup((char *)__func__, "Xilinx devices"); +#endif + break; + default: + printf("%s: Invalid or unsupported device type %d\n", + __func__, desc->devtype); + } + } + + return ret_val; +} +#endif + /* * Generic multiplexing code */ -int fpga_load(int devnum, const void *buf, size_t bsize) +int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype) { int ret_val = FPGA_FAIL; /* assume failure */ const fpga_desc *desc = fpga_validate(devnum, buf, bsize, @@ -192,7 +221,8 @@ int fpga_load(int devnum, const void *buf, size_t bsize) switch (desc->devtype) { case fpga_xilinx: #if defined(CONFIG_FPGA_XILINX) - ret_val = xilinx_load(desc->devdesc, buf, bsize); + ret_val = xilinx_load(desc->devdesc, buf, bsize, + bstype); #else fpga_no_sup((char *)__func__, "Xilinx devices"); #endif diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index 7054056..859fb3c 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -41,7 +41,8 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) { int ret_val = FPGA_FAIL; diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 5c9412c..b0213e6 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -45,7 +45,8 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) { int ret_val = FPGA_FAIL; diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index e092147..0d2d9a4 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -90,7 +90,8 @@ static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize); static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize); static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); -static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) { int ret_val = FPGA_FAIL; diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 8837f5c..3795c1a 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -24,7 +24,8 @@ static int xilinx_validate(xilinx_desc *desc, char *fn); /* ------------------------------------------------------------------------- */ -int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) +int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, + bitstream_type bstype) { unsigned int length; unsigned int swapsize; @@ -127,19 +128,36 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) dataptr += 4; printf(" bytes in bitstream = %d\n", swapsize); - return fpga_load(devnum, dataptr, swapsize); + return fpga_load(devnum, dataptr, swapsize, bstype); } -int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize) +int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) { if (!xilinx_validate (desc, (char *)__FUNCTION__)) { printf ("%s: Invalid device descriptor\n", __FUNCTION__); return FPGA_FAIL; } - return desc->operations->load(desc, buf, bsize); + return desc->operations->load(desc, buf, bsize, bstype); } +#if defined(CONFIG_CMD_FPGA_LOADFS) +int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, + fpga_fs_info *fpga_fsinfo) +{ + if (!xilinx_validate(desc, (char *)__func__)) { + printf("%s: Invalid device descriptor\n", __func__); + return FPGA_FAIL; + } + + if (!desc->operations->loadfs) + return FPGA_FAIL; + + return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo); +} +#endif + int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize) { if (!xilinx_validate (desc, (char *)__FUNCTION__)) { diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index c066f21..68fe0f3 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -9,6 +9,7 @@ #include <common.h> #include <asm/io.h> +#include <fs.h> #include <zynqpl.h> #include <linux/sizes.h> #include <asm/arch/hardware.h> @@ -194,7 +195,7 @@ static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen) return FPGA_SUCCESS; } -static int zynq_dma_xfer_init(u32 partialbit) +static int zynq_dma_xfer_init(bitstream_type bstype) { u32 status, control, isr_status; unsigned long ts; @@ -202,7 +203,7 @@ static int zynq_dma_xfer_init(u32 partialbit) /* Clear loopback bit */ clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK); - if (!partialbit) { + if (bstype != BIT_PARTIAL) { zynq_slcr_devcfg_disable(); /* Setting PCFG_PROG_B signal to high */ @@ -322,16 +323,11 @@ static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap) static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf, size_t bsize, u32 blocksize, u32 *swap, - u32 *partialbit) + bitstream_type *bstype) { u32 *buf_start; u32 diff; - /* Detect if we are going working with partial or full bitstream */ - if (bsize != desc->size) { - printf("%s: Working with partial bitstream\n", __func__); - *partialbit = 1; - } buf_start = check_data((u8 *)buf, blocksize, swap); if (!buf_start) @@ -351,17 +347,16 @@ static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf, return FPGA_FAIL; } - if (zynq_dma_xfer_init(*partialbit)) + if (zynq_dma_xfer_init(*bstype)) return FPGA_FAIL; return 0; } - -static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize, + bitstream_type bstype) { unsigned long ts; /* Timestamp */ - u32 partialbit = 0; u32 isr_status, swap; /* @@ -369,7 +364,7 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) * in chunks */ if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap, - &partialbit)) + &bstype)) return FPGA_FAIL; buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap); @@ -398,11 +393,92 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) debug("%s: FPGA config done\n", __func__); + if (bstype != BIT_PARTIAL) + zynq_slcr_devcfg_enable(); + + return FPGA_SUCCESS; +} + +#if defined(CONFIG_CMD_FPGA_LOADFS) +static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, + fpga_fs_info *fsinfo) +{ + unsigned long ts; /* Timestamp */ + u32 isr_status, swap; + u32 partialbit = 0; + u32 blocksize; + u32 pos = 0; + int fstype; + char *interface, *dev_part, *filename; + + blocksize = fsinfo->blocksize; + interface = fsinfo->interface; + dev_part = fsinfo->dev_part; + filename = fsinfo->filename; + fstype = fsinfo->fstype; + + if (fs_set_blk_dev(interface, dev_part, fstype)) + return FPGA_FAIL; + + if (fs_read(filename, (u32) buf, pos, blocksize) < 0) + return FPGA_FAIL; + + if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap, + &partialbit)) + return FPGA_FAIL; + + dcache_disable(); + + do { + buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap); + + if (zynq_dma_transfer((u32)buf | 1, blocksize >> 2, + 0xffffffff, 0)) + return FPGA_FAIL; + + bsize -= blocksize; + pos += blocksize; + + if (fs_set_blk_dev(interface, dev_part, fstype)) + return FPGA_FAIL; + + if (bsize > blocksize) { + if (fs_read(filename, (u32) buf, pos, blocksize) < 0) + return FPGA_FAIL; + } else { + if (fs_read(filename, (u32) buf, pos, bsize) < 0) + return FPGA_FAIL; + } + } while (bsize > blocksize); + + buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap); + + if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0)) + return FPGA_FAIL; + + dcache_enable(); + + isr_status = readl(&devcfg_base->int_sts); + + /* Check FPGA configuration completion */ + ts = get_timer(0); + while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + printf("%s: Timeout wait for FPGA to config\n", + __func__); + return FPGA_FAIL; + } + isr_status = readl(&devcfg_base->int_sts); + } + + debug("%s: FPGA config done\n", __func__); + if (!partialbit) zynq_slcr_devcfg_enable(); return FPGA_SUCCESS; } +#endif static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize) { @@ -411,6 +487,9 @@ static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize) struct xilinx_fpga_op zynq_op = { .load = zynq_load, +#if defined(CONFIG_CMD_FPGA_LOADFS) + .loadfs = zynq_loadfs, +#endif .dump = zynq_dump, .info = zynq_info, }; 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