diff options
Diffstat (limited to 'drivers/dma')
| -rw-r--r-- | drivers/dma/Kconfig | 22 | ||||
| -rw-r--r-- | drivers/dma/Makefile | 2 | ||||
| -rw-r--r-- | drivers/dma/dma-uclass.c | 72 | ||||
| -rw-r--r-- | drivers/dma/ti-edma3.c | 82 |
4 files changed, 176 insertions, 2 deletions
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index e69de29..1b92c77 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -0,0 +1,22 @@ +menu "DMA Support" + +config DMA + bool "Enable Driver Model for DMA drivers" + depends on DM + help + Enable driver model for DMA. DMA engines can do + asynchronous data transfers without involving the host + CPU. Currently, this framework can be used to offload + memory copies to and from devices like qspi, ethernet + etc Drivers provide methods to access the DMA devices + buses that is used to transfer data to and from memory. + The uclass interface is defined in include/dma.h. + +config TI_EDMA3 + bool "TI EDMA3 driver" + help + Enable the TI EDMA3 driver for DRA7xx and AM43xx evms. + This driver support data transfer between memory + regions. + +endmenu # menu "DMA Support" diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index f95fe70..39b78b2 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -5,6 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_DMA) += dma-uclass.o + obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o obj-$(CONFIG_APBH_DMA) += apbh_dma.o obj-$(CONFIG_FSL_DMA) += fsl_dma.o diff --git a/drivers/dma/dma-uclass.c b/drivers/dma/dma-uclass.c new file mode 100644 index 0000000..ea21fd9 --- /dev/null +++ b/drivers/dma/dma-uclass.c @@ -0,0 +1,72 @@ +/* + * Direct Memory Access U-Class driver + * + * (C) Copyright 2015 + * Texas Instruments Incorporated, <www.ti.com> + * + * Author: Mugunthan V N <mugunthanvnm@ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dma.h> +#include <dm.h> +#include <dm/uclass-internal.h> +#include <dm/device-internal.h> +#include <errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dma_get_device(u32 transfer_type, struct udevice **devp) +{ + struct udevice *dev; + int ret; + + for (ret = uclass_first_device(UCLASS_DMA, &dev); dev && !ret; + ret = uclass_next_device(&dev)) { + struct dma_dev_priv *uc_priv; + + uc_priv = dev_get_uclass_priv(dev); + if (uc_priv->supported & transfer_type) + break; + } + + if (!dev) { + error("No DMA device found that supports %x type\n", + transfer_type); + return -EPROTONOSUPPORT; + } + + *devp = dev; + + return ret; +} + +int dma_memcpy(void *dst, void *src, size_t len) +{ + struct udevice *dev; + const struct dma_ops *ops; + int ret; + + ret = dma_get_device(DMA_SUPPORTS_MEM_TO_MEM, &dev); + if (ret < 0) + return ret; + + ops = device_get_ops(dev); + if (!ops->transfer) + return -ENOSYS; + + /* Invalidate the area, so no writeback into the RAM races with DMA */ + invalidate_dcache_range((unsigned long)dst, (unsigned long)dst + + roundup(len, ARCH_DMA_MINALIGN)); + + return ops->transfer(dev, DMA_MEM_TO_MEM, dst, src, len); +} + +UCLASS_DRIVER(dma) = { + .id = UCLASS_DMA, + .name = "dma", + .flags = DM_UC_FLAG_SEQ_ALIAS, + .per_device_auto_alloc_size = sizeof(struct dma_dev_priv), +}; diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c index d6a427f..2478438 100644 --- a/drivers/dma/ti-edma3.c +++ b/drivers/dma/ti-edma3.c @@ -11,6 +11,9 @@ #include <asm/io.h> #include <common.h> +#include <dma.h> +#include <dm/device.h> +#include <asm/omap_common.h> #include <asm/ti-common/ti-edma3.h> #define EDMA3_SL_BASE(slot) (0x4000 + ((slot) << 5)) @@ -31,6 +34,10 @@ #define EDMA3_QEESR 0x108c #define EDMA3_QSECR 0x1094 +struct ti_edma3_priv { + u32 base; +}; + /** * qedma3_start - start qdma on a channel * @base: base address of edma @@ -383,8 +390,8 @@ void qedma3_stop(u32 base, struct edma3_channel_config *cfg) __raw_writel(0, base + EDMA3_QCHMAP(cfg->chnum)); } -void edma3_transfer(unsigned long edma3_base_addr, unsigned int - edma_slot_num, void *dst, void *src, size_t len) +void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, + void *dst, void *src, size_t len) { struct edma3_slot_config slot; struct edma3_channel_config edma_channel; @@ -460,3 +467,74 @@ void edma3_transfer(unsigned long edma3_base_addr, unsigned int qedma3_stop(edma3_base_addr, &edma_channel); } } + +#ifndef CONFIG_DMA + +void edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, + void *dst, void *src, size_t len) +{ + __edma3_transfer(edma3_base_addr, edma_slot_num, dst, src, len); +} + +#else + +static int ti_edma3_transfer(struct udevice *dev, int direction, void *dst, + void *src, size_t len) +{ + struct ti_edma3_priv *priv = dev_get_priv(dev); + + /* enable edma3 clocks */ + enable_edma3_clocks(); + + switch (direction) { + case DMA_MEM_TO_MEM: + __edma3_transfer(priv->base, 1, dst, src, len); + break; + default: + error("Transfer type not implemented in DMA driver\n"); + break; + } + + /* disable edma3 clocks */ + disable_edma3_clocks(); + + return 0; +} + +static int ti_edma3_ofdata_to_platdata(struct udevice *dev) +{ + struct ti_edma3_priv *priv = dev_get_priv(dev); + + priv->base = dev_get_addr(dev); + + return 0; +} + +static int ti_edma3_probe(struct udevice *dev) +{ + struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + uc_priv->supported = DMA_SUPPORTS_MEM_TO_MEM; + + return 0; +} + +static const struct dma_ops ti_edma3_ops = { + .transfer = ti_edma3_transfer, +}; + +static const struct udevice_id ti_edma3_ids[] = { + { .compatible = "ti,edma3" }, + { } +}; + +U_BOOT_DRIVER(ti_edma3) = { + .name = "ti_edma3", + .id = UCLASS_DMA, + .of_match = ti_edma3_ids, + .ops = &ti_edma3_ops, + .ofdata_to_platdata = ti_edma3_ofdata_to_platdata, + .probe = ti_edma3_probe, + .priv_auto_alloc_size = sizeof(struct ti_edma3_priv), +}; +#endif /* CONFIG_DMA */ |