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-rw-r--r--drivers/ddr/fsl/ctrl_regs.c28
-rw-r--r--drivers/ddr/fsl/interactive.c2
-rw-r--r--drivers/ddr/fsl/options.c4
3 files changed, 22 insertions, 12 deletions
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index d9cac22..a5ef40f 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -297,10 +297,13 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
unsigned char taxpd_mclk = 0;
/* Mode register set cycle time (tMRD). */
unsigned char tmrd_mclk;
+#if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
+ const unsigned int mclk_ps = get_memory_clk_period_ps();
+#endif
#ifdef CONFIG_SYS_FSL_DDR4
/* tXP=max(4nCK, 6ns) */
- int txp = max((get_memory_clk_period_ps() * 4), 6000); /* unit=ps */
+ int txp = max(mclk_ps * 4, 6000); /* unit=ps */
trwt_mclk = 2;
twrt_mclk = 1;
act_pd_exit_mclk = picos_to_mclk(txp);
@@ -311,16 +314,19 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
*/
tmrd_mclk = max(24, picos_to_mclk(15000));
#elif defined(CONFIG_SYS_FSL_DDR3)
+ unsigned int data_rate = get_ddr_freq(0);
+ int txp;
/*
* (tXARD and tXARDS). Empirical?
* The DDR3 spec has not tXARD,
* we use the tXP instead of it.
- * tXP=max(3nCK, 7.5ns) for DDR3.
+ * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
+ * max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
* spec has not the tAXPD, we use
* tAXPD=1, need design to confirm.
*/
- int txp = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
- unsigned int data_rate = get_ddr_freq(0);
+ txp = max(mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
+
tmrd_mclk = 4;
/* set the turnaround time */
@@ -578,6 +584,9 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
unsigned char cke_pls;
/* Window for four activates (tFAW) */
unsigned short four_act;
+#ifdef CONFIG_SYS_FSL_DDR3
+ const unsigned int mclk_ps = get_memory_clk_period_ps();
+#endif
/* FIXME add check that this must be less than acttorw_mclk */
add_lat_mclk = additive_latency;
@@ -619,10 +628,17 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
#ifdef CONFIG_SYS_FSL_DDR4
cpo = 0;
cke_pls = max(3, picos_to_mclk(5000));
+#elif defined(CONFIG_SYS_FSL_DDR3)
+ /*
+ * cke pulse = max(3nCK, 7.5ns) for DDR3-800
+ * max(3nCK, 5.625ns) for DDR3-1066, 1333
+ * max(3nCK, 5ns) for DDR3-1600, 1866, 2133
+ */
+ cke_pls = max(3, picos_to_mclk(mclk_ps > 1870 ? 7500 :
+ (mclk_ps > 1245 ? 5625 : 5000)));
#else
- cke_pls = picos_to_mclk(popts->tcke_clock_pulse_width_ps);
+ cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
#endif
-
four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
ddr->timing_cfg_2 = (0
diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c
index 6aa16b2..32ba6d8 100644
--- a/drivers/ddr/fsl/interactive.c
+++ b/drivers/ddr/fsl/interactive.c
@@ -517,7 +517,6 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
CTRL_OPTIONS(rcw_2),
CTRL_OPTIONS(ddr_cdr1),
CTRL_OPTIONS(ddr_cdr2),
- CTRL_OPTIONS(tcke_clock_pulse_width_ps),
CTRL_OPTIONS(tfaw_window_four_activates_ps),
CTRL_OPTIONS(trwt_override),
CTRL_OPTIONS(trwt),
@@ -808,7 +807,6 @@ static void print_memctl_options(const memctl_options_t *popts)
CTRL_OPTIONS(rcw_2),
CTRL_OPTIONS_HEX(ddr_cdr1),
CTRL_OPTIONS_HEX(ddr_cdr2),
- CTRL_OPTIONS(tcke_clock_pulse_width_ps),
CTRL_OPTIONS(tfaw_window_four_activates_ps),
CTRL_OPTIONS(trwt_override),
CTRL_OPTIONS(trwt),
diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
index 31cc2bf..6d098d1 100644
--- a/drivers/ddr/fsl/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -777,10 +777,6 @@ unsigned int populate_memctl_options(int all_dimms_registered,
*/
popts->bstopre = 0x100;
- /* Minimum CKE pulse width -- tCKE(MIN) */
- popts->tcke_clock_pulse_width_ps
- = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
-
/*
* Window for four activates -- tFAW
*