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path: root/drivers/ddr/fsl/util.c
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Diffstat (limited to 'drivers/ddr/fsl/util.c')
-rw-r--r--drivers/ddr/fsl/util.c26
1 files changed, 22 insertions, 4 deletions
diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index 7a22aa3..58b519b 100644
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -149,7 +149,7 @@ u32 fsl_ddr_get_intl3r(void)
return val;
}
-void board_add_ram_info(int use_default)
+void print_ddr_info(unsigned int start_ctrl)
{
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
@@ -164,17 +164,25 @@ void board_add_ram_info(int use_default)
int cas_lat;
#if CONFIG_NUM_DDR_CONTROLLERS >= 2
- if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
+ if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
+ (start_ctrl == 1)) {
ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
sdram_cfg = ddr_in32(&ddr->sdram_cfg);
}
#endif
#if CONFIG_NUM_DDR_CONTROLLERS >= 3
- if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
+ if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
+ (start_ctrl == 2)) {
ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
sdram_cfg = ddr_in32(&ddr->sdram_cfg);
}
#endif
+
+ if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
+ puts(" (DDR not enabled)\n");
+ return;
+ }
+
puts(" (DDR");
switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
SDRAM_CFG_SDRAM_TYPE_SHIFT) {
@@ -241,7 +249,7 @@ void board_add_ram_info(int use_default)
#endif
#endif
#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
- if (cs0_config & 0x20000000) {
+ if ((cs0_config & 0x20000000) && (start_ctrl == 0)) {
puts("\n");
puts(" DDR Controller Interleaving Mode: ");
@@ -290,3 +298,13 @@ void board_add_ram_info(int use_default)
}
}
}
+
+void __weak detail_board_ddr_info(void)
+{
+ print_ddr_info(0);
+}
+
+void board_add_ram_info(int use_default)
+{
+ detail_board_ddr_info();
+}