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path: root/drivers/clk/clk-uclass.c
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Diffstat (limited to 'drivers/clk/clk-uclass.c')
-rw-r--r--drivers/clk/clk-uclass.c54
1 files changed, 54 insertions, 0 deletions
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 73dfd7d..b483c1e 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -12,6 +12,8 @@
#include <dm/lists.h>
#include <dm/root.h>
+DECLARE_GLOBAL_DATA_PTR;
+
ulong clk_get_rate(struct udevice *dev)
{
struct clk_ops *ops = clk_get_ops(dev);
@@ -32,6 +34,16 @@ ulong clk_set_rate(struct udevice *dev, ulong rate)
return ops->set_rate(dev, rate);
}
+int clk_enable(struct udevice *dev, int periph)
+{
+ struct clk_ops *ops = clk_get_ops(dev);
+
+ if (!ops->enable)
+ return -ENOSYS;
+
+ return ops->enable(dev, periph);
+}
+
ulong clk_get_periph_rate(struct udevice *dev, int periph)
{
struct clk_ops *ops = clk_get_ops(dev);
@@ -52,6 +64,48 @@ ulong clk_set_periph_rate(struct udevice *dev, int periph, ulong rate)
return ops->set_periph_rate(dev, periph, rate);
}
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+int clk_get_by_index(struct udevice *dev, int index, struct udevice **clk_devp)
+{
+ int ret;
+#ifdef CONFIG_SPL_BUILD
+ u32 cell[2];
+
+ if (index != 0)
+ return -ENOSYS;
+ assert(*clk_devp);
+ ret = uclass_get_device(UCLASS_CLK, 0, clk_devp);
+ if (ret)
+ return ret;
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clocks",
+ cell, 2);
+ if (ret)
+ return ret;
+ return cell[1];
+#else
+ struct fdtdec_phandle_args args;
+
+ assert(*clk_devp);
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+ "clocks", "#clock-cells", 0, index,
+ &args);
+ if (ret) {
+ debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, clk_devp);
+ if (ret) {
+ debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
+ __func__, ret);
+ return ret;
+ }
+ return args.args_count > 0 ? args.args[0] : 0;
+#endif
+}
+#endif
+
UCLASS_DRIVER(clk) = {
.id = UCLASS_CLK,
.name = "clk",