diff options
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/README.at91 | 2 | ||||
| -rw-r--r-- | doc/README.kmeter1 | 91 | ||||
| -rw-r--r-- | doc/README.korat | 13 | ||||
| -rw-r--r-- | doc/README.mpc8572ds | 166 | ||||
| -rw-r--r-- | doc/README.nand | 2 | ||||
| -rw-r--r-- | doc/README.nios_CONFIG_SYS_NIOS_CPU | 140 | ||||
| -rw-r--r-- | doc/README.nmdk8815 | 22 | ||||
| -rw-r--r-- | doc/README.omap3 | 116 | ||||
| -rw-r--r-- | doc/README.qemu_mips | 88 | ||||
| -rw-r--r-- | doc/README.simpc8313 | 80 | ||||
| -rw-r--r-- | doc/feature-removal-schedule.txt | 37 |
11 files changed, 753 insertions, 4 deletions
diff --git a/doc/README.at91 b/doc/README.at91 index 838769a..4e3928a 100644 --- a/doc/README.at91 +++ b/doc/README.at91 @@ -3,7 +3,7 @@ Atmel AT91 Evaluation kits http://atmel.com/dyn/products/tools.asp?family_id=605#1443 ------------------------------------------------------------------------------ -AT91SAM9260EK +AT91SAM9260EK & AT91SAM9XEEK ------------------------------------------------------------------------------ Memory map diff --git a/doc/README.kmeter1 b/doc/README.kmeter1 new file mode 100644 index 0000000..44ebb7a --- /dev/null +++ b/doc/README.kmeter1 @@ -0,0 +1,91 @@ +Keymile kmeter1 Board +----------------------------------------- +1. Alternative Boot EEPROM + + Upon the kmeter1 startup the I2C_1 controller is used to fetch the boot + configuration from a serial EEPROM. During the development and debugging + phase it might be helpful to apply an alternative boot configuration in + a simple way. Therefore it is an alternative boot eeprom on the PIGGY, + which can be activated by setting the "ST" jumper on the PIGGY board. + +2. Memory Map + + BaseAddr PortSz Size Device + ----------- ------ ----- ------ + 0x0000_0000 64 bit 256MB DDR + 0x8000_0000 8 bit 256KB GPIO/PIGGY on CS1 + 0xa000_0000 8 bit 256MB PAXE on CS3 + 0xe000_0000 2MB Int Mem Reg Space + 0xf000_0000 16 bit 256MB FLASH on CS0 + + + DDR-SDRAM: + The current realization is made with four 16-bits memory devices. + Mounting options have been foreseen for device architectures from + 4Mx16 to 512Mx16. The kmeter1 is equipped with four 32Mx16 devices + thus resulting in a total capacity of 256MBytes. + +3. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + make kmeter1_config + make + +4. Downloading and Flashing Images + +4.0 Download over serial line using Kermit: + + loadb + [Drop to kermit: + ^\c + send <u-boot-bin-image> + c + ] + + + Or via tftp: + + tftp 10000 u-boot.bin + => run load + Using FSL UEC0 device + TFTP from server 192.168.1.1; our IP address is 192.168.205.4 + Filename '/tftpboot/kmeter1/u-boot.bin'. + Load address: 0x200000 + Loading: ############## + done + Bytes transferred = 204204 (31dac hex) + => + +4.1 Reflash U-boot Image using U-boot + + => run update + ..... done + Un-Protected 5 sectors + + ..... done + Erased 5 sectors + Copy to Flash... done + ..... done + Protected 5 sectors + Total of 204204 bytes were the same + Saving Environment to Flash... + . done + Un-Protected 1 sectors + . done + Un-Protected 1 sectors + Erasing Flash... + . done + Erased 1 sectors + Writing to Flash... done + . done + Protected 1 sectors + . done + Protected 1 sectors + => + +5. Notes + 1) The console baudrate for kmeter1 is 115200bps. diff --git a/doc/README.korat b/doc/README.korat index 0a59f40..a753f84 100644 --- a/doc/README.korat +++ b/doc/README.korat @@ -49,3 +49,16 @@ creates the upgradable U-Boot but selecting loader file "u-boot-F7FC.lds" and leaving preprocessor symbol "CONFIG_KORAT_PERMANENT" undefined. 2008-02-22, Larry Johnson <lrj@acm.org> + + +The CompactFlash(R) controller on the Korat board provides a hi-speed USB +interface. This may be connected to either a dedicated port on the on-board +USB controller, or to a USB port on the PowerPC 440EPx processor. The U-Boot +environment variable "korat_usbcf" can be used to specify which of these two +USB host ports is used for CompactFlash. The valid setting for the variable are +the strings "pci" and "ppc". If the variable defined and set to "ppc", then the +PowerPC USB port is used. In all other cases the on-board USB controller is +used, but if "korat_usbcf" is defined but is set to a string other than the two +valid options, a warning is also issued. + +2009-01-28, Larry Johnson <lrj@acm.org> diff --git a/doc/README.mpc8572ds b/doc/README.mpc8572ds new file mode 100644 index 0000000..06dab59 --- /dev/null +++ b/doc/README.mpc8572ds @@ -0,0 +1,166 @@ +Overview +-------- +MPC8572DS is a high-performance computing, evaluation and development platform +supporting the mpc8572 PowerTM processor. + +Building U-boot +----------- + make MPC8572DS_config + make + +Flash Banks +----------- +MPC8572DS board has two flash banks. They are both present on boot, but their +locations can be swapped using the dip-switch SW9[1:2]. + +Booting is always from the boot bank at 0xec00_0000. + + +Memory Map +---------- + +0xe800_0000 - 0xebff_ffff Alernate bank 64MB +0xec00_0000 - 0xefff_ffff Boot bank 64MB + +0xebf8_0000 - 0xebff_ffff Alternate u-boot address 512KB +0xeff8_0000 - 0xefff_ffff Boot u-boot address 512KB + + +Flashing Images +--------------- + +To place a new u-boot image in the alternate flash bank and then reset with that + new image temporarily, use this: + + tftp 1000000 u-boot.bin + erase ebf80000 ebffffff + cp.b 1000000 ebf80000 80000 + pixis_reset altbank + + +To program the image in the boot flash bank: + + tftp 1000000 u-boot.bin + protect off all + erase eff80000 ffffffff + cp.b 1000000 eff80000 80000 + + +The pixis_reset command +----------------------- +The command - "pixis_reset", is introduced to reset mpc8572ds board +using the FPGA sequencer. When the board restarts, it has the option +of using either the current or alternate flash bank as the boot +image, with or without the watchdog timer enabled, and finally with +or without frequency changes. + +Usage is; + + pixis_reset + pixis_reset altbank + pixis_reset altbank wd + pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> + pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> + +Examples: + + /* reset to current bank, like "reset" command */ + pixis_reset + + /* reset board but use the to alternate flash bank */ + pixis_reset altbank + + +Using the Device Tree Source File +--------------------------------- +To create the DTB (Device Tree Binary) image file, +use a command similar to this: + + dtc -b 0 -f -I dts -O dtb mpc8572ds.dts > mpc8572ds.dtb + +Likely, that .dts file will come from here; + + linux-2.6/arch/powerpc/boot/dts/mpc8572ds.dts + + +Booting Linux +------------- + +Place a linux uImage in the TFTP disk area. + + tftp 1000000 uImage.8572 + tftp c00000 mpc8572ds.dtb + bootm 1000000 - c00000 + + +Implementing AMP(Asymmetric MultiProcessing) +------------- +1. Build kernel image for core0: + + a. $ make 85xx/mpc8572_ds_defconfig + + b. $ make menuconfig + - un-select "Processor support"->"Symetric multi-processing support" + + c. $ make uImage + + d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0 + +2. Build kernel image for core1: + + a. $ make 85xx/mpc8572_ds_defconfig + + b. $ make menuconfig + - Un-select "Processor support"->"Symetric multi-processing support" + - Select "Advanced setup" -> " Prompt for advanced kernel + configuration options" + - Select "Set physical address where the kernel is loaded" and + set it to 0x20000000, asssuming core1 will start from 512MB. + - Select "Set custom page offset address" + - Select "Set custom kernel base address" + - Select "Set maximum low memory" + - "Exit" and save the selection. + + c. $ make uImage + + d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1 + +3. Create dtb for core0: + + $ dtc -I dts -O dtb -f -b 0 arch/powerpc/boot/dts/mpc8572ds_core0.dts > /tftpboot/mpc8572ds_core0.dtb + +4. Create dtb for core1: + + $ dtc -I dts -O dtb -f -b 1 arch/powerpc/boot/dts/mpc8572ds_core1.dts > /tftpboot/mpc8572ds_core1.dtb + +5. Bring up two cores separately: + + a. Power on the board, under u-boot prompt: + => setenv <serverip> + => setenv <ipaddr> + => setenv bootargs root=/dev/ram rw console=ttyS0,115200 + b. Bring up core1's kernel first: + => setenv bootm_low 0x20000000 + => setenv bootm_size 0x10000000 + => tftp 21000000 8572/uImage.core1 + => tftp 22000000 8572/ramdiskfile + => tftp 20c00000 8572/mpc8572ds_core1.dtb + => interrupts off + => bootm start 21000000 22000000 20c00000 + => bootm loados + => bootm ramdisk + => bootm fdt + => fdt boardsetup + => fdt chosen $initrd_start $initrd_end + => bootm prep + => cpu 1 release $bootm_low - $fdtaddr - + c. Bring up core0's kernel(on the same u-boot console): + => setenv bootm_low 0 + => setenv bootm_size 0x20000000 + => tftp 1000000 8572/uImage.core0 + => tftp 2000000 8572/ramdiskfile + => tftp c00000 8572/mpc8572ds_core0.dtb + => bootm 1000000 2000000 c00000 + +Please note only core0 will run u-boot, core1 starts kernel directly after +"cpu release" command is issued. diff --git a/doc/README.nand b/doc/README.nand index bf80bc0..fc62f92 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -172,7 +172,7 @@ More Definitions: #define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 - #define NAND_MAX_CHIPS 1 + #define CONFIG_SYS_NAND_MAX_CHIPS 1 #define CONFIG_SYS_DAVINCI_BROKEN_ECC Versions of U-Boot <= 1.3.3 and Montavista Linux kernels diff --git a/doc/README.nios_CONFIG_SYS_NIOS_CPU b/doc/README.nios_CONFIG_SYS_NIOS_CPU new file mode 100644 index 0000000..3547c34 --- /dev/null +++ b/doc/README.nios_CONFIG_SYS_NIOS_CPU @@ -0,0 +1,140 @@ + +=============================================================================== + C F G _ N I O S _ C P U _ * v s . N I O S S D K +=============================================================================== + +When ever you have to make a new NIOS CPU configuration you can use this table +as a reference list to the original NIOS SDK symbols made by Alteras SOPC +Builder. Look into excalibur.h and excalibur.s in your SDK path cpu_sdk/inc. +Symbols beginning with a '[ptf]:' are coming from your SOPC sytem description +(PTF file) in sections WIZARD_SCRIPT_ARGUMENTS or SYSTEM_BUILDER_INFO. + +C O R E N I O S S D K [1],[7] +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_CLK nasys_clock_freq +CONFIG_SYS_NIOS_CPU_ICACHE nasys_icache_size +CONFIG_SYS_NIOS_CPU_DCACHE nasys_dcache_size +CONFIG_SYS_NIOS_CPU_REG_NUMS nasys_nios_num_regs +CONFIG_SYS_NIOS_CPU_MUL __nios_use_multiply__ +CONFIG_SYS_NIOS_CPU_MSTEP __nios_use_mstep__ +CONFIG_SYS_NIOS_CPU_STACK nasys_stack_top +CONFIG_SYS_NIOS_CPU_VEC_BASE nasys_vector_table +CONFIG_SYS_NIOS_CPU_VEC_SIZE nasys_vector_table_size +CONFIG_SYS_NIOS_CPU_VEC_NUMS +CONFIG_SYS_NIOS_CPU_RST_VECT nasys_reset_address +CONFIG_SYS_NIOS_CPU_DBG_CORE nasys_debug_core +CONFIG_SYS_NIOS_CPU_RAM_BASE na_onchip_ram_64_kbytes +CONFIG_SYS_NIOS_CPU_RAM_SIZE na_onchip_ram_64_kbytes_size +CONFIG_SYS_NIOS_CPU_ROM_BASE na_boot_monitor_rom +CONFIG_SYS_NIOS_CPU_ROM_SIZE na_boot_monitor_rom_size +CONFIG_SYS_NIOS_CPU_OCI_BASE nasys_oci_core +CONFIG_SYS_NIOS_CPU_OCI_SIZE +CONFIG_SYS_NIOS_CPU_SRAM_BASE na_ext_ram nasys_program_mem + nasys_data_mem +CONFIG_SYS_NIOS_CPU_SRAM_SIZE na_ext_ram_size nasys_program_mem_size + nasys_data_mem_size +CONFIG_SYS_NIOS_CPU_SDRAM_BASE na_sdram +CONFIG_SYS_NIOS_CPU_SDRAM_SIZE na_sdram_size +CONFIG_SYS_NIOS_CPU_FLASH_BASE na_ext_flash nasys_main_flash + nasys_am29lv065d_flash_0 + nasys_flash_0 +CONFIG_SYS_NIOS_CPU_FLASH_SIZE na_ext_flash_size nasys_main_flash_size + +T I M E R N I O S S D K [3] +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_TIMER_NUMS nasys_timer_count +CONFIG_SYS_NIOS_CPU_TIMER[0-9] nasys_timer_[0-9] +CONFIG_SYS_NIOS_CPU_TIMER[0-9]_IRQ nasys_timer_[0-9]_irq +CONFIG_SYS_NIOS_CPU_TIMER[0-9]_PER [ptf]:period + [ptf]:period_units + [ptf]:mult +CONFIG_SYS_NIOS_CPU_TIMER[0-9]_AR [ptf]:always_run +CONFIG_SYS_NIOS_CPU_TIMER[0-9]_FP [ptf]:fixed_period +CONFIG_SYS_NIOS_CPU_TIMER[0-9]_SS [ptf]:snapshot + +U A R T N I O S S D K [2] +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_UART_NUMS nasys_uart_count +CONFIG_SYS_NIOS_CPU_UART[0-9] nasys_uart_[0-9] +CONFIG_SYS_NIOS_CPU_UART[0-9]_IRQ nasys_uart_[0-9]_irq +CONFIG_SYS_NIOS_CPU_UART[0-9]_BR [ptf]:baud +CONFIG_SYS_NIOS_CPU_UART[0-9]_DB [ptf]:data_bits +CONFIG_SYS_NIOS_CPU_UART[0-9]_SB [ptf]:stop_bits +CONFIG_SYS_NIOS_CPU_UART[0-9]_PA [ptf]:parity +CONFIG_SYS_NIOS_CPU_UART[0-9]_HS [ptf]:use_cts_rts +CONFIG_SYS_NIOS_CPU_UART[0-9]_EOP [ptf]:use_eop_register + +P I O N I O S S D K [4] +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_PIO_NUMS nasys_pio_count +CONFIG_SYS_NIOS_CPU_PIO[0-9] nasys_pio_[0-9] +CONFIG_SYS_NIOS_CPU_PIO[0-9]_IRQ nasys_pio_[0-9]_irq +CONFIG_SYS_NIOS_CPU_PIO[0-9]_BITS [ptf]:Data_Width +CONFIG_SYS_NIOS_CPU_PIO[0-9]_TYPE [ptf]:has_tri + [ptf]:has_out + [ptf]:has_in +CONFIG_SYS_NIOS_CPU_PIO[0-9]_CAP [ptf]:capture +CONFIG_SYS_NIOS_CPU_PIO[0-9]_EDGE [ptf]:edge_type +CONFIG_SYS_NIOS_CPU_PIO[0-9]_ITYPE [ptf]:irq_type + +S P I N I O S S D K [6] +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_SPI_NUMS nasys_spi_count +CONFIG_SYS_NIOS_CPU_SPI[0-9] nasys_spi_[0-9] +CONFIG_SYS_NIOS_CPU_SPI[0-9]_IRQ nasys_spi_[0-9]_irq +CONFIG_SYS_NIOS_CPU_SPI[0-9]_BITS [ptf]:databits +CONFIG_SYS_NIOS_CPU_SPI[0-9]_MA [ptf]:ismaster +CONFIG_SYS_NIOS_CPU_SPI[0-9]_SLN [ptf]:numslaves +CONFIG_SYS_NIOS_CPU_SPI[0-9]_TCLK [ptf]:targetclock +CONFIG_SYS_NIOS_CPU_SPI[0-9]_TDELAY [ptf]:targetdelay +CONFIG_SYS_NIOS_CPU_SPI[0-9]_* [ptf]:* + +I D E N I O S S D K +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_IDE_NUMS nasys_usersocket_count +CONFIG_SYS_NIOS_CPU_IDE[0-9] nasys_usersocket_[0-9] + +A S M I N I O S S D K [5] +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_ASMI_NUMS nasys_asmi_count +CONFIG_SYS_NIOS_CPU_ASMI[0-9] nasys_asmi_[0-9] +CONFIG_SYS_NIOS_CPU_ASMI[0-9]_IRQ nasys_asmi_[0-9]_irq + +E t h e r n e t ( L A N ) N I O S S D K +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_LAN_NUMS +CONFIG_SYS_NIOS_CPU_LAN[0-9]_BASE na_lan91c111 +CONFIG_SYS_NIOS_CPU_LAN[0-9]_OFFS LAN91C111_REGISTERS_OFFSET +CONFIG_SYS_NIOS_CPU_LAN[0-9]_IRQ na_lan91c111_irq +CONFIG_SYS_NIOS_CPU_LAN[0-9]_BUSW LAN91C111_DATA_BUS_WIDTH +CONFIG_SYS_NIOS_CPU_LAN[0-9]_TYPE + +s y s t e m c o m p o s i n g N I O S S D K +------------------------------------------------------------------------------- +CONFIG_SYS_NIOS_CPU_TICK_TIMER (na_low_priority_timer2) +CONFIG_SYS_NIOS_CPU_USER_TIMER (na_timer1) +CONFIG_SYS_NIOS_CPU_BUTTON_PIO (na_button_pio) +CONFIG_SYS_NIOS_CPU_LCD_PIO (na_lcd_pio) +CONFIG_SYS_NIOS_CPU_LED_PIO (na_led_pio) +CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO (na_seven_seg_pio) +CONFIG_SYS_NIOS_CPU_RECONF_PIO (na_reconfig_request_pio) +CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO (na_cf_present_pio) +CONFIG_SYS_NIOS_CPU_CFPOWER_PIO (na_cf_power_pio) +CONFIG_SYS_NIOS_CPU_CFATASEL_PIO (na_cf_ata_select_pio) +CONFIG_SYS_NIOS_CPU_USER_SPI (na_spi) + + +=============================================================================== + R E F E R E N C E S +=============================================================================== +[1] http://www.altera.com/literature/ds/ds_nioscpu.pdf +[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf +[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf +[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf +[5] http://www.altera.com/literature/ds/ds_nios_asmi.pdf +[6] http://www.altera.com/literature/ds/ds_nios_spi.pdf +[7] http://www.altera.com/literature/ds/ds_legacy_sdram_ctrl.pdf + + +=============================================================================== +Stephan Linz <linz@li-pro.net> diff --git a/doc/README.nmdk8815 b/doc/README.nmdk8815 new file mode 100644 index 0000000..453cfae --- /dev/null +++ b/doc/README.nmdk8815 @@ -0,0 +1,22 @@ + +The Nomadik 8815 CPU has a "secure" boot mode where no external access +(not even JTAG) is allowed. The "remap" bits in the evaluation board +are configured in order to boot from the internal ROM memory (in +secure mode). + +The boot process as defined by the manufacturer executes external code +(loaded from NAND or OneNAND) that that disables such "security" in +order to run u-boot and later the kernel without constraints. Such +code is a proprietary initial boot loader, called "X-Loader" (in case +anyone wonders, it has no relations with other loaders with the same +name and there is no GPL code inside the ST X-Loader). + +SDRAM configuration, PLL setup and initial loading from NAND is +implemented in the X-Loader, so U-Boot is already running in SDRAM +when control is handed over to it. + + +On www.st.com/nomadik and on www.stnwireless.com there are documents, +summary data and white papers on Nomadik. The full datasheet for +STn8815 is not currently available on line but under specific request +to the local ST sales offices. diff --git a/doc/README.omap3 b/doc/README.omap3 new file mode 100644 index 0000000..1ba307f --- /dev/null +++ b/doc/README.omap3 @@ -0,0 +1,116 @@ + +Summary +======= + +This README is about U-Boot support for TI's ARM Cortex-A8 based OMAP3 [1] +family of SoCs. TI's OMAP3 SoC family contains an ARM Cortex-A8. Additionally, +some family members contain a TMS320C64x+ DSP and/or an Imagination SGX 2D/3D +graphics processor and various other standard peripherals. + +Currently the following boards are supported: + +* OMAP3530 BeagleBoard [2] + +* Gumstix Overo [3] + +* TI EVM [4] + +* OpenPandora Ltd. Pandora [5] + +* TI/Logic PD Zoom MDK [6] + +Toolchain +========= + +While ARM Cortex-A8 support ARM v7 instruction set (-march=armv7a) we compile +with -march=armv5 to allow more compilers to work. For U-Boot code this has +no performance impact. + +Build +===== + +* BeagleBoard: + +make omap3_beagle_config +make + +* Gumstix Overo: + +make omap3_overo_config +make + +* TI EVM: + +make omap3_evm_config +make + +* Pandora: + +make omap3_pandora_config +make + +* Zoom MDK: + +make omap3_zoom1_config +make + +Custom commands +=============== + +To make U-Boot for OMAP3 support NAND device SW or HW ECC calculation, U-Boot +for OMAP3 supports custom user command + +nandecc hw/sw + +To be compatible with NAND drivers using SW ECC (e.g. kernel code) + +nandecc sw + +enables SW ECC calculation. HW ECC enabled with + +nandecc hw + +is typically used to write 2nd stage bootloader (known as 'x-loader') which is +executed by OMAP3's boot rom and therefore has to be written with HW ECC. + +For all other commands see + +help + +Acknowledgements +================ + +OMAP3 U-Boot is based on U-Boot tar ball [7] for BeagleBoard and EVM done by +several TI employees. + +Links +===== + +[1] OMAP3: + +http://www.ti.com/omap3 (high volume) and +http://www.ti.com/omap35x (broad market) + +[2] OMAP3530 BeagleBoard: + +http://beagleboard.org/ + +[3] Gumstix Overo: + +http://www.gumstix.net/Overo/ + +[4] TI EVM: + +http://focus.ti.com/docs/toolsw/folders/print/tmdxevm3503.html + +[5] OpenPandora Ltd. Pandora: + +http://openpandora.org/ + +[6] TI/Logic PD Zoom MDK: + +http://www.logicpd.com/products/devkit/ti/zoom_mobile_development_kit + +[7] TI OMAP3 U-Boot: + +http://beagleboard.googlecode.com/files/u-boot_beagle_revb.tar.gz diff --git a/doc/README.qemu_mips b/doc/README.qemu_mips index 2fdd2b0..3985264 100644 --- a/doc/README.qemu_mips +++ b/doc/README.qemu_mips @@ -17,19 +17,103 @@ create image: start it: # qemu-system-mips -M mips -pflash flash -monitor null -nographic +2) Download kernel + initrd + +On ftp://ftp.denx.de/pub/contrib/Jean-Christophe_Plagniol-Villard/qemu_mips/ +you can downland + +#config to build the kernel +qemu_mips_defconfig +#patch to fix mips interupt init on 2.6.24.y kernel +qemu_mips_kernel.patch +initrd.gz +vmlinux +vmlinux.bin +System.map + +4) Generate uImage + +# tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x80010000 -e 0x80245650 -n "Linux 2.6.24.y" -d vmlinux.bin.gz uImage + +5) Copy uImage to Flash +# dd if=uImage bs=1k conv=notrunc seek=224 of=flash + +6) Generate Ide Disk + +# dd of=ide bs=1k cout=100k if=/dev/zero + +# sfdisk -C 261 -d ide +# partition table of ide +unit: sectors + + ide1 : start= 63, size= 32067, Id=83 + ide2 : start= 32130, size= 32130, Id=83 + ide3 : start= 64260, size= 4128705, Id=83 + ide4 : start= 0, size= 0, Id= 0 + +7) Copy to ide + +# dd if=uImage bs=512 conv=notrunc seek=63 of=ide + +8) Generate ext2 on part 2 on Copy uImage and initrd.gz + +# Attached as loop device ide offset = 32130 * 512 +# losetup -o 16450560 -f ide +# Format as ext2 ( arg2 : nb blocks) +# mke2fs /dev/loop0 16065 +# losetup -d /dev/loop0 +# Mount and copy uImage and initrd.gz to it +# mount -o loop,offset=16450560 -t ext2 ide /mnt +# mkdir /mnt/boot +# cp {initrd.gz,uImage} /mnt/boot/ +# Umount it +# umount /mnt + +9) Set Environment + +setenv rd_start 0x80800000 +setenv rd_size 2663940 +setenv kernel BFC38000 +setenv oad_addr 80500000 +setenv load_addr2 80F00000 +setenv kernel_flash BFC38000 +setenv load_addr_hello 80200000 +setenv bootargs 'root=/dev/ram0 init=/bin/sh' +setenv load_rd_ext2 'ide res; ext2load ide 0:2 ${rd_start} /boot/initrd.gz' +setenv load_rd_tftp 'tftp ${rd_start} /initrd.gz' +setenv load_kernel_hda 'ide res; diskboot ${load_addr} 0:2' +setenv load_kernel_ext2 'ide res; ext2load ide 0:2 ${load_addr} /boot/uImage' +setenv load_kernel_tftp 'tftp ${load_addr} /qemu_mips/uImage' +setenv boot_ext2_ext2 'run load_rd_ext2; run load_kernel_ext2; run addmisc; bootm ${load_addr}' +setenv boot_ext2_flash 'run load_rd_ext2; run addmisc; bootm ${kernel_flash}' +setenv boot_ext2_hda 'run load_rd_ext2; run load_kernel_hda; run addmisc; bootm ${load_addr}' +setenv boot_ext2_tftp 'run load_rd_ext2; run load_kernel_tftp; run addmisc; bootm ${load_addr}' +setenv boot_tftp_hda 'run load_rd_tftp; run load_kernel_hda; run addmisc; bootm ${load_addr}' +setenv boot_tftp_ext2 'run load_rd_tftp; run load_kernel_ext2; run addmisc; bootm ${load_addr}' +setenv boot_tftp_flash 'run load_rd_tftp; run addmisc; bootm ${kernel_flash}' +setenv boot_tftp_tftp 'run load_rd_tftp; run load_kernel_tftp; run addmisc; bootm ${load_addr}' +setenv load_hello_tftp 'tftp ${load_addr_hello} /examples/hello_world.bin' +setenv go_tftp 'run load_hello_tftp; go ${load_addr_hello}' +setenv addmisc 'setenv bootargs ${bootargs} console=ttyS0,${baudrate} rd_start=${rd_start} rd_size=${rd_size} ethaddr=${ethaddr}' +setenv bootcmd 'run boot_tftp_flash' + +10) Now you can boot from flash, ide, ide+ext2 and tfp + +# qemu-system-mips -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide + II) How to debug U-Boot In order to debug U-Boot you need to start qemu with gdb server support (-s) and waiting the connection to start the CPU (-S) -# qemu-system-mips -S -s -M mips -pflash flash -monitor null -nographic +# qemu-system-mips -S -s -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide in an other console you start gdb 1) Debugging of U-Boot Before Relocation Before relocation, the addresses in the ELF file can be used without any problems -buy connecting to the gdb server localhost:1234 +by connecting to the gdb server localhost:1234 # mipsel-unknown-linux-gnu-gdb u-boot GNU gdb 6.6 diff --git a/doc/README.simpc8313 b/doc/README.simpc8313 new file mode 100644 index 0000000..b362c6a --- /dev/null +++ b/doc/README.simpc8313 @@ -0,0 +1,80 @@ +Sheldon Instruments SIMPC8313 Board +----------------------------------------- + +1. Board Switches and Jumpers + + S2 is used to set CFG_RESET_SOURCE. + + To boot the image in Large page NAND flash, use these DIP + switch settings for S2: + + +----------+ ON + | * * **** | + | * * | + +----------+ + 12345678 + + To boot the image in Small page NAND flash, use these DIP + switch settings for S2: + + +----------+ ON + | *** **** | + | * | + +----------+ + 12345678 + (where the '*' indicates the position of the tab of the switch.) + +2. Memory Map + The memory map looks like this: + + 0x0000_0000 0x1fff_ffff DDR 512M + 0x8000_0000 0x8fff_ffff PCI MEM 256M + 0x9000_0000 0x9fff_ffff PCI_MMIO 256M + 0xe000_0000 0xe00f_ffff IMMR 1M + 0xe200_0000 0xe20f_ffff PCI IO 16M + 0xe280_0000 0xe280_7fff NAND FLASH (CS0) 32K + or + 0xe280_0000 0xe281_ffff NAND FLASH (CS0) 128K + 0xff00_0000 0xff00_7fff FPGA (CS1) 1M + +3. Compilation + + Assuming you're using BASH (or similar) as your shell: + + export CROSS_COMPILE=your-cross-compiler-prefix- + make distclean + make SIMPC8313_LP_config + (or make SIMPC8313_SP_config, depending on the page size + of your NAND flash) + make + +4. Downloading and Flashing Images + +4.1 Reflash U-boot Image using U-boot + + =>run update_uboot + + You may want to try + =>tftp $loadaddr $uboot + first, to make sure that the TFTP load will succeed before it + goes ahead and wipes out your current firmware. And of course, + if the new u-boot doesn't boot, you can plug the board into + your PCI slot and with the supplied driver and sample app + you can reburn a working u-boot. + +4.2 Downloading and Booting Linux Kernel + + Ensure that all networking-related environment variables are set + properly (including ipaddr, serverip, gatewayip (if needed), + netmask, ethaddr, eth1addr, fdtfile, and bootfile). + + =>tftp $loadaddr uImage + =>nand write $loadaddr kernel $filesize + =>tftp $loadaddr $fdtfile + =>nand write $loadaddr 7e0000 1800 + + =>boot + +5 Notes + + The console baudrate for SIMPC8313 is 115200bps. diff --git a/doc/feature-removal-schedule.txt b/doc/feature-removal-schedule.txt new file mode 100644 index 0000000..9ba7a04 --- /dev/null +++ b/doc/feature-removal-schedule.txt @@ -0,0 +1,37 @@ +The following is a list of files and features that are going to be +removed from the U-Boot source tree. Every entry should contain what +exactly is going away, when it will be gone, why it is being removed, +and who is going to be doing the work. When the feature is removed +from U-Boot, its corresponding entry should also be removed from this +file. + +--------------------------- + +What: "autoscr" command +When: August 2009 +Why: "autosrc" is an ugly and completely non-standard name. The "autoscr" + command is deprecated and will be replaced the "source" command as + used by other shells such as bash. Both commands will be supported + for a transition period of 6 months after which "autoscr" will be + removed. +Who: Peter Tyser <ptyser@xes-inc.com> + +--------------------------- + +What: Individual I2C commands +When: April 2009 +Why: Per the U-Boot README, individual I2C commands such as "imd", "imm", + "imw", etc are deprecated. The single "i2c" command which is + currently enabled via CONFIG_I2C_CMD_TREE contains the same + functionality as the individual I2C commands. The individual + I2C commands should be removed as well as any references to + CONFIG_I2C_CMD_TREE. +Who: Peter Tyser <ptyser@xes-inc.com> + +--------------------------- + +What: Legacy NAND code +When: April 2009 +Why: Legacy NAND code is deprecated. Similar functionality exists in + more recent NAND code ported from the Linux kernel. +Who: Scott Wood <scottwood@freescale.com> |