diff options
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/README.dfutftp | 114 | ||||
| -rw-r--r-- | doc/README.fec_mxc | 9 | ||||
| -rw-r--r-- | doc/README.imx5 | 12 | ||||
| -rw-r--r-- | doc/README.omap3 | 4 | ||||
| -rw-r--r-- | doc/README.pxe | 9 | ||||
| -rw-r--r-- | doc/README.rockchip | 247 | ||||
| -rw-r--r-- | doc/README.scrapyard | 12 | ||||
| -rw-r--r-- | doc/README.switch_config | 25 | ||||
| -rw-r--r-- | doc/README.update | 7 | ||||
| -rw-r--r-- | doc/README.watchdog | 1 | ||||
| -rw-r--r-- | doc/README.x86 | 2 | ||||
| -rw-r--r-- | doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt | 61 | ||||
| -rw-r--r-- | doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt | 61 | ||||
| -rw-r--r-- | doc/device-tree-bindings/clock/rockchip,rk3288-dmc.txt | 155 | ||||
| -rw-r--r-- | doc/device-tree-bindings/clock/rockchip.txt | 77 | ||||
| -rw-r--r-- | doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt | 157 | ||||
| -rw-r--r-- | doc/device-tree-bindings/thermal/rockchip-thermal.txt | 68 | ||||
| -rw-r--r-- | doc/git-mailrc | 5 |
18 files changed, 992 insertions, 34 deletions
diff --git a/doc/README.dfutftp b/doc/README.dfutftp new file mode 100644 index 0000000..0257f0d --- /dev/null +++ b/doc/README.dfutftp @@ -0,0 +1,114 @@ +Device Firmware Upgrade (DFU) - extension to use TFTP +===================================================== + +Why? +---- + +* Update TFTP (CONFIG_UPDATE_TFTP) only supports writing +code to NAND memory via TFTP. +* DFU supports writing data to the variety of mediums (NAND, +eMMC, SD, partitions, RAM, etc) via USB. + +Combination of both solves their shortcomings! + + +Overview +-------- + +This document briefly describes how to use DFU for +upgrading firmware (e.g. kernel, u-boot, rootfs, etc.) +via TFTP protocol. + +By using Ethernet (TFTP protocol to be precise) it is +possible to overcome the major problem of USB based DFU - +the relatively low transfer speed for large files. +This was caused by DFU standard, which imposed utilization +of only EP0 for transfer. By using Ethernet we can circumvent +this shortcoming. + +Beagle Bone Black rev. C (BBB) powered by TI's am335x CPU has +been used as a demo board. + +To utilize this feature, one needs to first enable support +for USB based DFU (CONFIG_DFU_*) and DFU TFTP update +(CONFIG_DFU_TFTP) described in ./doc/README.update. + +The "dfu" command has been extended to support transfer via TFTP - one +needs to type for example "dfu tftp 0 mmc 0" + +This feature does not depend on "fitupd" command enabled. + +As of this writing (SHA1:8d77576371381ade83de475bb639949b44941e8c v2015.10-rc2) +the update.c code is not enabled (CONFIG_UPDATE_TFTP) by any board in the +contemporary u-boot tree. + + +Environment variables +--------------------- + +The "dfu tftp" command can be used in the "preboot" environment variable +(when it is enabled by defining CONFIG_PREBOOT). +This is the preferable way of using this command in the early boot stage +as opposed to legacy update_tftp() function invocation. + + +Beagle Bone Black (BBB) setup +----------------------------- + +1. Setup tftp env variables: + * select desired eth device - 'ethact' variable ["ethact=cpsw"] + (use "bdinfo" to check current setting) + * setup "serverip" and "ipaddr" variables + * set "loadaddr" as a fixed buffer where incoming data is placed + ["loadaddr=0x81000000"] + +######### +# BONUS # +######### +It is possible to use USB interface to emulate ETH connection by setting +"ethact=usb_ether". In this way one can have very fast DFU transfer via USB. + +For 33MiB test image the transfer rate was 1MiB/s for ETH over USB and 200KiB/s +for pure DFU USB transfer. + +2. Setup update_tftp variables: + * set "updatefile" - the file name to be downloaded via TFTP (stored on + the HOST at e.g. /srv/tftp) + +3. If required, to update firmware on boot, put the "dfu tftp 0 mmc 0" in the + "preboot" env variable. Otherwise use this command from u-boot prompt. + +4. Inspect "dfu" specific variables: + * "dfu_alt_info" - information about available DFU entities + * "dfu_bufsiz" - variable to set buffer size [in bytes] - when it is not + possible to set large enough default buffer (8 MiB @ BBB) + + + +FIT image format for download +----------------------------- + +To create FIT image for download one should follow the update tftp README file +(./doc/README.update) with one notable difference: + +The original snippet of ./doc/uImage.FIT/update_uboot.its + + images { + update@1 { + description = "U-Boot binary"; + +should look like + + images { + u-boot.bin@1 { + description = "U-Boot binary"; + +where "u-boot.bin" is the DFU entity name to be stored. + + + +To do +----- + +* Extend dfu-util command to support TFTP based transfers +* Upload support (via TFTP) diff --git a/doc/README.fec_mxc b/doc/README.fec_mxc index 72a1d59..30e05da 100644 --- a/doc/README.fec_mxc +++ b/doc/README.fec_mxc @@ -1,7 +1,8 @@ U-boot config options used in fec_mxc.c CONFIG_FEC_MXC - Selects fec_mxc.c to be compiled into u-boot. + Selects fec_mxc.c to be compiled into u-boot. Can read out the + ethaddr from the SoC eFuses (see below). CONFIG_MII Must be defined if CONFIG_FEC_MXC is defined. @@ -25,3 +26,9 @@ CONFIG_FEC_MXC_NO_ANEG CONFIG_FEC_MXC_PHYADDR Optional, selects the exact phy address that should be connected and function fecmxc_initialize will try to initialize it. + + +Reading the ethaddr from the SoC eFuses: +if CONFIG_FEC_MXC is defined and the U-Boot environment does not contain the +ethaddr variable, then its value gets read from the corresponding eFuses in +the SoC. See the README files of the specific SoC for details. diff --git a/doc/README.imx5 b/doc/README.imx5 index c5312b6..ea0e144 100644 --- a/doc/README.imx5 +++ b/doc/README.imx5 @@ -26,3 +26,15 @@ i.MX5x SoCs. 2.1 MAC Address: It is stored in the words 9 to 14 of fuse bank 1, using the natural MAC byte order (i.e. MSB first). + + This is an example how to program an example MAC address 01:23:45:67:89:ab + into the eFuses. Assure that the programming voltage is available and then + execute: + + => fuse prog -y 1 9 01 23 45 67 89 ab + + After programming a MAC address, consider locking the MAC fuses. This is + done by programming the MAC_ADDR_LOCK fuse, which is bit 4 of word 0 in + bank 1: + + => fuse prog -y 1 0 10 diff --git a/doc/README.omap3 b/doc/README.omap3 index a62c357..e09ac03 100644 --- a/doc/README.omap3 +++ b/doc/README.omap3 @@ -68,10 +68,6 @@ make make cm_t35_config make -* BlueLYNX-X: - -make omap3_mvblx_config -make Custom commands =============== diff --git a/doc/README.pxe b/doc/README.pxe index f67605c..bd175eb 100644 --- a/doc/README.pxe +++ b/doc/README.pxe @@ -155,6 +155,13 @@ fdt <path> - if this label is chosen, use tftp to retrieve the fdt blob the fdt_addr_r environment variable, and that address will be passed to bootm. +fdtdir <path> - if this label is chosen, use tftp to retrieve a fdt blob + relative to <path>. If the fdtfile environment variable + is set, <path>/<fdtfile> is retrieved. Otherwise, the + filename is generated from the soc and board environment + variables, i.e. <path>/<soc>-<board>.dtb is retrieved. + If the fdt command is specified, fdtdir is ignored. + localboot <flag> - Run the command defined by "localcmd" in the environment. <flag> is ignored and is only here to match the syntax of PXELINUX config files. @@ -163,7 +170,7 @@ Example ------- Here's a couple of example files to show how this works. -------------/tftpboot/pxelinux.cfg/menus/linux.list---------- +------------/tftpboot/pxelinux.cfg/menus/base.menu----------- menu title Linux selections # This is the default label diff --git a/doc/README.rockchip b/doc/README.rockchip new file mode 100644 index 0000000..87ce9d2 --- /dev/null +++ b/doc/README.rockchip @@ -0,0 +1,247 @@ +# +# Copyright (C) 2015 Google. Inc +# Written by Simon Glass <sjg@chromium.org> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +U-Boot on Rockchip +================== + +There are several repositories available with versions of U-Boot that support +many Rockchip devices [1] [2]. + +The current mainline support is experimental only and is not useful for +anything. It should provide a base on which to build. + +So far only support for the RK3288 is provided. + + +Prerequisites +============= + +You will need: + + - Firefly RK3288 baord + - Power connection to 5V using the supplied micro-USB power cable + - Separate USB serial cable attached to your computer and the Firefly + (connect to the micro-USB connector below the logo) + - rkflashtool [3] + - openssl (sudo apt-get install openssl) + - Serial UART connection [4] + - Suitable ARM cross compiler, e.g.: + sudo apt-get install gcc-4.7-arm-linux-gnueabi + + +Building +======== + +At present three RK3288 boards are supported: + + - Firefly RK3288 - use firefly-rk3288 configuration + - Radxa Rock 2 - also uses firefly-rk3288 configuration + - Haier Chromebook - use chromebook_jerry configuration + +For example: + + CROSS_COMPILE=arm-linux-gnueabi- make O=firefly firefly-rk3288_defconfig all + +(or you can use another cross compiler if you prefer) + +Note that the Radxa Rock 2 uses the Firefly configuration for now as +device tree files are not yet available for the Rock 2. Clearly the two +have hardware differences, so this approach will break down as more drivers +are added. + + +Writing to the board with USB +============================= + +For USB to work you must get your board into ROM boot mode, either by erasing +your MMC or (perhaps) holding the recovery button when you boot the board. +To erase your MMC, you can boot into Linux and type (as root) + + dd if=/dev/zero of=/dev/mmcblk0 bs=1M + +Connect your board's OTG port to your computer. + +To create a suitable image and write it to the board: + + ./firefly-rk3288/tools/mkimage -T rkimage -d \ + ./firefly-rk3288/spl/u-boot-spl-dtb.bin out && \ + cat out | openssl rc4 -K 7c4e0304550509072d2c7b38170d1711 | rkflashtool l + +If all goes well you should something like: + + U-Boot SPL 2015.07-rc1-00383-ge345740-dirty (Jun 03 2015 - 10:06:49) + Card did not respond to voltage select! + spl: mmc init failed with error: -17 + ### ERROR ### Please RESET the board ### + +You will need to reset the board before each time you try. Yes, that's all +it does so far. If support for the Rockchip USB protocol or DFU were added +in SPL then we could in principle load U-Boot and boot to a prompt from USB +as several other platforms do. However it does not seem to be possible to +use the existing boot ROM code from SPL. + + +Booting from an SD card +======================= + +To write an image that boots from an SD card (assumed to be /dev/sdc): + + ./firefly-rk3288/tools/mkimage -T rksd -d \ + firefly-rk3288/spl/u-boot-spl-dtb.bin out && \ + sudo dd if=out of=/dev/sdc seek=64 && \ + sudo dd if=firefly-rk3288/u-boot-dtb.img of=/dev/sdc seek=256 + +This puts the Rockchip header and SPL image first and then places the U-Boot +image at block 256 (i.e. 128KB from the start of the SD card). This +corresponds with this setting in U-Boot: + + #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 256 + +Put this SD (or micro-SD) card into your board and reset it. You should see +something like: + + U-Boot SPL 2015.07-rc1-00383-ge345740-dirty (Jun 03 2015 - 11:04:40) + + + U-Boot 2015.07-rc1-00383-ge345740-dirty (Jun 03 2015 - 11:04:40) + + DRAM: 2 GiB + MMC: + Using default environment + + In: serial@ff690000 + Out: serial@ff690000 + Err: serial@ff690000 + => + + +Booting from SPI +================ + +To write an image that boots from SPI flash (e.g. for the Haier Chromebook): + + ./chromebook_jerry/tools/mkimage -T rkspi -d chromebook_jerry/spl/u-boot-spl-dtb.bin out + dd if=spl.bin of=out.bin bs=128K conv=sync + cat chromebook_jerry/u-boot-dtb.img out.bin + dd if=out.bin of=out.bin.pad bs=4M conv=sync + +This converts the SPL image to the required SPI format by adding the Rockchip +header and skipping every 2KB block. Then the U-Boot image is written at +offset 128KB and the whole image is padded to 4MB which is the SPI flash size. +The position of U-Boot is controlled with this setting in U-Boot: + + #define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) + +If you have a Dediprog em100pro connected then you can write the image with: + + sudo em100 -s -c GD25LQ32 -d out.bin.pad -r + +When booting you should see something like: + + U-Boot SPL 2015.07-rc2-00215-g9a58220-dirty (Jun 23 2015 - 12:11:32) + + + U-Boot 2015.07-rc2-00215-g9a58220-dirty (Jun 23 2015 - 12:11:32 -0600) + + Model: Google Jerry + DRAM: 2 GiB + MMC: + Using default environment + + In: serial@ff690000 + Out: serial@ff690000 + Err: serial@ff690000 + => + + +Future work +=========== + +Immediate priorities are: + +- GPIO (driver exists but is lightly tested) +- I2C (driver exists but is non-functional) +- USB host +- USB device +- PMIC and regulators (only ACT8846 is supported at present) +- LCD and HDMI +- Run CPU at full speed +- Ethernet +- NAND flash +- Support for other Rockchip parts +- Boot U-Boot proper over USB OTG (at present only SPL works) + + +Development Notes +================= + +There are plenty of patches in the links below to help with this work. + +[1] https://github.com/rkchrome/uboot.git +[2] https://github.com/linux-rockchip/u-boot-rockchip.git branch u-boot-rk3288 +[3] https://github.com/linux-rockchip/rkflashtool.git +[4] http://wiki.t-firefly.com/index.php/Firefly-RK3288/Serial_debug/en + +rkimage +------- + +rkimage.c produces an SPL image suitable for sending directly to the boot ROM +over USB OTG. This is a very simple format - just the string RK32 (as 4 bytes) +followed by u-boot-spl-dtb.bin. + +The boot ROM loads image to 0xff704000 which is in the internal SRAM. The SRAM +starts at 0xff700000 and extends to 0xff718000 where we put the stack. + +rksd +---- + +rksd.c produces an image consisting of 32KB of empty space, a header and +u-boot-spl-dtb.bin. The header is defined by 'struct header0_info' although +most of the fields are unused by U-Boot. We just need to specify the +signature, a flag and the block offset and size of the SPL image. + +The header occupies a single block but we pad it out to 4 blocks. The header +is encoding using RC4 with the key 7c4e0304550509072d2c7b38170d1711. The SPL +image can be encoded too but we don't do that. + +The maximum size of u-boot-spl-dtb.bin which the boot ROM will read is 32KB, +or 0x40 blocks. This is a severe and annoying limitation. There may be a way +around this limitation, since there is plenty of SRAM, but at present the +board refuses to boot if this limit is exceeded. + +The image produced is padded up to a block boundary (512 bytes). It should be +written to the start of an SD card using dd. + +Since this image is set to load U-Boot from the SD card at block offset, +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, dd should be used to write +u-boot-dtb.img to the SD card at that offset. See above for instructions. + +rkspi +----- + +rkspi.c produces an image consisting of a header and u-boot-spl-dtb.bin. The +resulting image is then spread out so that only the first 2KB of each 4KB +sector is used. The header is the same as with rksd and the maximum size is +also 32KB (before spreading). The image should be written to the start of +SPI flash. + +See above for instructions on how to write a SPI image. + + +Device tree and driver model +---------------------------- + +Where possible driver model is used to provide a structure to the +functionality. Device tree is used for configuration. However these have an +overhead and in SPL with a 32KB size limit some shortcuts have been taken. +In general all Rockchip drivers should use these features, with SPL-specific +modifications where required. + + +-- +Simon Glass <sjg@chromium.org> +24 June 2015 diff --git a/doc/README.scrapyard b/doc/README.scrapyard index fb1ed42..9cda0bd 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,7 +12,17 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= -cam_enc_4xx arm arm926ejs - - Heiko Schocher <hs@denx.de> +stxgp3 powerpc mpc85xx - - Dan Malek <dan@embeddedalley.com> +stxssa powerpc mpc85xx - - Dan Malek <dan@embeddedalley.com> +cmi_mpc5xx powerpc mpc5xx - - +zeus powerpc ppc4xx - - Stefan Roese <sr@denx.de> +sbc405 powerpc ppc4xx - - +pcs440ep powerpc ppc4xx - - Stefan Roese <sr@denx.de> +p3p440 powerpc ppc4xx - - Stefan Roese <sr@denx.de> +lwmon5 powerpc ppc4xx - - Stefan Roese <sr@denx.de> +csb272/csb472 powerpc ppc4xx - - Tolunay Orkun <torkun@nextio.com> +alpr powerpc ppc4xx - - Stefan Roese <sr@denx.de> +cam_enc_4xx arm arm926ejs 8d775763 2015-08-20 Heiko Schocher <hs@denx.de> atstk1003 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen@atmel.com> atstk1004 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen@atmel.com> atstk1006 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen@atmel.com> diff --git a/doc/README.switch_config b/doc/README.switch_config deleted file mode 100644 index f890373..0000000 --- a/doc/README.switch_config +++ /dev/null @@ -1,25 +0,0 @@ -On the enbw_cmc board is a KSZ8864RMN switch which needs -configured through spi before working. This is done on -startup from u-boot through a config file stored at an -address specified in the "hwconfig" environment variable, -subcommand "config". - -For example on the enbw_cmc board: - -hwconfig=switch:lan=on,pwl=off,config=0x60160000 - -The file has the following structure: - -- a comment starts with a '#' or a ';' and ends with a newline -- The switch needs for its config a reg/value pair, so we - have two columns in the file: - reg : contains the register address - value: contains a 8 bit register value - This 2 columns are seperated through space or tab. - -example (minimal configuration on the enbw_cmc board): - -;reg value comment -;----------------------------------------- -0x01 0x00 -0x01 0x01 ; Start Switch with this configuration diff --git a/doc/README.update b/doc/README.update index a7f4d9e..eab124c 100644 --- a/doc/README.update +++ b/doc/README.update @@ -93,3 +93,10 @@ Example .its files An example containing three updates. It can be used to update Linux kernel, ramdisk and FDT blob stored in Flash. The procedure for preparing the update file is similar to the example above. + +TFTP update via DFU +------------------- + +- It is now possible to update firmware (bootloader, kernel, rootfs, etc.) via + TFTP by using DFU (Device Firmware Upgrade). More information can be found in + ./doc/README.dfutftp documentation entry. diff --git a/doc/README.watchdog b/doc/README.watchdog index 59f306b..b66fd6c 100644 --- a/doc/README.watchdog +++ b/doc/README.watchdog @@ -27,6 +27,7 @@ CONFIG_IMX_WATCHDOG Available for i.mx31/35/5x/6x to service the watchdog. This is not automatically set because some boards (vision2) still need to define their own hw_watchdog_reset routine. + TODO: vision2 is removed now, so perhaps this can be changed. CONFIG_XILINX_TB_WATCHDOG Available for Xilinx Axi platforms to service timebase watchdog timer. diff --git a/doc/README.x86 b/doc/README.x86 index 3bab5cf..5f9c46f 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -189,7 +189,7 @@ Offset Description Controlling config 001000 me.bin Set by the descriptor 500000 <spare> 700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE -790000 vga.bin CONFIG_X86_OPTION_ROM_ADDR +790000 vga.bin CONFIG_VGA_BIOS_ADDR 7c0000 fsp.bin CONFIG_FSP_ADDR 7f8000 <spare> (depends on size of fsp.bin) 7fe000 Environment CONFIG_ENV_OFFSET diff --git a/doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt b/doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt new file mode 100644 index 0000000..0c2bf5e --- /dev/null +++ b/doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt @@ -0,0 +1,61 @@ +* Rockchip RK3188/RK3066 Clock and Reset Unit + +The RK3188/RK3066 clock controller generates and supplies clock to various +controllers within the SoC and also implements a reset controller for SoC +peripherals. + +Required Properties: + +- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or + "rockchip,rk3066a-cru" +- reg: physical base address of the controller and length of memory mapped + region. +- #clock-cells: should be 1. +- #reset-cells: should be 1. + +Optional Properties: + +- rockchip,grf: phandle to the syscon managing the "general register files" + If missing pll rates are not changable, due to the missing pll lock status. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/rk3188-cru.h and +dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources. +Similar macros exist for the reset sources in these files. + +External clocks: + +There are several clocks that are generated outside the SoC. It is expected +that they are defined using standard clock bindings with following +clock-output-names: + - "xin24m" - crystal input - required, + - "xin32k" - rtc clock - optional, + - "xin27m" - 27mhz crystal input on rk3066 - optional, + - "ext_hsadc" - external HSADC clock - optional, + - "ext_cif0" - external camera clock - optional, + - "ext_rmii" - external RMII clock - optional, + - "ext_jtag" - externalJTAG clock - optional + +Example: Clock controller node: + + cru: cru@20000000 { + compatible = "rockchip,rk3188-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + +Example: UART controller node that consumes the clock generated by the clock + controller: + + uart0: serial@10124000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10124000 0x400>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&cru SCLK_UART0>; + }; diff --git a/doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt b/doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt new file mode 100644 index 0000000..c9fbb76 --- /dev/null +++ b/doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt @@ -0,0 +1,61 @@ +* Rockchip RK3288 Clock and Reset Unit + +The RK3288 clock controller generates and supplies clock to various +controllers within the SoC and also implements a reset controller for SoC +peripherals. + +Required Properties: + +- compatible: should be "rockchip,rk3288-cru" +- reg: physical base address of the controller and length of memory mapped + region. +- #clock-cells: should be 1. +- #reset-cells: should be 1. + +Optional Properties: + +- rockchip,grf: phandle to the syscon managing the "general register files" + If missing pll rates are not changable, due to the missing pll lock status. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be +used in device tree sources. Similar macros exist for the reset sources in +these files. + +External clocks: + +There are several clocks that are generated outside the SoC. It is expected +that they are defined using standard clock bindings with following +clock-output-names: + - "xin24m" - crystal input - required, + - "xin32k" - rtc clock - optional, + - "ext_i2s" - external I2S clock - optional, + - "ext_hsadc" - external HSADC clock - optional, + - "ext_edp_24m" - external display port clock - optional, + - "ext_vip" - external VIP clock - optional, + - "ext_isp" - external ISP clock - optional, + - "ext_jtag" - external JTAG clock - optional + +Example: Clock controller node: + + cru: cru@20000000 { + compatible = "rockchip,rk3188-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + +Example: UART controller node that consumes the clock generated by the clock + controller: + + uart0: serial@10124000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10124000 0x400>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&cru SCLK_UART0>; + }; diff --git a/doc/device-tree-bindings/clock/rockchip,rk3288-dmc.txt b/doc/device-tree-bindings/clock/rockchip,rk3288-dmc.txt new file mode 100644 index 0000000..2ca9db7 --- /dev/null +++ b/doc/device-tree-bindings/clock/rockchip,rk3288-dmc.txt @@ -0,0 +1,155 @@ +Rockchip Dynamic Memory Controller Driver +Required properties: +- compatible: "rockchip,rk3288-dmc", "syscon" +- rockchip,cru: this driver should access cru regs, so need get cru here +- rockchip,grf: this driver should access grf regs, so need get grf here +- rockchip,pmu: this driver should access pmu regs, so need get pmu here +- rockchip,sgrf: this driver should access sgrf regs, so need get sgrf here +- rockchip,noc: this driver should access noc regs, so need get noc here +- reg: dynamic ram protocol controller(PCTL) address and phy controller(PHYCTL) address +- clock: must include clock specifiers corresponding to entries in the clock-names property. +- clock-output-names: from common clock binding to override the default output clock name + Must contain + pclk_ddrupctl0: support clock for access protocol controller registers of channel 0 + pclk_publ0: support clock for access phy controller registers of channel 0 + pclk_ddrupctl1: support clock for access protocol controller registers of channel 1 + pclk_publ1: support clock for access phy controller registers of channel 1 + arm_clk: for get arm frequency +-logic-supply: this driver should adjust VDD_LOGIC according to dmc frequency, so need get logic-supply here +-timings: + Must contain + rockchip,odt-disable-freq: if ddr clock frequency low than odt-disable-freq,this driver should disable DDR ODT + rockchip,dll-disable-freq: if ddr clock frequency low than dll-disable-freq,this driver should disable DDR DLL + rockchip,sr-enable-freq: if ddr clock frequency high than sr-enable-freq,this driver should enable the automatic self refresh function + rockchip,pd-enable-freq: if ddr clock frequency high than pd-enable-freq,this driver should enable the automatic power down function + rockchip,auto-self-refresh-cnt: Self Refresh idle period. Memories are placed into Self-Refresh mode if the NIF is idle in Access state for auto-self-refresh-cnt * 32 * n_clk cycles.The automatic self refresh function is disabled when auto-self-refresh-cnt=0. + rockchip,auto-power-down-cnt: Power-down idle period. Memories are placed into power-down mode if the NIF is idle for auto-power-down-cnt n_clk cycles.The automatic power down function is disabled when auto-power-down-cnt=0. + rockchip,ddr-speed-bin: DDR3 type,AC timing parameters from the memory data-sheet + 0.DDR3_800D (5-5-5) + 1.DDR3_800E (6-6-6) + 2.DDR3_1066E (6-6-6) + 3.DDR3_1066F (7-7-7) + 4.DDR3_1066G (8-8-8) + 5.DDR3_1333F (7-7-7) + 6.DDR3_1333G (8-8-8) + 7.DDR3_1333H (9-9-9) + 8.DDR3_1333J (10-10-10) + 9.DDR3_1600G (8-8-8) + 10.DDR3_1600H (9-9-9) + 11.DDR3_1600J (10-10-10) + 12.DDR3_1600K (11-11-11) + 13.DDR3_1866J (10-10-10) + 14.DDR3_1866K (11-11-11) + 15.DDR3_1866L (12-12-12) + 16.DDR3_1866M (13-13-13) + 17.DDR3_2133K (11-11-11) + 18.DDR3_2133L (12-12-12) + 19.DDR3_2133M (13-13-13) + 20.DDR3_2133N (14-14-14) + 21.DDR3_DEFAULT + rockchip,trcd: tRCD,AC timing parameters from the memory data-sheet + rockchip,trp: tRP,AC timing parameters from the memory data-sheet +-rockchip,num-channels: number of SDRAM channels (1 or 2) +-rockchip,pctl-timing: parameters for the SDRAM setup, in this order: + togcnt1u + tinit + trsth + togcnt100n + trefi + tmrd + trfc + trp + trtw + tal + tcl + tcwl + tras + trc + trcd + trrd + trtp + twr + twtr + texsr + txp + txpdll + tzqcs + tzqcsi + tdqs + tcksre + tcksrx + tcke + tmod + trstl + tzqcl + tmrr + tckesr + tdpd +-rockchip,phy-timing: PHY timing information in this order: + dtpr0 + dtpr1 + dtpr2 + mr0..mr3 +-rockchip,sdram-channel: SDRAM channel information, each 8 bits. Both channels +will be set up the same. The parameters are in this order: + rank + col + bk + bw + dbw + row_3_4 + cs0_row + cs1_row +- rockchip,sdram-params: SDRAM base parameters, in this order: + NOC timing - value for ddrtiming register + NOC activate - value for activate register + ddrconf - value for ddrconf register + DDR frequency in MHz + DRAM type (3=DDR3, 6=LPDDR3) + stride - stride value for soc_con2 register + odt - 1 to enable DDR ODT, 0 to disable + +Example: + dmc: dmc@ff610000 { + compatible = "rockchip,rk3288-dmc", "syscon"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmu>; + rockchip,sgrf = <&sgrf>; + rockchip,noc = <&noc>; + reg = <0xff610000 0x3fc + 0xff620000 0x294 + 0xff630000 0x3fc + 0xff640000 0x294>; + clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>, + <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>, + <&cru ARMCLK>; + clock-names = "pclk_ddrupctl0", "pclk_publ0", + "pclk_ddrupctl1", "pclk_publ1", + "arm_clk"; + }; + + &dmc { + logic-supply = <&vdd_logic>; + timings { + rockchip,odt-disable-freq = <333000000>; + rockchip,dll-disable-freq = <333000000>; + rockchip,sr-enable-freq = <333000000>; + rockchip,pd-enable-freq = <666000000>; + rockchip,auto-self-refresh-cnt = <0>; + rockchip,auto-power-down-cnt = <64>; + rockchip,ddr-speed-bin = <21>; + rockchip,trcd = <10>; + rockchip,trp = <10>; + }; + rockchip,num-channels = <2>; + rockchip,pctl-timing = <0x29a 0x1f4 0xc8 0x42 0x4e 0x4 0xea 0xa + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 + 0x5 0x0>; + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 + 0xa60 0x40 0x10 0x0>; + rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf>; + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; + }; diff --git a/doc/device-tree-bindings/clock/rockchip.txt b/doc/device-tree-bindings/clock/rockchip.txt new file mode 100644 index 0000000..22f6769 --- /dev/null +++ b/doc/device-tree-bindings/clock/rockchip.txt @@ -0,0 +1,77 @@ +Device Tree Clock bindings for arch-rockchip + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +== Gate clocks == + +These bindings are deprecated! +Please use the soc specific CRU bindings instead. + +The gate registers form a continuos block which makes the dt node +structure a matter of taste, as either all gates can be put into +one gate clock spanning all registers or they can be divided into +the 10 individual gates containing 16 clocks each. +The code supports both approaches. + +Required properties: +- compatible : "rockchip,rk2928-gate-clk" +- reg : shall be the control register address(es) for the clock. +- #clock-cells : from common clock binding; shall be set to 1 +- clock-output-names : the corresponding gate names that the clock controls +- clocks : should contain the parent clock for each individual gate, + therefore the number of clocks elements should match the number of + clock-output-names + +Example using multiple gate clocks: + + clk_gates0: gate-clk@200000d0 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d0 0x4>; + clocks = <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>, + <&dummy>, <&dummy>; + + clock-output-names = + "gate_core_periph", "gate_cpu_gpll", + "gate_ddrphy", "gate_aclk_cpu", + "gate_hclk_cpu", "gate_pclk_cpu", + "gate_atclk_cpu", "gate_i2s0", + "gate_i2s0_frac", "gate_i2s1", + "gate_i2s1_frac", "gate_i2s2", + "gate_i2s2_frac", "gate_spdif", + "gate_spdif_frac", "gate_testclk"; + + #clock-cells = <1>; + }; + + clk_gates1: gate-clk@200000d4 { + compatible = "rockchip,rk2928-gate-clk"; + reg = <0x200000d4 0x4>; + clocks = <&xin24m>, <&xin24m>, + <&xin24m>, <&dummy>, + <&dummy>, <&xin24m>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>, + <&xin24m>, <&dummy>; + + clock-output-names = + "gate_timer0", "gate_timer1", + "gate_timer2", "gate_jtag", + "gate_aclk_lcdc1_src", "gate_otgphy0", + "gate_otgphy1", "gate_ddr_gpll", + "gate_uart0", "gate_frac_uart0", + "gate_uart1", "gate_frac_uart1", + "gate_uart2", "gate_frac_uart2", + "gate_uart3", "gate_frac_uart3"; + + #clock-cells = <1>; + }; diff --git a/doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt b/doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt new file mode 100644 index 0000000..388b213 --- /dev/null +++ b/doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt @@ -0,0 +1,157 @@ +* Rockchip Pinmux Controller + +The Rockchip Pinmux Controller, enables the IC +to share one PAD to several functional blocks. The sharing is done by +multiplexing the PAD input/output signals. For each PAD there are several +muxing options with option 0 being the use as a GPIO. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The Rockchip pin configuration node is a node of a group of pins which can be +used for a specific device or function. This node represents both mux and +config of the pins in that group. The 'pins' selects the function mode(also +named pin mode) this pin can work on and the 'config' configures various pad +settings such as pull-up, etc. + +The pins are grouped into up to 5 individual pin banks which need to be +defined as gpio sub-nodes of the pinmux controller. + +Required properties for iomux controller: + - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl" + "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl" + "rockchip,rk3288-pinctrl" + - rockchip,grf: phandle referencing a syscon providing the + "general register files" + +Optional properties for iomux controller: + - rockchip,pmu: phandle referencing a syscon providing the pmu registers + as some SoCs carry parts of the iomux controller registers there. + Required for at least rk3188 and rk3288. + +Deprecated properties for iomux controller: + - reg: first element is the general register space of the iomux controller + It should be large enough to contain also separate pull registers. + second element is the separate pull register space of the rk3188. + Use rockchip,grf and rockchip,pmu described above instead. + +Required properties for gpio sub nodes: + - compatible: "rockchip,gpio-bank" + - reg: register of the gpio bank (different than the iomux registerset) + - interrupts: base interrupt of the gpio bank in the interrupt controller + - clocks: clock that drives this bank + - gpio-controller: identifies the node as a gpio controller and pin bank. + - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See generic + GPIO binding documentation for description of particular cells. + - interrupt-controller: identifies the controller node as interrupt-parent. + - #interrupt-cells: the value of this property should be 2 and the interrupt + cells should use the standard two-cell scheme described in + bindings/interrupt-controller/interrupts.txt + +Deprecated properties for gpio sub nodes: + - compatible: "rockchip,rk3188-gpio-bank0" + - reg: second element: separate pull register for rk3188 bank0, use + rockchip,pmu described above instead + +Required properties for pin configuration node: + - rockchip,pins: 3 integers array, represents a group of pins mux and config + setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>. + The MUX 0 means gpio and MUX 1 to N mean the specific device function. + The phandle of a node containing the generic pinconfig options + to use, as described in pinctrl-bindings.txt in this directory. + +Examples: + +#include <dt-bindings/pinctrl/rockchip.h> + +... + +pinctrl@20008000 { + compatible = "rockchip,rk3066a-pinctrl"; + rockchip,grf = <&grf>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@20034000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20034000 0x100>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 9>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + ... + + pcfg_pull_default: pcfg_pull_default { + bias-pull-pin-default + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>, + <RK_GPIO1 9 1 &pcfg_pull_default>; + }; + }; +}; + +uart2: serial@20064000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20064000 0x400>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <1>; + clocks = <&mux_uart2>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; +}; + +Example for rk3188: + + pinctrl@20008000 { + compatible = "rockchip,rk3188-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmu>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@0x2000a000 { + compatible = "rockchip,rk3188-gpio-bank0"; + reg = <0x2000a000 0x100>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 9>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@0x2003c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003c000 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 10>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + ... + + }; diff --git a/doc/device-tree-bindings/thermal/rockchip-thermal.txt b/doc/device-tree-bindings/thermal/rockchip-thermal.txt new file mode 100644 index 0000000..ef802de --- /dev/null +++ b/doc/device-tree-bindings/thermal/rockchip-thermal.txt @@ -0,0 +1,68 @@ +* Temperature Sensor ADC (TSADC) on rockchip SoCs + +Required properties: +- compatible : "rockchip,rk3288-tsadc" +- reg : physical base address of the controller and length of memory mapped + region. +- interrupts : The interrupt number to the cpu. The interrupt specifier format + depends on the interrupt controller. +- clocks : Must contain an entry for each entry in clock-names. +- clock-names : Shall be "tsadc" for the converter-clock, and "apb_pclk" for + the peripheral clock. +- resets : Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names : Must include the name "tsadc-apb". +- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description. +- rockchip,hw-tshut-temp : The hardware-controlled shutdown temperature value. +- rockchip,hw-tshut-mode : The hardware-controlled shutdown mode 0:CRU 1:GPIO. +- rockchip,hw-tshut-polarity : The hardware-controlled active polarity 0:LOW + 1:HIGH. + +Exiample: +tsadc: tsadc@ff280000 { + compatible = "rockchip,rk3288-tsadc"; + reg = <0xff280000 0x100>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + pinctrl-names = "default"; + pinctrl-0 = <&otp_out>; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <95000>; + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; +}; + +Example: referring to thermal sensors: +thermal-zones { + cpu_thermal: cpu_thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&tsadc 1>; + + trips { + cpu_alert0: cpu_alert { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/doc/git-mailrc b/doc/git-mailrc index 598bb3e..6fe78a1 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -12,6 +12,7 @@ alias u-boot uboot # things simple and easy to look up/coordinate. alias aaribaud Albert Aribaud <albert.u.boot@aribaud.net> alias abiessmann Andreas Bießmann <andreas.devel@googlemail.com> +alias abrodkin Alexey Brodkin <alexey.brodkin@synopsys.com> alias afleming Andy Fleming <afleming@gmail.com> alias ag Anatolij Gustschin <agust@denx.de> alias alisonwang Alison Wang <alison.wang@freescale.com> @@ -50,9 +51,11 @@ alias vapier Mike Frysinger <vapier@gentoo.org> alias wd Wolfgang Denk <wd@denx.de> # Architecture aliases -alias arch arm, avr32, bfin, m68k, microblaze, mips, nds32, nios2, powerpc, sandbox, superh, sparc, x86 +alias arch arc, arm, avr32, bfin, m68k, microblaze, mips, nds32, nios2, powerpc, sandbox, superh, sparc, x86 alias arches arch +alias arc uboot, abrodkin + alias arm uboot, aaribaud alias at91 uboot, abiessmann alias davinci ti |