diff options
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/README.nios2 | 95 | ||||
| -rw-r--r-- | doc/device-tree-bindings/cpu/nios2.txt | 54 | ||||
| -rw-r--r-- | doc/device-tree-bindings/gpio/altera_pio.txt | 28 | ||||
| -rw-r--r-- | doc/device-tree-bindings/misc/altera_sysid.txt | 4 | ||||
| -rw-r--r-- | doc/device-tree-bindings/net/altera_tse.txt | 112 | ||||
| -rw-r--r-- | doc/device-tree-bindings/serial/altera_jtaguart.txt | 4 | ||||
| -rw-r--r-- | doc/device-tree-bindings/serial/altera_uart.txt | 7 | ||||
| -rw-r--r-- | doc/device-tree-bindings/spi/spi_altera.txt | 4 | ||||
| -rw-r--r-- | doc/device-tree-bindings/timer/altera_timer.txt | 19 |
9 files changed, 327 insertions, 0 deletions
diff --git a/doc/README.nios2 b/doc/README.nios2 new file mode 100644 index 0000000..2dab7d1 --- /dev/null +++ b/doc/README.nios2 @@ -0,0 +1,95 @@ +Nios II is a 32-bit embedded-processor architecture designed +specifically for the Altera family of FPGAs. + +Please refer to the link for more information on Nios II, +https://www.altera.com/products/processors/overview.html + +Please refer to the link for Linux port and toolchains, +http://rocketboards.org/foswiki/view/Documentation/NiosIILinuxUserManual + +The Nios II port of u-boot is controlled by device tree. Please check +out doc/README.fdt-control. + +To add a new board/configuration (eg, mysystem) to u-boot, you will need +three files. + +1. The device tree source which describes the hardware, dts file. + arch/nios2/dts/mysystem.dts + +2. Default configuration of Kconfig, defconfig file. + configs/mysystem_defconfig + +3. The legacy board header file. + include/configs/mysystem.h + +The device tree source must be generated from your qsys/sopc design +using the sopc2dts tool. Then modified to fit your configuration. Please +find the sopc2dts download and usage at the wiki, +http://www.alterawiki.com/wiki/Sopc2dts + +$ java -jar sopc2dts.jar --force-altr -i mysystem.sopcinfo -o mysystem.dts + +You will need to add additional properties to the dts. Please find an +example at, arch/nios2/dts/3c120_devboard.dts. + +1. Add "stdout-path=..." property with your serial path to the chosen +node, like this, + chosen { + stdout-path = &jtag_uart; + }; + +2. If you use SPI/EPCS or I2C, you will need to add aliases to number +the sequence of these devices, like this, + aliases { + spi0 = &epcs_controller; + }; + +Next, you will need a default config file. You may start with +nios2-generic_defconfig, modify the options and save it. + +$ make nios2-generic_defconfig +$ make menuconfig +$ make savedefconfig +$ cp defconfig configs/mysystem_defconfig + +You will need to change the names of board header file and device tree, +and select the drivers with menuconfig. + +Nios II architecture ---> + (mysystem) Board header file +Device Tree Control ---> + (mysystem) Default Device Tree for DT control + +There is a selection of "Provider of DTB for DT control" in the Device +Tree Control menu. + +( ) Separate DTB for DT control, will cat the dtb to end of u-boot +binary, output u-boot-dtb.bin. This should be used for production. +If you use boot copier, like EPCS boot copier, make sure the copier +copies all the u-boot-dtb.bin, not just u-boot.bin. + +( ) Embedded DTB for DT control, will include the dtb inside the u-boot +binary. This is handy for development, eg, using gdb or nios2-download. + +The last thing, legacy board header file describes those config options +not covered in Kconfig yet. You may copy it from nios2-generic.h. + +$ cp include/configs/nios2-generic.h include/configs/mysystem.h + +Please change the SDRAM base and size to match your board. The base +should be cached virtual address, for Nios II with MMU it is 0xCxxx_xxxx +to 0xDxxx_xxxx. + +#define CONFIG_SYS_SDRAM_BASE 0xD0000000 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 + +You will need to change the environment variables location and setting, +too. You may change other configs to fit your board. + +After all these changes, you may build and test. + +$ export CROSS_COMPILE=nios2-elf- (or nios2-linux-gnu-) +$ make mysystem_defconfig +$ make + +Enjoy! diff --git a/doc/device-tree-bindings/cpu/nios2.txt b/doc/device-tree-bindings/cpu/nios2.txt new file mode 100644 index 0000000..0ed2f44 --- /dev/null +++ b/doc/device-tree-bindings/cpu/nios2.txt @@ -0,0 +1,54 @@ +* Nios II Processor Binding + +This binding specifies what properties available in the device tree +representation of a Nios II Processor Core. + +Users can use sopc2dts tool for generating device tree sources (dts) from a +Qsys system. See more detail in: http://www.alterawiki.com/wiki/Sopc2dts + +Required properties: + +- compatible: Compatible property value should be "altr,nios2-1.0" or + "altr,nios2-1.1". +- reg: Contains CPU index. +- clock-frequency: Contains the clock frequency for CPU, in Hz. +- dcache-line-size: Contains data cache line size. +- icache-line-size: Contains instruction line size. +- dcache-size: Contains data cache size. +- icache-size: Contains instruction cache size. +- altr,reset-addr: Specifies CPU reset address +- altr,exception-addr: Specifies CPU exception address + +Optional properties: +- altr,has-initda: Specifies CPU support initda instruction, should be 1. +- altr,has-mmu: Specifies CPU support MMU support. +- altr,has-mul: Specifies CPU hardware multipy support. +- altr,has-div: Specifies CPU hardware divide support +- altr,implementation: Nios II core implementation, this should be "fast"; + +Example: + +cpu@0x0 { + device_type = "cpu"; + compatible = "altr,nios2-1.0"; + reg = <0>; + interrupt-controller; + #interrupt-cells = <1>; + clock-frequency = <125000000>; + dcache-line-size = <32>; + icache-line-size = <32>; + dcache-size = <32768>; + icache-size = <32768>; + altr,implementation = "fast"; + altr,pid-num-bits = <8>; + altr,tlb-num-ways = <16>; + altr,tlb-num-entries = <128>; + altr,tlb-ptr-sz = <7>; + altr,has-div = <1>; + altr,has-mul = <1>; + altr,reset-addr = <0xc2800000>; + altr,fast-tlb-miss-addr = <0xc7fff400>; + altr,exception-addr = <0xd0000020>; + altr,has-initda = <1>; + altr,has-mmu = <1>; +}; diff --git a/doc/device-tree-bindings/gpio/altera_pio.txt b/doc/device-tree-bindings/gpio/altera_pio.txt new file mode 100644 index 0000000..cf71eb2 --- /dev/null +++ b/doc/device-tree-bindings/gpio/altera_pio.txt @@ -0,0 +1,28 @@ +Altera GPIO controller bindings + +Required properties: +- compatible: + - "altr,pio-1.0" +- reg: Physical base address and length of the controller's registers. + +Optional properties: +- altr,gpio-bank-width: Width of the GPIO bank. This defines how many pins the + GPIO device has. Ranges between 1-32. Optional and defaults to 32 if not + specified. +- gpio-bank-name: bank name attached to this device. + +Example: + +user_led_pio_8out: gpio@0x4cc0 { + compatible = "altr,pio-1.0"; + reg = <0x00004cc0 0x00000010>; + resetvalue = <255>; + altr,gpio-bank-width = <8>; + #gpio-cells = <2>; + gpio-controller; + gpio-bank-name = "led"; +}; + +In this example, the gpio can be accessed as led[0..7] using gpio command of +u-boot. +==> gpio clear led0 diff --git a/doc/device-tree-bindings/misc/altera_sysid.txt b/doc/device-tree-bindings/misc/altera_sysid.txt new file mode 100644 index 0000000..54462eb --- /dev/null +++ b/doc/device-tree-bindings/misc/altera_sysid.txt @@ -0,0 +1,4 @@ +Altera sysid + +Required properties: +- compatible : should be "altr,sysid-1.0" diff --git a/doc/device-tree-bindings/net/altera_tse.txt b/doc/device-tree-bindings/net/altera_tse.txt new file mode 100644 index 0000000..cb190df --- /dev/null +++ b/doc/device-tree-bindings/net/altera_tse.txt @@ -0,0 +1,112 @@ +* Altera Triple-Speed Ethernet MAC driver (TSE) + +Required properties: +- compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should + be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE. +- reg: Address and length of the register set for the device. It contains + the information of registers in the same order as described by reg-names +- reg-names: Should contain the reg names + "control_port": MAC configuration space region + "tx_csr": xDMA Tx dispatcher control and status space region + "tx_desc": MSGDMA Tx dispatcher descriptor space region + "rx_csr" : xDMA Rx dispatcher control and status space region + "rx_desc": MSGDMA Rx dispatcher descriptor space region + "rx_resp": MSGDMA Rx dispatcher response space region + "s1": SGDMA descriptor memory +- interrupts: Should contain the TSE interrupts and it's mode. +- interrupt-names: Should contain the interrupt names + "rx_irq": xDMA Rx dispatcher interrupt + "tx_irq": xDMA Tx dispatcher interrupt +- rx-fifo-depth: MAC receive FIFO buffer depth in bytes +- tx-fifo-depth: MAC transmit FIFO buffer depth in bytes +- phy-mode: See ethernet.txt in the same directory. +- phy-handle: See ethernet.txt in the same directory. +- phy-addr: See ethernet.txt in the same directory. A configuration should + include phy-handle or phy-addr. +- altr,has-supplementary-unicast: + If present, TSE supports additional unicast addresses. + Otherwise additional unicast addresses are not supported. +- altr,has-hash-multicast-filter: + If present, TSE supports a hash based multicast filter. + Otherwise, hash-based multicast filtering is not supported. + +- mdio device tree subnode: When the TSE has a phy connected to its local + mdio, there must be device tree subnode with the following + required properties: + + - compatible: Must be "altr,tse-mdio". + - #address-cells: Must be <1>. + - #size-cells: Must be <0>. + + For each phy on the mdio bus, there must be a node with the following + fields: + + - reg: phy id used to communicate to phy. + - device_type: Must be "ethernet-phy". + +Optional properties: +- local-mac-address: See ethernet.txt in the same directory. +- max-frame-size: See ethernet.txt in the same directory. + +Example: + + tse_sub_0_eth_tse_0: ethernet@0x1,00000000 { + compatible = "altr,tse-msgdma-1.0"; + reg = <0x00000001 0x00000000 0x00000400>, + <0x00000001 0x00000460 0x00000020>, + <0x00000001 0x00000480 0x00000020>, + <0x00000001 0x000004A0 0x00000008>, + <0x00000001 0x00000400 0x00000020>, + <0x00000001 0x00000420 0x00000020>; + reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc"; + interrupt-parent = <&hps_0_arm_gic_0>; + interrupts = <0 41 4>, <0 40 4>; + interrupt-names = "rx_irq", "tx_irq"; + rx-fifo-depth = <2048>; + tx-fifo-depth = <2048>; + address-bits = <48>; + max-frame-size = <1500>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-mode = "gmii"; + altr,has-supplementary-unicast; + altr,has-hash-multicast-filter; + phy-handle = <&phy0>; + mdio { + compatible = "altr,tse-mdio"; + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { + reg = <0x0>; + device_type = "ethernet-phy"; + }; + + phy1: ethernet-phy@1 { + reg = <0x1>; + device_type = "ethernet-phy"; + }; + + }; + }; + + tse_sub_1_eth_tse_0: ethernet@0x1,00001000 { + compatible = "altr,tse-msgdma-1.0"; + reg = <0x00000001 0x00001000 0x00000400>, + <0x00000001 0x00001460 0x00000020>, + <0x00000001 0x00001480 0x00000020>, + <0x00000001 0x000014A0 0x00000008>, + <0x00000001 0x00001400 0x00000020>, + <0x00000001 0x00001420 0x00000020>; + reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc"; + interrupt-parent = <&hps_0_arm_gic_0>; + interrupts = <0 43 4>, <0 42 4>; + interrupt-names = "rx_irq", "tx_irq"; + rx-fifo-depth = <2048>; + tx-fifo-depth = <2048>; + address-bits = <48>; + max-frame-size = <1500>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-mode = "gmii"; + altr,has-supplementary-unicast; + altr,has-hash-multicast-filter; + phy-handle = <&phy1>; + }; diff --git a/doc/device-tree-bindings/serial/altera_jtaguart.txt b/doc/device-tree-bindings/serial/altera_jtaguart.txt new file mode 100644 index 0000000..97c7062 --- /dev/null +++ b/doc/device-tree-bindings/serial/altera_jtaguart.txt @@ -0,0 +1,4 @@ +Altera JTAG UART + +Required properties: +- compatible : should be "altr,juart-1.0" diff --git a/doc/device-tree-bindings/serial/altera_uart.txt b/doc/device-tree-bindings/serial/altera_uart.txt new file mode 100644 index 0000000..ebac3f5 --- /dev/null +++ b/doc/device-tree-bindings/serial/altera_uart.txt @@ -0,0 +1,7 @@ +Altera UART + +Required properties: +- compatible : should be "altr,uart-1.0" + +Optional properties: +- clock-frequency : frequency of the clock input to the UART diff --git a/doc/device-tree-bindings/spi/spi_altera.txt b/doc/device-tree-bindings/spi/spi_altera.txt new file mode 100644 index 0000000..de4fae8 --- /dev/null +++ b/doc/device-tree-bindings/spi/spi_altera.txt @@ -0,0 +1,4 @@ +Altera SPI + +Required properties: +- compatible : should be "altr,spi-1.0". diff --git a/doc/device-tree-bindings/timer/altera_timer.txt b/doc/device-tree-bindings/timer/altera_timer.txt new file mode 100644 index 0000000..904a584 --- /dev/null +++ b/doc/device-tree-bindings/timer/altera_timer.txt @@ -0,0 +1,19 @@ +Altera Timer + +Required properties: + +- compatible : should be "altr,timer-1.0" +- reg : Specifies base physical address and size of the registers. +- interrupt-parent: phandle of the interrupt controller +- interrupts : Should contain the timer interrupt number +- clock-frequency : The frequency of the clock that drives the counter, in Hz. + +Example: + +timer { + compatible = "altr,timer-1.0"; + reg = <0x00400000 0x00000020>; + interrupt-parent = <&cpu>; + interrupts = <11>; + clock-frequency = <125000000>; +}; |