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Diffstat (limited to 'doc')
| -rw-r--r-- | doc/README.Lite5200B_low_power | 22 | ||||
| -rw-r--r-- | doc/README.mpc7448hpc2 | 184 | ||||
| -rw-r--r-- | doc/README.mpc832xemds | 128 | ||||
| -rw-r--r-- | doc/README.mpc8349itx | 187 | ||||
| -rw-r--r-- | doc/README.sbc8349 | 99 |
5 files changed, 620 insertions, 0 deletions
diff --git a/doc/README.Lite5200B_low_power b/doc/README.Lite5200B_low_power new file mode 100644 index 0000000..5b04fbb --- /dev/null +++ b/doc/README.Lite5200B_low_power @@ -0,0 +1,22 @@ +Lite5200B wakeup from low-power mode (CONFIG_LITE5200B_PM) +---------------------------------------------------------- + +Low-power mode as described in Lite5200B User's Manual, means that +with support of MC68HLC908QT1 microcontroller (refered to as QT), +everything but the SDRAM can be powered down. This brings +maximum power saving, while one can still restore previous state +quickly. + +Quick overview where U-Boot comes into the picture: +- OS saves device states +- OS saves wakeup handler address to physical 0x0, puts SDRAM into + self-refresh and signals to QT, it should power down the board +- / board is sleeping here / +- someone presses SW4 (connected to QT) +- U-Boot checks PSC2_4 pin, if QT drives it down, then we woke up, + so get SDRAM out of self-refresh and transfer control to OS + wakeup handler +- OS restores device states + +This was tested on Linux with USB and Ethernet in use. Adding +support for other devices is an OS issue. diff --git a/doc/README.mpc7448hpc2 b/doc/README.mpc7448hpc2 new file mode 100644 index 0000000..8659e83 --- /dev/null +++ b/doc/README.mpc7448hpc2 @@ -0,0 +1,184 @@ +Freescale MPC7448hpc2 (Taiga) board +=================================== + +Created 08/11/2006 Roy Zang +-------------------------- +MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference +design, which is optimized for high speed throughput between the processor and +the memory, disk drive and Ethernet port subsystems. + +MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be +used in 1U or 2U rack-mount chassis¡¯, as well as in standard ATX/Micro-ATX +chassis. + +Building U-Boot +------------------ +The mpc7448hpc2 code base is known to compile using: + Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3 + + $ make mpc7448hpc2_config + Configuring for mpc7448hpc2 board... + + $ make + +Memory Map +---------- + +The memory map is setup for Linux to operate properly. + +The mapping is: + + Range Start Range End Definition Size + + 0x0000_0000 0x7fff_ffff DDR 2G + 0xe000_0000 0xe7ff_ffff PCI Memory 128M + 0xfa00_0000 0xfaff_ffff PCI IO 16M + 0xfb00_0000 0xfbff_ffff PCI Config 16M + 0xfc00_0000 0xfc0f_ffff NVRAM/CADMUS 1M + 0xfe00_0000 0xfeff_ffff PromJet 16M + 0xff00_0000 0xff80_0000 FLASH (boot flash) 8M + 0xff80_0000 0xffff_ffff FLASH (second half flash) 8M + +Using Flash +----------- + +The MPC7448hpc2 board has two "banks" of flash, each 8MB in size +(2^23 = 0x00800000). + +Note: the "bank" here refers to half of the flash. In fact, there is only one +bank of flash, which is divided into low and high half. Each is controlled by +the most significant bit of the address bus. The so called "bank" is only for +convenience. + +There is a switch which allows the "bank" to be selected. The switch +settings for updating flash are given below. + +The u-boot commands for copying the boot-bank into the secondary bank are +as follows: + + erase ff800000 ff880000 + cp.b ff000000 ff800000 80000 + +U-boot commands for downloading an image via tftp and flashing +it into the secondary bank: + + tftp 10000 <u-boot.bin.image> + erase ff000000 ff080000 + cp.b 10000 ff000000 80000 + +After copying the image into the second bank of flash, be sure to toggle +SW3[4] on board before resetting the board in order to set the +secondary bank as the boot-bank. + +Board Switches +---------------------- + +Most switches on the board should not be changed. The most frequent +user-settable switches on the board are used to configure +the flash banks and determining the PCI frequency. + +SW1[1-5]: Processor core voltage + + 12345 Core Voltage + ----- + SW1=01111 1.000V. + SW1=01101 1.100V. + SW1=01011 1.200V. + SW1=01001 1.300V only for MPC7447A. + + +SW2[1-6]: CPU core frequency + + CPU Core Frequency (MHz) + Bus Frequency + 123456 100 133 167 200 Ratio + + ------ + SW2=101100 500 667 833 1000 5x + SW2=100100 550 733 917 1100 5.5x + SW2=110100 600 800 1000 1200 6x + SW2=010100 650 866 1083 1300 6.5x + SW2=001000 700 930 1167 1400 7x + SW2=000100 750 1000 1250 1500 7.5x + SW2=110000 800 1066 1333 1600 8x + SW2=011000 850 1333 1417 1700 8.5x only for MPC7447A + SW2=011110 900 1200 1500 1800 9x + +This table shows only a subset of available frequency options; see the CPU +hardware specifications for more information. + +SW2[7-8]: Bus Protocol and CPU Reset Option + + 7 + - + SW2=0 System bus uses MPX bus protocol + SW2=1 System bus uses 60x bus protocol + + 8 + - + SW2=0 TSI108 can cause CPU reset + SW2=1 TSI108 can not cause CPU reset + +SW3[1-8] system options + + 123 + --- + SW3=xxx Connected to GPIO[0:2] on TSI108 + + 4 + - + SW3=0 CPU boots from low half of flash + SW3=1 CPU boots from high half of flash + + 5 + - + SW3=0 SATA and slot2 connected to PCI bus + SW3=1 Only slot1 connected to PCI bus + + 6 + - + SW3=0 USB connected to PCI bus + SW3=1 USB disconnected from PCI bus + + 7 + - + SW3=0 Flash is write protected + SW3=1 Flash is NOT write protected + + 8 + - + SW3=0 CPU will boot from flash + SW3=1 CPU will boot from PromJet + +SW4[1-3]: System bus frequency + + Bus Frequency (MHz) + --- + SW4=010 183 + SW4=011 100 + SW4=100 133 + SW4=101 166 only for MPC7447A + SW4=110 200 only for MPC7448 + others reserved + +SW4[4-6]: DDR2 SDRAM frequency + + Bus Frequency (MHz) + --- + SW4=000 external clock + SW4=011 system clock + SW4=100 133 + SW4=101 166 + SW4=110 200 + others reserved + +SW4[7-8]: PCI/PCI-X frequency control + 7 + - + SW4=0 PCI/PCI-X bus operates normally + SW4=1 PCI bus forced to PCI-33 mode + + 8 + - + SW4=0 PCI-X mode at 133 MHz allowed + SW4=1 PCI-X mode limited to 100 MHz diff --git a/doc/README.mpc832xemds b/doc/README.mpc832xemds new file mode 100644 index 0000000..b63cc79 --- /dev/null +++ b/doc/README.mpc832xemds @@ -0,0 +1,128 @@ +Freescale MPC832XEMDS Board +----------------------------------------- +1. Board Switches and Jumpers +1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board + For some reason, the HW designers describe the switch settings + in terms of 0 and 1, and then map that to physical switches where + the label "On" refers to logic 0 and "Off" is logic 1. + + Switch bits are numbered 1 through, like, 4 6 8 or 10, but the + bits may contribute to signals that are numbered based at 0, + and some of those signals may be high-bit-number-0 too. Heed + well the names and labels and do not get confused. + + "Off" == 1 + "On" == 0 + + SW3 is switch 18 as silk-screened onto the board. + SW4[8] is the bit labled 8 on Switch 4. + SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5. + SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6. + SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On" + and bits labeled 8 is set as "Off". + +1.1 For the MPC832XEMDS PROTO Board + + First, make sure the board default setting is consistent with the document + shipped with your board. Then apply the following setting: + SW3[1-8]= 0000_1000 (core PLL setting, core enable) + SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting) + SW5[1-8]= 0010_0110 (Boot from high end) + SW6[1-8]= 0011_0100 (Flash boot on 16 bit local bus) + SW7[1-8]= 1000_0011 (QE PLL setting) + + ENET3/4 MII mode settings: + J1 1-2 (ETH3_TXER) + J2 2-3 (MII mode) + J3 2-3 (MII mode) + J4 2-3 (ADSL clockOscillator) + J5 1-2 (ETH4_TXER) + J6 2-3 (ClockOscillator) + JP1 removed (don't force PORESET) + JP2 mounted (ETH4/2 MII) + JP3 mounted (ETH3 MII) + JP4 mounted (HRCW from BCSR) + + ENET3/4 RMII mode settings: + J1 1-2 (ETH3_TXER) + J2 1-2 (RMII mode) + J3 1-2 (RMII mode) + J4 2-3 (ADSL clockOscillator) + J5 1-2 (ETH4_TXER) + J6 2-3 (ClockOscillator) + JP1 removed (don't force PORESET) + JP2 removed (ETH4/2 RMII) + JP3 removed (ETH3 RMII) + JP4 removed (HRCW from FLASH) + + on board Oscillator: 66M + + +2. Memory Map + +2.1 The memory map should look pretty much like this: + + 0x0000_0000 0x7fff_ffff DDR 2G + 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M + 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M + 0xc000_0000 0xdfff_ffff Empty 512M + 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M + 0xe020_0000 0xe02f_ffff Empty 1M + 0xe030_0000 0xe03f_ffff PCI IO 1M + 0xe040_0000 0xefff_ffff Empty 252M + 0xf400_0000 0xf7ff_ffff Empty 64M + 0xf800_0000 0xf800_7fff BCSR on CS1 32K + 0xf800_8000 0xf800_ffff PIB CS2 32K + 0xf801_0000 0xf801_7fff PIB CS3 32K + 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M + + +3. Definitions + +3.1 Explanation of NEW definitions in: + + include/configs/MPC832XEPB.h + + CONFIG_MPC83XX MPC83XX family for MPC8349, MPC8360 and MPC832X + CONFIG_MPC832X MPC832X specific + CONFIG_MPC832XEMDS MPC832XEMDS board specific + +4. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + make MPC832XEMDS_config + make + + MPC832X support PCI 33MHz and PCI 66MHz, to make u-boot support PCI: + + 1)Make sure the DIP SW support PCI mode as described in Section 1.1. + + 2)To Make U-Boot image support PCI 33MHz, use + Make MPC832XEMDS_HOST_33_config + + 3)To Make U-Boot image support PCI 66MHz, use + Make MPC832XEMDS_HOST_66M_config + +5. Downloading and Flashing Images + +5.0 Download over network: + + tftp 10000 u-boot.bin + +5.1 Reflash U-boot Image using U-boot + + tftp 20000 u-boot.bin + protect off fe000000 fe0fffff + erase fe000000 fe0fffff + cp.b 20000 fe000000 xxxx + +You have to supply the correct byte count with 'xxxx' from the TFTP result log. +Maybe 3ffff will work too, that corresponds to the erased sectors. + + +6. Notes + 1) The console baudrate for MPC832XEMDS is 115200bps. diff --git a/doc/README.mpc8349itx b/doc/README.mpc8349itx new file mode 100644 index 0000000..4ae03ae --- /dev/null +++ b/doc/README.mpc8349itx @@ -0,0 +1,187 @@ +Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards +--------------------------------------------------- + +1. Board Description + + The MPC8349E-mITX and MPC8349E-mITX-GP are reference boards featuring + the Freescale MPC8349E processor in a Mini-ITX form factor. + + The MPC8349E-mITX-GP is an MPC8349E-mITX with the following differences: + + A) One 8MB on-board flash EEPROM chip, instead of two. + B) No SATA controller + C) No Compact Flash slot + D) No Mini-PCI slot + E) No Vitesse 7385 5-port Ethernet switch + F) No 4-port USB Type-A interface + +2. Board Switches and Jumpers + +2.0 Descriptions for all of the board jumpers can be found in the User + Guide. Of particular interest to U-Boot developers is jumper J22: + + Pos. Name Default Description + ----------------------------------------------------------------------- + A LGPL0 ON (0) HRCW source, bit 0 + B LGPL1 ON (0) HRCW source, bit 1 + C LGPL3 ON (0) HRCW source, bit 2 + D LGPL5 OFF (1) PCI_SYNC_OUT frequency + E BOOT1 ON (0) Flash EEPROM boot device + F PCI_M66EN ON (0) PCI 66MHz enable + G I2C-WP ON (0) I2C EEPROM write protection + H F_WP OFF (1) Flash EEPROM write protection + + Jumper J22.E is only for the ITX, and it decides the configuration + of the flash chips. If J22.E is ON (i.e. jumpered), then flash chip + U4 is located at address FE000000 and flash chip U7 is at FE800000. + If J22.E is OFF, then U7 is at FE000000 and U4 is at FE800000. + + For U-Boot development, J22.E can be used to switch back-and-forth + between two U-Boot images. + +3. Memory Map + +3.1. The memory map should look pretty much like this: + + 0x0000_0000 - 0x0FFF_FFFF DDR SDRAM (256 MB) + 0x8000_0000 - 0x9FFF_FFFF PCI1 memory space (512 MB) + 0xA000_0000 - 0xBFFF_FFFF PCI2 memory space (512 MB) + 0xE000_0000 - 0xEFFF_FFFF IMMR (1 MB) + 0xE200_0000 - 0xE2FF_FFFF PCI1 I/O space (16 MB) + 0xE300_0000 - 0xE3FF_FFFF PCI2 I/O space (16 MB) + 0xF000_0000 - 0xF000_FFFF Compact Flash (ITX only) + 0xF001_0000 - 0xF001_FFFF Local bus expansion slot + 0xF800_0000 - 0xF801_FFFF Vitesse 7385 Parallel Interface (ITX only) + 0xFE00_0000 - 0xFE7F_FFFF First 8MB bank of Flash memory + 0xFE80_0000 - 0xFEFF_FFFF Second 8MB bank of Flash memory (ITX only) + +3.2 Flash EEPROM layout. + + On the ITX, jumper J22.E is used to determine which flash chips are + at which address. When J22.E is switched, addresses from FE000000 + to FE7FFFFF are swapped with addresses from FE800000 to FEFFFFFF. + + On the ITX, at the normal boot address (aka HIGHBOOT): + + FE00_0000 HRCW + FE70_0000 Alternative U-Boot image + FE80_0000 Alternative HRCW + FEF0_0000 U-Boot image + FEFF_FFFF End of flash + + On the ITX, at the low boot address (LOWBOOT) + + FE00_0000 HRCW and U-Boot image + FE04_0000 U-Boot environment variables + FE80_0000 Alternative HRCW and U-Boot image + FEFF_FFFF End of flash + + On the ITX-GP, the only option is LOWBOOT and there is only one chip + + FE00_0000 HRCW and U-Boot image + FE04_0000 U-Boot environment variables + F7FF_FFFF End of flash + +4. Definitions + +4.1 Explanation of NEW definitions in: + + include/configs/MPC8349ITX.h + + CONFIG_MPC83XX MPC83xx family + CONFIG_MPC8349 MPC8349 specific + CONFIG_MPC8349ITX MPC8349E-mITX + CONFIG_MPC8349ITXGP MPC8349E-mITX-GP + +5. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + + make MPC8349ITX_config + or: + make MPC8349ITXGP_config + or: + make MPC8349ITX_LOWBOOT_config + + make + +6. Downloading and Flashing Images + +6.1 Download via tftp: + + tftp $loadaddr <uboot> + + where "<uboot>" is the path and filename, on the TFTP server, of + the U-Boot image. + +6.1 Reflash U-Boot Image using U-Boot + + setenv uboot <uboot> + run tftpflash + + where "<uboot>" is the path and filename, on the TFTP server, of + the U-Boot image. + +6.2 Using the HRCW to switch between two different U-Boot images on the ITX + + Because the ITX has 16MB of flash, it is possible to keep two U-Boot + images in flash, and use the HRCW to specify which one is to be used + when the board boots. This trick is especially effective with a + hardware debugger that can override the HRCW, such as the BDI-2000. + + When the BMS bit in the HRCW is 0, the ITX will boot the U-Boot image + at address FE000000. When the BMS bit is 1, the ITX will boot the + image at address FEF00000. + + Therefore, just put a U-Boot image at both FE000000 and FEF00000 and + change the BMS bit whenever you want to boot the other image. + + Step-by-step instructions: + + 1) Build an ITX image to be loaded at FEF00000 + + make distclean + make MPC8349ITX_config + make + + 2) Take the u-boot.bin image and flash it at FEF00000. + + tftp $loadaddr u-boot.bin + protect off all + erase FEF00000 +$filesize + cp.b $loadaddr FEF00000 $filesize + + 3) Build an ITX image to be loaded at FE000000 + + make distclean + make MPC8349ITX_LOWBOOT_config + make + + 4) Take the u-boot.bin image and flash it at FE000000. + + tftp $loadaddr u-boot.bin + protect off FE000000 +$filesize + erase FE000000 +$filesize + cp.b $loadaddr FE000000 $filesize + + The HRCW in flash is currently set to boot the image at FE000000. + + If you have a hardware debugger, configure it to set the HRCW to + B460A000 04040000 if you want to boot the image at FEF00000, or set + it to B060A000 04040000 if you want to boot the image at FE000000. + + To change the HRCW in flash to boot the image at FEF00000, use these + U-Boot commands: + + cp.b FE000000 1000 10000 ; copy 1st flash sector to 1000 + mw.b 1020 b4 8 ; modify BMS bit + protect off FE000000 +10000 + erase FE000000 +10000 + cp.b 1000 FE000000 10000 + +7. Notes + 1) The console baudrate for MPC8349EITX is 115200bps. diff --git a/doc/README.sbc8349 b/doc/README.sbc8349 new file mode 100644 index 0000000..a0ac638 --- /dev/null +++ b/doc/README.sbc8349 @@ -0,0 +1,99 @@ + + + U-Boot for Wind River SBC834x Boards + ==================================== + + +The Wind River SBC834x board is a 6U form factor (not CPCI) reference +design that uses the MPC8347E or MPC8349E processor. U-Boot support +for this board is heavily based on the existing U-Boot support for +Freescale MPC8349 reference boards. + +Support has been primarily tested on the SBC8349 version of the board, +although earlier versions were also tested on the SBC8347. The primary +difference in the two is the level of PCI functionality. + + http://www.windriver.com/products/OCD/SBC8347E_49E/ + + +Flash Details: +============== + +The flash type is intel 28F640Jx (4096x16) [one device]. Base address +is 0xFF80_0000 which is also where the Hardware Reset Configuration +Word (HRCW) is stored. Caution should be used to not overwrite the +HRCW, or "CF RCW" with a Wind River ICE will be required to restore +the HRCW and allow the board to enter background mode for further +steps in the flash process. + + +Restoring a corrupted or missing flash image: +============================================= + +Details for storing U-boot to flash using a Wind River ICE can be found +on page 19 of the board manual (request ERG-00328-001). The following +is a summary of that information: + + - Connect ICE and establish connection to it from WorkBench/OCD. + - Ensure you have background mode (BKM) in the OCD terminal window. + - Select the appropriate flash type (listed above) + - Prepare a u-boot image by using the Wind River Convert utility; + by using "Convert and Add file" on the ELF file from your build. + Convert from FFF0_0000 to FFFF_FFFF (or to FFF3_FFFF if you are + trying to preserve your old environment settings). + - Set the start address of the erase/flash process to FFF0_0000 + - Set the target RAM required to 64kB. + - Select sectors for erasing (see note on enviroment below) + - Select Erase and Reprogram. + +Note that some versions of the register files used with Workbench +would zero some TSEC registers, which inhibits ethernet operation +by u-boot when this register file is played to the target. Using +"INN" in the OCD terminal window instead of "IN" before the "GO" +will not play the register file, and allow u-boot to use the TSEC +interface while executed from the ICE "GO" command. + +Alternatively, you can locate the register file which will be named +WRS_SBC8349_PCT00328001.reg or similar) and "REM" out all the lines +beginning with "SCGA TSEC1" and "SCGA TSEC2". This allows you to +use all the remaining register file content. + +If you wish to preserve your prior U-Boot environment settings, +then convert (and erase to) 0xFFF3FFFF instead of 0xFFFFFFFF. +The size for converting (and erasing) must be at least as large +as u-boot.bin. + + +Updating U-Boot with U-Boot: +============================ + +This procedure is very similar to other boards that have u-boot installed. +Assuming that the network has been configured, and that the new u-boot.bin +has been copied to the TFTP server, the commands are: + + tftp 200000 u-boot.bin + protect off all + erase fff00000 fff3ffff + cp.b 200000 fff00000 3ffff + protect on all + + +PCI: +==== + +This board and U-Boot have been tested with PCI built in, on a SBC8349 +and confirmed that the "pci" command showed the intel e1000 that was +present in the PCI slot. Note that if a 33MHz 32bit card is inserted +in the slot, then the whole board will clock down to a 33MHz base +clock instead of the default 66MHz. This will change the baud clocks +and mess up your serial console output. If you want to use a 33MHz PCI +card, then you should build a U-Boot with #undef PCI_66M in the +include/configs/sbc8349.h and store this to flash prior to powering down +the board and inserting the 33MHz PCI card. + +By default PCI support is disabled to better support very early +revision MPC834x chips with possible PCI issues. Also PCI support is +untested on the sbc8347 variants at this point in time. + + + Paul Gortmaker, 01/2007 |